COMPOSITIONS INCLUDING PERHYDRO-POLYSILAZANE USED IN A SEMICONDUCTOR MANUFACTURING PROCESS

Abstract

A film is formed on a substrate including conductive patterns or trenches using a composition that included a solvent and perhydro-polysilazane having a weight average molecular weight of about 1,800 to 3,000 and a molecular weight distribution of more than about 2.2 to about 3.0. The film is changed into a silicon oxide film, and then an opening is formed through the silicon oxide film. A contact is formed in the opening by filling the opening with conductive material. The silicon oxide film of perhydro-polysilazane having low molecular weight becomes dense and uniform.

Description

BACKGROUND

Example embodiments relate to a composition including perhydro-polysilazane used in a semiconductor manufacturing process and a method of manufacturing a semiconductor using the same. More particularly, Example embodiments relate a composition including perhydro-polysilazane used in a semiconductor manufacturing process to form a dense and uniform film, and a method of manufacturing a semiconductor device using the composition.

The design of semiconductor devices has experienced rapid progress in accordance with the wide use of information process apparatuses such as computers. This progress has lead to the development of semiconductor devices that can function at high operating speeds and that have large storage capacities. In order to satisfy such requirements, semiconductor devices with increased density, reliability and response time are under development. Thus, the size of all kinds of patterns formed on the semiconductor devices is reduced, and the size of gaps in the patterns greatly decreases.

Generally, because various conductive patterns are formed on a silicon substrate in the semiconductor manufacturing process as transistors and various metal wirings, insulation films are interposed between the conductive patterns. The insulation film is formed on the substrate to cover the conductive patterns, and then is planarized to fill gaps between the conductive patterns. This planarizing process becomes more important in order to completely fill the gaps between the conductive patterns with the insulation film.

Boro-phosphor silicate glass (BPSG) is widely employed to form the insulation film because BPSG may effectively fill the gap between the patterns, and may have a level surface by thermally treating the BPSG after deposition of BPSG on the substrate. However, BPSG may not be easily employed because a high temperature reflow process is required in order for the deposition of BPSG to fill the gap between the patterns. Furthermore, the etching rate of BPSG is too rapid so that the insulation film composed of BPSG has little significant thickness.

To form an insulation film on a semiconductor substrate, there are processes that utilize high-density plasma chemical vapor deposition (HPD-CVD) oxide and ozone-tetra ethyl ortho silicate (O₃-TEOS). HDP-CVD oxide and O₃-TEOS are widely employed for a shallow trench isolation (STI) process or a pre-metallic dielectric (PMD) process to fabricate a semiconductor device having a design rule of below about 100 nm. However, HDP-CVD oxide and O₃-TEOS may not fill up a gap between patterns formed on a substrate.

Flowing type spin on glass (SOG) is used for forming an insulation film because SOG effectively fills gaps between patterns to thereby prevent voids from forming in the insulation film. As for the process for forming the insulation film using SOG, a polysilazane-based material is coated on a substrate including the patterns by a spin coating process and the polysilazane-based material is changed to a silicon oxide (SiO₂) film by a hardening process in which oxygen (O₂) gas and water (H₂O) vapor are provided at high temperature. Thus, when the process for forming the insulation film is performed using the polysilazane-based material, the cost of the process may be reduced. This silicon oxide film made from the polysilazane-based material is thermally and chemically stable in comparison with a conventional SOG film so that the silicon oxide film of the polysilazane-based material is effectively used as a shallow trench isolation (STI) film and an interlayer insulation film in a semiconductor manufacturing process. Japanese Laid-Open Patent Publication No. 2001-308090 and Korean Laid-Open Patent Publication No. 2002-68672 disclose methods of filling a gap between patterns using polysilazane. However, the above-mentioned polysilazane compositions have a high weight average molecular weight (greater than about 3,000). Although polysilazane having weight average molecular weight of about 5,000 may be used to fill gaps between patterns, the insulation film of this polysilazane may be porous when this polysilazane of high molecular weight is employed for a semiconductor device having a design rule of below about 20 nm. Since polysilazane having weight average molecular weight of about 5,000 typically has an average molecular size of about 4 nm. Voids may be formed in the insulation film in the insulation film when gaps between the patterns are filled with polysilazane having the average molecular size of about 4 nm. Thus, when the insulation film of polysilazane having high molecular weight is etched and cleaned to form contact holes therein, undesired portions of the insulation film might be etched, yield contact holes that are connected to each other. As a result, the failure of a semiconductor device may be caused due to electric short between contacts formed in the connected contact holes.

SUMMARY

Embodiments of the invention are to provide compositions including perhydro-polysilazane of a low molecular weight to completely fill a gap between conductive patterns formed on a substrate.

Other embodiments of the invention is to provide methods of forming a film using compositions including perhydro-polysilazane of a low molecular weight to thereby completely fill a gap between conductive patterns formed on a substrate.

Further embodiments of the invention is to provide methods of manufacturing semiconductor devices including a dense and uniform insulation film using a composition including perhydro-polysilazane of low molecular weight.

In some embodiments of present invention, compositions used in a semiconductor manufacturing process are provided. The composition comprises perhydro-polysilazane having a weight average molecular weight of about 300 to about 3,000 and a polydispersity index (the ratio of weight average molecular weight and number average molecular weight, Mw/Mn, or molecular weight distribution) of about 1.8 to about 3.0 according to the formula,

—(SiH₂NH)_n—

wherein n is a positive integer.

In other embodiments of the invention, the compositions are provided in a solution, wherein the solution comprises about 5 to about 30 percent by weight of perhydro-polysilazane, and about 70 to about 95 percent by weight of a solvent such as xylene or dibutyl ether.

In yet other embodiments of the present invention, methods of forming films using the above-described compositions and solutions are provided. Here, the films are formed using a spin coating process, and the films are changed into a silicon oxide film by heating the film and by providing an oxidizing gas to the film.

In still other embodiments of the present invention, methods of manufacturing a semiconductor device are provided. After first conductive patterns are formed on a substrate where an active region and a field region are defined, a first film is formed on the substrate to fill gaps between the first conductive patterns using a solution that includes the above-mentioned solvent and perhydro-polysilazane. A first silicon oxide film is formed from the first film by heating the first film and providing a first oxidizing gas to the first film, and then a first opening exposing the active region is formed by partially etching the first silicon oxide film. Finally, a first contact is formed in the first opening by filling the first opening with a conductive material.

In still other embodiments of present invention, compositions used in a semiconductor manufacturing process are provided. The composition comprises perhydro-polysilazane having a weight average molecular weight of about 1,800 to about 3,000 and a polydispersity index (the ratio of weight average molecular weight and number average molecular weight, Mw/Mn, or molecular weight distribution) of more than about 2.2 to about 3.0 according to the formula,

—(SiH₂NH)_n—

wherein n is a positive integer.

According to embodiments of the present invention, a semiconductor device is manufactured using compositions including perhydro-polysilazane of a low molecular weight having a weight average molecular weight of about 300 to about 3,000 and polydispersity index of about 1.8 to about 3.0. Thus, a dense and uniform film of the semiconductor device is formed using the composition including perhydro-polysilazane having low molecular weight and small molecular weight distribution. When this film is employed for an interlayer insulation film of the semiconductor device, the interlayer insulation film is not etched during a cleaning process so that contact holes formed through the interlayer insulation film are completely separated each other. As a result, contact plugs formed in the contact holes are completely insulated each other, thereby improving the reliability of the semiconductor device.

BRIEF DESCRIPTION OF THE DRAWINGS

Example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings. FIGS. 1 to 10 represent non-limiting, example embodiments as described herein.

FIGS. 1A to 1E are cross sectional views illustrating a method of forming a field oxide film in a trench of a semiconductor substrate according to one example of the present invention;

FIG. 2A is plan view illustrating a semiconductor device manufactured by the method described in FIGS. 1A to 1E;

FIGS. 2B to 2J are cross sectional views illustrating the method of forming the semiconductor device taken along a line of A-A′ in FIG. 2A;

FIG. 3A is a schematic cross sectional view illustrating a step of filling a gap between transistors in accordance with one example of the present invention;

FIG. 3B is a schematic cross sectional view illustrating a step of filing a gap between the transistors in accordance with a comparative example of the present invention;

FIG. 4A is a schematic plan view illustrating a semiconductor device according to one comparative example of the present invention;

FIGS. 4B to 4J are cross sectional views illustrating a method of forming the semiconductor device taken along line of B-B′ in FIG. 4A;

FIG. 5A is a cross sectional photo illustrating a first interlayer insulation film obtained using a transmission electron microscope (TEM) according to one example of the present invention;

FIG. 5B is a cross sectional photo illustrating a first interlayer insulation film obtained using a TEM according to one comparative example of the present invention; and

FIG. 6 is a graph illustrating the number of bit fails generated in a semiconductor device of 256M in accordance with the example and the comparative example of the present invention.

FIG. 7A is a scanning electron microscope (SEM) picture illustrating a silicon oxide film formed using perhydro-polysilazane having a weight average molecular weight of about 2,300 and a polydispersity index of about 2.4

FIG. 7B is a scanning electron microscope (SEM) picture illustrating a silicon oxide film formed using perhydro-polysilazane having a weight average molecular weight of about 3,040 and a polydispersity index of about 2.4.

DETAILED DESCRIPTION

Various example embodiments will be described more fully hereinafter with reference to the accompanying drawings, in which some example embodiments are shown. The present invention may, however, be embodied in many different forms and should not be construed as limited to the example embodiments set forth herein. Rather, these example embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. In the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity.

It will be understood that when an element or layer is referred to as being “on,” “connected to” or “coupled to” another element or layer, it can be directly on, connected or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly connected to” or “directly coupled to” another element or layer, there are no intervening elements or layers present. Like numerals refer to like elements throughout. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

It will be understood that, although the terms first, second, third etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary term “below” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

Example embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized example embodiments (and intermediate structures). As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, example embodiments should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present invention.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Hereinafter, example embodiments will be explained in detail with reference to the accompanying drawings.

The perhydro-polysilazane of the present invention has low molecular weight. In a preferred embodiment, the composition of the present invention includes perhydro-polysilazane having a weight average molecular weight of about 300 to about 3,000 and a polydispersity index (the ratio of weight average molecular weight to number average molecular weight, Mw/Mn, or molecular weight distribution) of about 1.8 to about 3.0. When the perhydro-polysilazane of the present invention is described as having “low molecular weight” herein, it is defined as having the weight average molecular weight and polydispersity index as described. When a perhydro-polysilazane is described as having “high molecular weight” herein, it is defined as having a weight average molecular weight of above about 3,000, preferably above 5,000. Perhydro-polysilazane of the present invention has the formula,

—(SiH₂NH)_n—

wherein n indicates a positive integer.

When perhydro-polysilazane has a weight average molecular weight of below about 300, perhydro-polysilazane may not have characteristics of a high molecular weight substance. Furthermore, when perhydro-polysilazane has a weight average molecular weight of above about 3,000, the average molecular size of perhydro-polysilazane is such that perhydro-polysilazane of high molecular weight may not be employed for a thin film of a semiconductor device. Thus, it is preferred that the perhydro-polysilazane of the present invention has a weight average molecular weight of about 300 to about 3,000.

Meanwhile, when perhydro-polysilazane has a polydispersity index of below about 1.8, the porosity of perhydro-polysilazane molecules increases to generate pores or voids in a film of perhydro-polysilazane because the molecular weight distribution of perhydro-polysilazane becomes relatively uniform. However, when perhydro-polysilazane has a polydispersity index of above about 3.0, the film of perhydro-polysilazane has deteriorated uniformity although the porosity of perhydro-polysilazane molecules decreases. Therefore, it is preferred that the perhydro-polysilazane of the present invention has a polydispersity index of about 1.8 to about 3.0.

Furthermore, the perhydro-polysilazane of low molecular weight of the present invention has a small molecular size. The average molecular size of the perhydro-polysilazane should be such as to effectively fill gaps between conductive patterns on a semiconductor substrate below about 20 nm. In another preferred embodiment, the average molecular size of the perhydro-polysilazane is below about 4 nm, and preferably about 2 nm.

According to the present invention, the composition employed in a semiconductor manufacturing process is provided as a solution that includes perhydro-polysilazane and a solvent. In yet another preferred embodiment, the solution of the present invention includes about 5 to about 30 percent by weight perhydro-polysilazane and about 70 to about 95 percent by weight solvent. Examples of the solvent include, but are not limited to, xylene and dibutyl ether.

When the solution includes below about 5 percent by weight perhydro-polysilazane and above 95 percent by weight solvent, the solution may have insufficient viscosity for preparing a film. However, when the composition includes above about 30 percent by weight perhydro-polysilazane and below 70 percent by weight solvent, the solution may be too viscous for preparing a film. Thus, it is preferred that the solution of the present invention includes about 5 to about 30 percent by weight of perhydro-polysilazane and includes about 70 to 95 percent by weight solvent.

In other embodiments, the above-described composition and solution is employed in a semiconductor manufacturing process in which a semiconductor substrate is coated with the composition and solution. In some embodiments a spin coating process to thereby form a film on the substrate. In still other embodiments, the film is hardened by heating and providing an oxidizing gas such as an oxygen gas and a water vapor to the film. Heating may be performed at a temperature above about 600° C., and preferably at a temperature of about 700° C. After forming the film, defects such as impurities or particles on the film may be measured using a conventional optical inspection apparatus.

Having described the invention, the same will be illustrated with reference to the following examples, which are included herein for illustrative purposes only, and which are not meant to be limiting of the invention.

EXAMPLE 1

A composition for manufacturing a semiconductor device was prepared to include perhydro-polysilazane having a weight average molecular weight (Mw) of about 1,800, a number average molecular weight (Mn) of about 800 and a polydispersity index (Mw/Mn, or molecular weight distribution) of about 2.2. The molecules of perhydro-polysilazane had an average molecular size of about 2 nm and a size range of about 0.5 to about 4 nm. A solution was prepared by mixing perhydro-polysilazane with a solvent of dibutyl ether. The solution included was about 14 percent by weight perhydro-polysilazane. The viscosity of the solution was about 1 cP. After the solution was coated on a substrate, the coated solution was hardened by providing an oxidizing gas to the coated solution, thereby forming an insulation film on the substrate. Here, the volume of the insulation film was shrunk by about 19 percent relative to the initial volume of the coated solution. The insulation film had a dielectric constant of about 4.0.

COMPARATIVE EXAMPLE 1

A composition for manufacturing a semiconductor device was prepared to include perhydro-polysilazane having a weight average molecular weight (Mw) of about 5,100, a number average molecular weight (Mn) of about 1,560 and a polydispersity index of about 3.1. The molecules of perhydro-polysilazane had an average molecular size of about 4 nm and a size range of about 0.7 to about 7 nm. A solution was prepared by mixing perhydro-polysilazane with a solvent of dibutyl ether. The solution included was about 12 percent by weight of perhydro-polysilazane. Here, the viscosity of the solution was about 1 cP.

After the solution was coated on a substrate, the coated solution was hardened by providing an oxidizing gas to the coated solution, thereby forming an insulation film on the substrate. The volume of the insulation film was shrunk by about 20 percent relative to the initial volume of the coated solution. The insulation film had a dielectric constant of about 3.9.

The insulation films of Example 1 and Comparative Example 1 had substantially identical thickness of about 3,000 Å, although the insulation films were formed using the solutions included by different weight percent of perhydro-polysilazane. Furthermore, the insulation films had the substantially identical properties such as the viscosity of about 1 cP, the volume shrinkage of about 19 and 20 percent, and the dielectric constant of about 4.0 and 3.9.

However, upon examination with the optical inspection apparatus, scores to hundreds of defects were detected on the insulation film of Example 1 while hundreds to thousands of defects were measured on the insulation film of comparative Example 1. The number of the measured defects on the insulation film of Example 1 was less than about 10 percent of that of the insulation film of Comparative Example 1.

EXAMPLE 2

FIGS. 1A to 1E are cross sectional views illustrating a method of forming an oxide film in a trench of a semiconductor device according to the embodiments of the present invention.

Referring to FIG. 1A, after a pad oxide film 202 was formed on a silicon substrate 200, a first nitride film 204 and a high temperature oxide (HTO) film 206 were sequentially formed on the pad oxide film 202.

Referring to FIG. 1B, after a photoresist pattern (not shown) was formed on the HTO film 206, a trench 210 was formed by successively etching the HTO film, 206, the first nitride film 204, the pad oxide film 202 and the substrate 200. Thus, an etched portion of the silicon substrate 200 was exposed through the trench 210. In addition, there were also exposed sidewalls of the pad oxide film 202, the first nitride film 204 and the HTO film 206.

An inner oxide film 215 was formed in the trench 210 by thermally treating the exposed portion of the silicon substrate 200 under an oxygen atmosphere. That is, the inner oxide film 215 was formed on a bottom face and on an inner sidewall of the trench 210 by reacting an oxygen gas with silicon contained in the substrate 200.

A second nitride film 225 was formed on the inner oxide film 215 and on the HTO film 206. The second nitride film 225 was also formed the exposed sidewalls of the pad oxide film 202, the first nitride film 204 and the HTO film 206.

Referring to FIG. 1C, a first film 226 was formed on the second nitride film 225 to fill up the trench 210 using the a solution according to the embodiments of the invention, the solution including perhydro-polysilazane and dibutyl ether, by a spin coating process.

Referring to FIG. 1D, the first film 226 was changed into a first oxide film 227 by hardening the first film 226 while an oxidizing gas such as an oxygen (O2) gas and a water vapor (H2O) was provided to the first film 226. Here, the first film 226 was diminished during the hardening so that the first oxide film 227 had a reduced height over the substrate 200. Hence, a construction of the first oxide film 227 was dense.

Referring to FIG. 1E, an etch back process was carried out to sequentially remove the first oxide film 227, a portion of the second nitride film 225 that is formed the substrate 200 except inside the trench 210, the HTO film 206 and the first nitride film 204 so that the first oxide film 227 remained only in the trench 210. As a result, a trench oxide film 230 is formed in the trench 210. Then, the pad oxide film 202 was removed from the substrate 200.

FIG. 2A is plan view illustrating a semiconductor device manufactured by the method described in FIGS. 1A to 1E.

Referring to FIG. 2A, a semiconductor device of the present invention included a gate line (gate electrodes) 238 disposed along a first direction, and a bit line 280 disposed along a second direction perpendicular to the first direction. The bit line 280 included a bit line contact (a first contact plug) 275a that electrically connected the bit line 280 to a first underlying contact region of a semiconductor substrate. Additionally, a second contact plug 275b was formed so as to electrically connect a capacitor to a second underlying contact region of the semiconductor substrate.

FIGS. 2B to 2J are cross sectional views illustrating a method of forming the semiconductor device taken along the line of A-A′ in FIG. 2A.

Referring to FIG. 2B, a plurality of active and field regions were defined on the semiconductor substrate 200 according to the formation of the trench oxide film 230 as described above.

After an oxide film was formed on the substrate 200 including the field and active regions, a polysilicon film was formed on the oxide film. The polysilicon film was doped with impurities to have a high impurity concentration. The doped polysilicon film and the oxide film were successively patterned using a photolithography process to form the gate electrodes 238 including gate oxide film patterns 235 and doped polysilicon film patterns 236. Here, a gap between the gate electrodes 238 was about 20 nm.

Source/drain regions 240 were formed at portions of the substrate 200 by an ion implantation process using the gate electrodes 238 as masks. Thus, transistors including the gate electrodes 238 and the source/drain regions 240 were formed on the substrate 200.

After a silicon nitride film was formed on the gate electrodes 238 and on the substrate 200, the silicon nitride film was anisotropically etched to form gate spacers 250 on sidewalls of the gate electrodes 238.

FIG. 3A is a schematic cross sectional view illustrating a step of filling a gap between the transistors in accordance with embodiments of the present invention.

Referring to FIGS. 2C and 3A, a second film 260 was formed on the substrate 200 having the transistors formed thereon using the above-described solution. Here, perhydro-polysilazane 300 having low molecular weight had an average molecular size of below about 2 mm. Since the ratio between the gap between transistors and the average molecular size of perhydro-polysilazane 300 having low molecular weight was above about 10:1, perhydro-polysilazane 300 having low molecular weight was sufficiently inserted in the gap between the transistors, thereby completely filling the gap between the transistors. Particularly, because perhydro-polysilazane 300 having low molecular weight had a molecular weight distribution of about 2.2, the gap between the transistors was effectively filled without voids as perhydro-polysilazane molecules having relatively small sizes were sufficiently inserted between perhydro-polysilazane molecules having relatively large sizes.

Referring to FIG. 2D, the second film 260 was hardened using an oxidizing gas to form a second oxide film. Here, the second oxide film was dense, and had reduced height relative to the second film 260 because the second film 260 was diminished during hardening. Hence, the second oxide film was densely filled up the gap between the transistors.

The second oxide film was planarized using a chemical mechanical polishing (CMP) process, thereby forming a first interlayer insulation film 265 on the substrate 200 to cover the gate electrodes 238.

Referring to FIG. 2E, a photoresist film was coated on the first interlayer insulation film 265, and then a photoresist pattern (not shown) exposing portions of the first interlayer insulation film 265 was formed on the interlayer insulation film 265. The exposed portions of the first interlayer insulation film 265 were etched using the photoresist pattern as an etching mask to thereby form the first contact holes 270a and the second contact holes 270b. The substrate 200 including the first and second holes 270a and 270b was cleaned so as to remove impurities or particles existing in the first and second contact holes 270a and 270b. Here, the first interlayer insulation film 265 was not damaged during the cleaning process because the first interlayer insulation film 265 had a dense construction.

Referring to FIG. 2F, a conductive film was formed on the first interlayer insulation film 265 to fill up the first and second contact holes 270a and 270b. The conductive film was removed using a CMP process until the upper face of the first interlayer insulation film 265 was exposed. Thus, first and second contact plugs 275a and 275b were formed in the first and second contact holes 270a and 270b, respectively.

Referring to FIG. 2G, after a metal film was formed on the first interlayer insulation film 265 including the first and second contact plugs 275a and 275b, bit lines 280 were formed on the first contact plugs 275a and on the first interlayer insulation film 265 by patterning the metal film.

Referring to FIG. 2H, a third film was formed on the bit lines 280, on the second contact plugs 275b and on the first interlayer insulation film 265 using the above-described composition that includes perhydro-polysilazane having low molecular weight. The bit lines 280 were completely covered with the third film. The third film was hardened using an oxidizing gas to thereby form a second interlayer insulation film 285 on the bit lines 280, on the second contact plugs 275b and on the first interlayer insulation film 265. Alternatively, the second interlayer insulation film 285 might be formed using insulation material such as oxides or nitrides.

Referring to FIG. 2I, portions of the second interlayer insulation film 285 were etched to form third contact holes 290 exposing the second contact plugs 275b. To remove impurities or particles generated during etching the second interlayer insulation film 285, a cleaning process was carried out on the substrate 200 including the third contact holes 290.

Referring to FIG. 2J, after a conductive film was formed on the second interlayer insulation film 290 to fill up the third contact holes 290, the conductive film was removed until the second interlayer insulation film 290 was exposed to thereby form third contact plugs 295 in the third contact holes 290. The third contact plugs 295 were contacted to the second contact plugs 275b, respectively.

COMPARATIVE EXAMPLE 2

FIG. 4A is a schematic plan view illustrating a semiconductor device according to one comparative example of the present invention.

Referring to FIG. 4A, a gate line (gate electrodes) 438 was formed on a semiconductor substrate in a first direction, and a bit line 480 was formed on the substrate in a second direction perpendicular to the first direction.

The bit line 480 included bit line contact plugs (first contact plugs) 475a making contact with underlying first contact regions of the substrate. In addition, second contact plugs 475b making contact with second contact regions of the substrate were formed for capacitors successively formed.

FIGS. 4B to 4J are cross sectional views illustrating a method of forming the semiconductor device taken along line of B-B′ in FIG. 4A.

Referring to FIG. 4B, after a trench was formed on a semiconductor substrate 400 by a shallow trench isolation (STI) process, a field region 430 was defined on the semiconductor substrate 400 by filling an oxide film in the trench. The field region 430 is formed using the above-described composition and method. Also, active regions were formed on the substrate 400 in accordance with the formation of the field region 430.

An oxide film was formed on the substrate 400 where the field region 430 and the active regions were defined, and then a polysilicon film was formed on the oxide film. The polysilicon film was doped with impurities to have a high impurity concentration. The doped polysilicon film and the oxide film were patterned by a photolithography process to thereby form gate electrodes 438 including doped polysilicon patterns 436 and gate oxide film patterns 435. A gap between the gate electrodes 438 was about 20 nm.

Source/drain regions 440 were formed at portions of the substrate 400 by an ion implantation process using the gate electrodes 438 as masks. Hence, transistors including the gate electrodes 438 and the source/drain regions 440 were formed on the substrate 400.

After an insulation film such as a silicon nitride film or a silicon oxide film was formed on the gate electrodes 438 and on the substrate 400, the insulation film was anisotropically etched to form gate spacers 450 on sidewalls of the gate electrodes 438.

FIG. 3B is a schematic cross sectional view illustrating a step of filling a gap between the transistors in accordance with the comparative example of the present invention.

Referring to FIGS. 3B and 4C, a spin on glass (SOG) film 460 was formed on the substrate 400 having the transistors formed thereon using a solution comprising a perhydro-polysilazane of high molecular weight and a solvent. Here, perhydro-polysilazane 320 having high molecular weight had an average molecular size of above about 4 nm. The ratio between the gap between transistors and the average molecular size of perhydro-polysilazane 320 of high molecular weight was below about 5:1. When perhydro-polysilazane 320 having high molecular weight was provided on the substrate 400, perhydro-polysilazane 320 might not effectively occupy the gap between the transistors because perhydro-polysilazane 320 of high molecular weight had a relative large size. Thus, perhydro-polysilazane 320 of high molecular weight results in the formation of pores in the gap between the transistors. Furthermore, the SOG film 460 was not dense between the transistors because various sized particles of perhydro-polysilazane 320 having high molecular weight were not evenly distributed in the gap between the transistors although perhydro-polysilazane 320 of high molecular weight had the polydispersity index of about 3.1. Portions of the SOG film 460 did not have high or uniform density due to the size of perhydro-polysilazane 320 of high molecular weight. As a result, pores 330 were formed in the gap between the transistors.

Referring to FIG. 4D, the SOG film 460 was changed into an oxide film by hardening the SOG film 460 and providing an oxidizing gas such as an oxygen gas and a water vapor. Here, the second oxide film had reduced height relative to the SOG film 460 because the SOG film 460 was diminished during hardening.

The oxide film was planarized using a CMP process to thereby form a first interlayer insulation film 465 on the substrate 400.

Referring to FIG. 4E, a photoresist film was coated on the first interlayer insulation film 465, and then a photoresist pattern (not shown) exposing portions of the first interlayer insulation film 465 was formed on the interlayer insulation film 465. The exposed portions of the first interlayer insulation film 465 were etched using the photoresist pattern as an etching mask to thereby form the first contact holes 470a and the second contact holes 470b. The substrate 400 including the first and second holes 470a and 470b was cleaned so as to remove impurities or particles existing in the first and second contact holes 470a and 470b. Here, the first interlayer insulation film 465 was not dense except porous film since the first interlayer insulation film 465 was formed using perhydro-polysilazane of high molecular weight. Therefore, the first interlayer insulation film 465 was damaged during the cleaning process so that an etched portion 465b exposing conductive patterns such as the gate electrodes 438 was formed. Further, the first interlayer insulation film 465 was damaged to generate a passage 465a that connects adjacent contact holes 470b.

Referring to FIG. 4F, a conductive film was formed on the first interlayer insulation film 465 to fill the first and second contact holes 470a and 470b. The conductive film was removed using a CMP process until the upper face of the first interlayer insulation film 265 was exposed. Thus, first and second contact plugs 475a and 475b were formed in the first and second contact holes 470a and 470b, respectively. Here, adjacent first contact plugs 475a or second contact plugs 475b were connected each other through a bridge 475 formed in the passage 465a formed due to the damage of the first interlayer insulation film 465. This bridge 475 might cause an electrical short between adjacent contact plugs 475a or 475b. Hence, the failure of the semiconductor device might be caused due to the bridge 475.

Referring to FIG. 4G, after a metal film was formed on the first interlayer insulation film 465 including the first and second contact plugs 475a and 475b, bit lines 480 were formed on the first contact plugs 475a and on the first interlayer insulation film 465 by patterning the metal film.

Referring to FIG. 4H, a film was formed on the bit lines 480, on the second contact plugs 475b and on the first interlayer insulation film 465 using the above-described composition that includes perhydro-polysilazane having high molecular weight. The film was hardened using an oxidizing gas to thereby form a second interlayer insulation film 485 on the bit lines 480, on the second contact plugs 475b and on the first interlayer insulation film 465.

Referring to FIG. 4I, portions of the second interlayer insulation film 485 were etched to form third contact holes 490 exposing the second contact plugs 475b. To remove impurities or particles generated during etching the second interlayer insulation film 485, a cleaning process was carried out on the substrate 400 including the third contact holes 490.

Referring to FIG. 4J, after a conductive film was formed on the second interlayer insulation film 490 to fill the third contact holes 490, the conductive film was removed until the second interlayer insulation film 490 was exposed to thereby form third contact plugs 495 in the third contact holes 490. The third contact plugs 495 were contacted to the second contact plugs 475b, respectively.

FIG. 5A is a cross sectional photograph illustrating the first interlayer insulation film obtained using a transmission electron microscope (TEM) according to example 2 of the present invention, and FIG. 5B is a cross sectional photo illustrating the first interlayer insulation film obtained using a TEM according to comparative example 2 of the present invention.

Referring to FIG. 5A, because the first interlayer insulation film 265 was formed using perhydro-polysilazane 300 having low molecular weight and the average molecular size of about 2 nm that completely filled in the gap between the transistors, the first interlayer insulation film 265 was dense and uniform. Further, perhydro-polysilazane 300 of low molecular weight had the polydispersity index of about 2.2 so that relatively small particles of perhydro-polysilazane 300 of low molecular weight were effectively inserted between relatively large particles of perhydro-polysilazane 300 of low molecular weight. Thus, the first interlayer insulation film 265 was dense and durable for the cleaning process.

Referring to FIG. 5B, the first interlayer insulation film 465 was not dense as well as not uniform because the first interlayer insulation film 465 was formed using perhydro-polysilazane 320 having high molecular weight and an average molecular size of about 4 nm, which does not sufficiently fill the gap between the transistors. In addition, perhydro-polysilazane 320 of high molecular weight had a polydispersity index of about 3.1 so that the first interlayer insulation film 465 was porous and weak for the cleaning process.

FIG. 6 is a graph illustrating the number of bit-fails generated in semiconductor devices of 256M in accordance with Example 2 and comparative Example 2 of the present invention.

As shown in FIG. 6, the number of failed contact plugs in the semiconductors of 256M was measured. Here, the semiconductors were formed on one wafer. In semiconductor devices manufactured according to Example 2 of the present invention, the number of the failed contact plugs was about 5. However, in the semiconductor devices manufactured according to comparative Example 2, the maximum number of the failed contact plugs was about 50 while the minimum number of the failure of the contact plugs was about 5. Thus, the reliability of the semiconductor manufacturing process was deteriorated when the semiconductor devices were manufactured in accordance with the Comparative Examples.

EXAMPLE 3

Perhydro-polysilazane having a weight average molecular weight (Mw) of about 2,300 and a polydispersity index (Mw/Mn, or molecular weight distribution) of about 2.4 was prepared. The molecules of perhydro-polysilazane had an average molecular size of about 2 nm and a size range of about 0.5 to about 4 nm. A solution was prepared by mixing perhydro-polysilazane with a solvent of dibutyl ether. The solution included about 14 percent by weight of perhydro-polysilazane.

COMPARATIVE EXAMPLE 3

Perhydro-polysilazane having a weight average molecular weight of about 3,040 and a polydispersity index of about 2.4 was prepared. The molecules of perhydro-polysilazane had an average molecular size of about 4 nm and a size range of about 0.7 to about 7 nm. A solution was prepared by mixing perhydro-polysilazane with a solvent of dibutyl ether. The solution included about 12 percent by weight of perhydro-polysilazane.

EXAMPLE 4

A silicon substrate was provided. After a pad oxide film was formed on a silicon substrate, a first nitride film was sequentially formed on the pad oxide film. After a photoresist pattern was formed on the first nitride film, trenches were formed by successively etching the first nitride film, the pad oxide film and the silicon substrate. Thus, an etched portion of the silicon substrate was exposed through the trenches. In addition, there were also exposed sidewalls of the pad oxide film and the first nitride film. An inner oxide film was formed in the trenches by thermally treating the exposed portion of the silicon substrate under an oxygen atmosphere. That is, the inner oxide film was formed on a bottom face and on an inner sidewall of the trenches by reacting an oxygen gas with silicon contained in the substrate. A second nitride film was formed on the inner oxide film and the first nitride film. The second nitride film was also formed the exposed sidewalls of the pad oxide film and the first nitride film.

A preliminary film was formed using the solution according to Example 3 by a spin coating process on the second nitride film to fill up the trenches. The preliminary film was changed into a silicon oxide film by hardening the preliminary film while an oxygen (O₂) gas and a water vapor (H₂O) were provided to the preliminary film. The silicon oxide film was etched using a low ammonium fluoride liquid (LAL) solution as an etching solution employing a wet etching process. FIG. 7A is illustrating a scanning electron microscope (SEM) picture of the silicon oxide film formed using Example 3 in the trenches after performing the etching process

Referring FIG. 7A, the silicon oxide film formed using perhydro-polysilazane having a weight average molecular weight of about 2,300 and a polydispersity index of about 2.4 was not damaged during performing the etching process. Thus, perhydro-polysilazane having a weight average molecular weight of about 2,300 and a polydispersity index of about 2.4 may form the highly dense and uniform silicon oxide film.

COMPARATIVE EXAMPLE 4

A silicon oxide film was formed by performing substantially the same process as that of Example 4 except for using the solution according to Comparative Example 3. FIG. 7B is illustrating a scanning electron microscope (SEM) picture of the silicon oxide film formed using Comparative Example 3 in the trench after performing an etching process.

Referring to FIG. 7B, the silicon oxide film formed using perhydro-polysilazane having a weight average molecular weight of about 3,040 and a polydispersity index of about 2.4 was damaged during performing the etching process. Thus, perhydro-polysilazane having a weight average molecular weight of about 3,040 and a polydispersity index of about 2.4 may not form the dense and uniform silicon oxide film and may not be suitable as a silicon oxide film precursor.

Perhydro-polysilazane having a weight average molecular weight of 3,000 or less may form a denser and more uniform silicon oxide film than perhydropolysilazane having a weight average molecular weight of more than 3,000.

As described above, a highly dense film is obtained using perhydro-polysilazane having low molecular weight because perhydro-polysilazane of low molecular weight is completely filled into a narrow gap between conductive patterns formed on a substrate. Since perhydro-polysilazane of low molecular weight has good solubility relative to a solvent such as xylene or dibutyl ether, the gellation of perhydro-polysilazane of low molecular weight is not generated in a solution, and particles or impurities in the solution are reduced. When perhydro-polysilazane has low molecular weight of about 1,800, perhydro-polysilazane of low molecular weight has an average molecular size of about 2 nm. Therefore, a dense and uniform film is formed using perhydro-polysilazane of low molecular weight without the generation of pores or voids. However, when a film is obtained using perhydro-polysilazane of high molecular weight, the film is porous, but it is not uniform.

When the film formed using perhydro-polysilazane of low molecular weight is employed as an interlayer insulation film of a semiconductor device, a failure such as an electrical short between adjacent contact plugs is greatly reduced to improve a reliability of a semiconductor manufacturing process.

According to the embodiments of present invention, a semiconductor device is manufactured using a composition including perhydro-polysilazane of low molecular weight having weight average molecular weight of about 300 to about 3,000 and polydispersity index of about 1.8 to about 3.0. Thus, a dense and uniform film of the semiconductor device is formed using the composition including perhydro-polysilazane having low molecular weight and small molecular weight distribution. When this film is employed for an interlayer insulation film of the semiconductor device, the interlayer insulation film is not etched during a cleaning process so that contact holes formed through the interlayer insulation film are completely separated from each other. As a result, contact plugs formed in the contact holes are completely insulated from each other, thereby improving the reliability of the semiconductor device.

The foregoing is illustrative of example embodiments and is not to be construed as limiting thereof. Although a few example embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in the example embodiments without materially departing from the novel teachings and advantages of the present invention. Accordingly, all such modifications are intended to be included within the scope of the present invention as defined in the claims. In the claims, means-plus-function clauses are intended to cover the structures described herein as performing the recited function and not only structural equivalents but also equivalent structures. Therefore, it is to be understood that the foregoing is illustrative of various example embodiments and is not to be construed as limited to the specific example embodiments disclosed, and that modifications to the disclosed example embodiments, as well as other example embodiments, are intended to be included within the scope of the appended claims.

Claims

1. An oxide film precursor for forming a silicon oxide film comprising: a perhydro-polysilazane having a weight average molecular weight of about 1,800 to 3,000, an average molecular size less than about 4 nm and a polydispersity index of more than about 2.2 to about 3.0 according to the formula: —(SiH2NH)n—wherein n is a positive integer.

2. The oxide film precursor of claim 1, further comprising a solvent, wherein the oxide film precursor comprises about 5 to about 30 percent by weight of perhydro-polysilazane, and about 70 to about 95 percent by weight of the solvent.

3. The oxide film precursor of claim 2, wherein the solvent comprises xylene or dibutyl ether.