Patent Application
20230369435
The present invention relates to the field of semiconductor technology, in particular to a method for forming a contact on a compound semiconductor device.
High electron mobility transistors (HEMTs) are known in the art. GaN HEMTs are widely used in high-frequency, high-power amplifier components due to high breakdown voltage, high saturation electron moving speed and high operation temperature.
In a typical HEMT, for example, a two-dimensional electron gas (2DEG) is generated at a semiconductor heterojunction. The 2DEG represents a very thin conduction layer of highly mobile and highly concentrated charge carriers free to move readily in the two dimensions of that conduction layer, but constrained from movement in a third dimension perpendicular to the conduction layer.
Low-resistance, stable contacts are critical for the performance and reliability of integrated circuits, and their preparation and characterization are major efforts in circuit fabrication.
It is one object of the present invention to provide a method for fabricating a compound semiconductor device having low-resistance and stable contact structure.
One aspect of the invention provides a compound semiconductor device including a substrate, a channel layer on the substrate, a barrier layer on the channel layer, a passivation layer on the barrier layer, and a contact area recessed into the passivation layer and the barrier layer. The channel layer is partially exposed at a bottom of the contact area. A bi-layer silicide film is disposed on the contact area. A copper contact is disposed on the bi-layer silicide film.
According to some embodiments, the bi-layer silicide film comprises a first silicide layer in direct contact with the channel layer and a second silicide layer in direct contact with the first silicide layer.
According to some embodiments, the first silicide layer has a work function smaller than that of the second silicide layer, and the second silicide layer has a work function smaller than that of a diffusion barrier layer of the copper contact.
According to some embodiments, the first silicide layer has a thickness smaller than that of the second silicide layer.
According to some embodiments, the first silicide layer has a thickness smaller than or equal to 200 angstroms.
According to some embodiments, the second silicide layer has a thickness ranging between 200 angstroms and 500 angstroms.
According to some embodiments, the first silicide layer comprises TiSi, the second silicide layer comprises TaSi, and the diffusion barrier comprises TaN.
According to some embodiments, the channel layer comprises GaN.
According to some embodiments, the barrier layer comprises AlGaN.
According to some embodiments, the passivation layer comprises silicon nitride, silicon oxide, aluminum oxide, hafnium oxide, or aluminum nitride.
Another aspect of the invention provides a method for forming a compound semiconductor device. A substrate is provided. A channel layer is formed on the substrate. A barrier layer is formed on the channel layer. A passivation layer is formed on the barrier layer. A contact area is formed by etching through the passivation layer and the barrier layer. The channel layer is partially exposed at a bottom of the contact area. A bi-layer silicide film is formed on the contact area. A copper contact is formed on the bi-layer silicide film.
According to some embodiments, the bi-layer silicide film comprises a first silicide layer in direct contact with the channel layer and a second silicide layer in direct contact with the first silicide layer.
According to some embodiments, the first silicide layer has a work function smaller than that of the second silicide layer, and the second silicide layer has a work function smaller than that of a diffusion barrier layer of the copper contact.
According to some embodiments, the first silicide layer has a thickness smaller than that of the second silicide layer.
According to some embodiments, the first silicide layer has a thickness smaller than or equal to 200 angstroms.
According to some embodiments, the second silicide layer has a thickness ranging between 200 angstroms and 500 angstroms.
According to some embodiments, the first silicide layer comprises TiSi, the second silicide layer comprises TaSi, and the diffusion barrier comprises TaN.
According to some embodiments, the channel layer comprises GaN.
According to some embodiments, the barrier layer comprises AlGaN.
According to some embodiments, the passivation layer comprises silicon nitride, silicon oxide, aluminum oxide, hafnium oxide, or aluminum nitride.
According to some embodiments, the method further comprises the steps of forming a buffer layer on the substrate; and forming the channel layer on the buffer layer, wherein the buffer layer has a band gap larger than that of the channel layer.
According to some embodiments, the buffer layer comprises AlN, AlGaN, or GaN.
According to some embodiments, the substrate comprises SiC, Sapphire, Si, Al2O3, AlN, or GaN.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
In the following detailed description of the disclosure, reference is made to the accompanying drawings, which form a part hereof, and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention.
Other embodiments may be utilized, and structural, logical, and electrical changes may be made without departing from the scope of the present invention. Therefore, the following detailed description is not to be considered as limiting, but the embodiments included herein are defined by the scope of the accompanying claims.
Please refer to
Next, a channel layer 110 is formed on the buffer layer 106. According to an embodiment of the present invention, for example, the channel layer 110 may include GaN. According to an embodiment of the present invention, the band gap of the buffer layer 106 is larger than the band gap of the channel layer 110.
Next, a barrier layer 120 is formed on the channel layer 110. According to an embodiment of the present invention, for example, the barrier layer 120 may include AlGaN. A passivation layer 130 is then formed on the barrier layer 120. According to an embodiment of the present invention, for example, the passivation layer 130 may include silicon nitride, silicon oxide, aluminum oxide, hafnium oxide, or aluminum nitride.
Next, photolithography and etching processes are performed to etch through the passivation layer 130 and the barrier layer 120, thereby forming a contact area CA. The channel layer 110 is partially exposed at the bottom of the contact area CA.
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According to an embodiment of the present invention, for example, the bi-layer silicide film 300 includes a first silicide layer 310 in direct contact with the channel layer 110 and a second silicide layer 320 in direct contact with the first silicide layer 310.
According to an embodiment of the present invention, for example, the first silicide layer 310 includes TiSi, and the second silicide layer 320 includes TaSi.
According to an embodiment of the present invention, for example, the thickness of the first silicide layer 310 is smaller than the thickness of the second silicide layer 320. According to an embodiment of the present invention, for example, the thickness of the first silicide layer 310 is less than or equal to 200 angstroms. According to an embodiment of the present invention, the thickness of the second silicide layer 320 is 200-500 angstroms.
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TaN. Subsequently, an etch stop layer 600, for example, a silicon nitride layer, may be deposited on the copper contact 500 and on the dielectric layer 400.
According to an embodiment of the present invention, the work function of the first silicide layer 310 is smaller than that of the second silicide layer 320, and the work function of the second silicide layer 320 is smaller than that of the diffusion barrier layer 520 of the copper contact 500. Therefore, a contact interface with a work function gradient is formed between the copper metal layer 510 and the channel layer 110.
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According to an embodiment of the present invention, the compound semiconductor device 10 further includes a contact area CA recessed into the passivation layer 130 and the barrier layer 120. Part of the channel layer 110 constitutes the bottom of the contact area CA.
According to an embodiment of the present invention, the compound semiconductor device 10 further includes a bi-layer silicide film 300 on the contact area CA, and a copper contact 500 on the bi-layer silicide film 300.
According to an embodiment of the present invention, the bi-layer silicide film 500 includes a first silicide layer 310 in direct contact with the channel layer 110 and a second silicide layer 320 in direct contact with the first silicide layer 310.
According to the embodiment of the present invention, the work function of the first silicide layer 310 is smaller than that of the second silicide layer 320, and the work function of the second silicide layer 320 is smaller than that of the diffusion barrier layer 520 of the copper contact 500. A contact interface with work function gradient is formed between the copper metal layer 510 and the channel layer 110.
According to the embodiment of the present invention, the thickness of the first silicide layer 310 is smaller than the thickness of the second silicide layer 320. According to an embodiment of the present invention, the thickness of the first silicide layer 310 is less than or equal to 200 angstroms. According to an embodiment of the present invention, the thickness of the second silicide layer 320 is 200-500 angstroms.
According to an embodiment of the present invention, the first silicide layer 310 includes TiSi, the second silicide layer 320 includes TaSi, and the diffusion barrier layer 520 includes TaN.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202210527178.6 | May 2022 | CN | national |
