Claims
- 1. A method of manufacturing an integrated circuit comprising;providing a substrate having a semiconductor device thereon; forming a first stop layer over the substrate; forming a first dielectric layer over the first stop layer; forming an opening having sidewalls in the first dielectric layer; forming a first conformal barrier liner in the opening, forming the first conformal barrier liner to a constant thickness; processing the first conformal barrier liner to remove horizontal portions and leave vertical portions of the constant thickness of the first conformal barrier liner on the sidewalls of the opening in the first dielectric layer, the processing the first conformal barrier liner including removing a portion of the first stop layer to the semiconductor device; treating the first conformal barrier liner and the first stop layer to increase adhesion properties thereof; and forming a first conductor core in the opening over the vertical portions of the first conformal barrier liner and the first stop layer, forming the first conductor core includes connecting the first conductor core to the semiconductor device.
- 2. The method of manufacturing an integrated circuit as claimed in claim 1 including:forming a via stop layer over the first dielectric layer; forming a via dielectric layer over the via stop layer; forming a second stop layer over the via dielectric layer; forming a second dielectric layer over the via dielectric layer; forming an opening having sidewalls in the second dielectric layer, through the second stop layer, and in the via dielectric layer; forming a second conformal barrier liner in the opening, forming the second conformal barrier liner to a second constant thickness; processing the second conformal barrier liner to remove horizontal portions and leave vertical portions of the second constant thickness of the second conformal barrier liner on the sidewalls of the opening in the second dielectric layer and the via dielectric layer, the portions of the second conformal barrier liner on the sidewalls acting as a barrier to diffusion of conductor core material to the second dielectric layer and the via dielectric layer, processing the second conformal barrier liner including removing a portion of the via stop layer to the first conductor core; treating the second conformal barrier liner and the second stop layer to increase adhesion properties thereof; and forming a second conductor core in the opening over the vertical portions of the second conformal barrier liner, the first conductor core, and the second stop layer, forming the second conductor core includes connecting the second conductor core to the first conductor core.
- 3. The method of manufacturing as claimed in claim 2 wherein forming the second stop layer forms a second stop layer having at least about twice the thickness of the first stop layer.
- 4. The method of manufacturing as claimed in claim 1 wherein treating the first conformal barrier liner uses a treatment selected from a group consisting of pre-cleaning, silicon-enrichment, wetting layer deposition, and a combination thereof.
- 5. The method of manufacturing as claimed in claim 1 wherein the first conductor core is a material selected from a group consisting of copper, aluminum, gold, silver, compounds thereof, and combinations thereof.
- 6. The method of manufacturing as claimed in claim 1 wherein forming the first dielectric layer deposits a low dielectric constant material.
CROSS-REFERENCE TO RELATED APPLICATION
The present application contains subject matter related to a co-pending U.S. patent application Ser. No. 10/079,515 by Christy Mei-Chu Woo, John E. Sanchez, Darrell M. Erb, and Amit P. Marathe entitled “COPPER INTERCONNECT WITH IMPROVED BARRIER LAYER”. The related application is assigned to Advanced Micro Devices, Inc. and is identified by docket number 50432-321.
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