The present patent document claims priority to German Application Serial No. DE 10 2005 014 645.7, filed Mar. 31, 2005, the entirety of which is hereby incorporated by reference.
The present disclosure relates to a connection electrode for phase change materials, to an associated phase change memory element and to an associated production process, and in particular to connection electrodes which allow particularly high integration densities to be achieved with memory circuits of this type.
What are known as phase change memory elements use materials whose electrical properties can be reversibly switched from one phase to another. By way of example, materials of this type change between an amorphous phase and a crystalline or polycrystalline phase. In particular a resistance or conductance of a material of this type is very different in these two different phase states.
Therefore, phase change memory elements usually use phase change materials which, for example, represent alloys of elements from group VI of the periodic system and are known as chalcogenides or chalcogenide materials. Accordingly, in the text which follows, phase change materials of this type are to be understood as meaning materials which can be switched between two different phase states with different electrical properties (resistances).
Currently the most widespread chalcogenides or phase change materials consist of an alloy of Ge, Sb and Te (GexSbyTez). Ge2Sb2Te5 is already used in a large number of phase change memory elements and is also known as a material for rewritable optical storage media (e.g. CDs, DVDs etc.).
The changes in the resistance of phase change materials are utilized in order, for example, to create nonvolatile memory elements (NVM) and to store information. Accordingly, materials of this type have a higher resistance in the amorphous phase than in the crystalline or polycrystalline phase. Accordingly, a phase change material can be used as a programmable resistor, the resistance of which can be reversibly altered as a function of its phase state.
An overview of phase change materials of this type is known, for example, from literature reference S. Hatkins et al.: “Overview of phase-change chalcogenide nonvolatile memory technology”, MRS Bulletin/November 2004, pages 829 to 832.
A change in the phase of materials of this type can be caused by a local increase in a temperature. Both phase states are usually stable below 150 degrees Celsius. Above 300 degrees Celsius, rapid crystal nucleation takes place, resulting in a change in the phase state to a crystalline or polycrystalline state, provided that a temperature of this nature is present for a sufficient length of time. To return the phase state to the amorphous state, the temperature is increased to above the melting point of approx. 600 degrees Celsius, followed by very rapid cooling. Both critical temperatures, i.e. both for the crystallization and for the melting, can be generated using an electric current which flows through an electrically conductive connection electrode with a predetermined resistance and is in contact with or in the vicinity of the phase change material. The heating is in this case carried out by what is known as Joule heating.
Reference numeral 20 denotes an insulating interlayer dielectric. The section of the phase change material 50 which is in direct contact with the connection electrodes 40 and 60 defines the effective phase change region of the chalcogenide material.
If an electric current at a sufficiently high level is now passed through the connection electrode 40, this phase change section of the phase change material 50 can undergo a corresponding crystallization heating or melting heating, thereby causing a phase change. In this case, only a short time (short current pulse) but a high temperature (high current level) are required to render the phase change material amorphous, whereas a lower current has to be applied for a longer time to render it crystalline.
The phase state which has been set can be read by applying a sufficiently low read voltage which does not cause critical heating. Since the measured current is proportional to the conductivity or resistance of the phase change material, the phase states which have been set in this manner can be reliably recorded. Since, furthermore, the phase change material can be electrically switched almost any desired number of times, it is very easy to produce nonvolatile memory elements.
To avoid interference between adjacent memory elements, in accordance with
However, a drawback of memory elements of this type is formed by the very high programming currents which are required to change the phase state. In particular in semiconductor circuits with very high integration densities, however, currents of this level are subject to considerable restrictions; for example, in the case of gate lengths of approx. 100 nm and a gate dielectric which resists a voltage of 3 V, maximum currents of 100 to 200 μA are available. This results in contact surfaces with respect to the phase change material of at most 20 nm×20 nm, which are much smaller than structures which can be realized by lithographic means.
To achieve such high current densities or small contact surfaces, U.S. Pat. No. 6,746,892 B2 has disclosed, for example, the use of connection electrodes which have a tapered shape.
Furthermore, US 2003/0209746 A1 has disclosed a connection electrode in which a lithographically patterned connection surface for a phase change material is reduced in size by spacers, in such a manner that in turn a very small contact surface and in particular a sublithographic contact surface between the connection electrode and the phase change material can be realized.
However, this does not allow accurate setting of the contact surface which is actually active between the connection electrode and the phase change material.
Therefore, the disclosure is based on the object of providing a connection electrode for phase change materials, an associated phase change memory element and an associated production process with which an effective contact surface and therefore a spatial delimitation of the current path can be set with a high level of accuracy.
Accordingly, in accordance with the disclosure an electrode material of the connection electrode has a multiplicity of insulation regions which are formed at least at the connection surface to the phase change material.
In this case, the electrode material is preferably lithographically patterned, whereas the insulation regions are formed at a sublithographic level.
The insulation regions in this case preferably have a grain-like surface cross section and consist of SiO2, while the electrode material includes TiN.
With regard to the phase change memory element, the connection electrode is preferably formed in a contact hole of a dielectric, with the phase change material being formed either at the surface of the dielectric outside the contact hole or only at the surface of the connection electrode within the contact hole.
With regard to the process for producing a phase change memory element, it is preferable for a multiplicity of masking elements to be formed at the surface of an auxiliary dielectric, then in a subsequent step, regions of the auxiliary dielectric which are not covered by the masking elements are etched back anisotropically to form a multiplicity of insulation regions, and the resulting uncovered regions are filled with an electrode material to form a connection electrode.
It is preferable for the masking elements to be formed at a sublithographic level, in which case in particular what are known as LPCVD processes are used to produce semiconductor nanocrystals or HSG processes are used to produce HSG grains (hemispherical silicon grains).
In particular TiN is deposited conformally over the entire surface by means of an ALD process as the electrode material and is removed from a common surface of the dielectric and the insulation regions.
Alternatively, it is also possible for the connection electrode to be etched back to a predetermined depth in the contact hole and for the phase change material to be formed only in this recess, resulting in a self-aligning process with a maximum integration density.
The disclosure is described in more detail below on the basis of exemplary embodiments and with reference to the drawing, in which:
In accordance with
In principle, it is also possible to use other insulation layers and in particular alternative interlayer dielectrics as dielectric 2. In the same way, the carrier layer 1 may also form a metallization level or another, preferably electrically conductive layer.
To realize an electrical connection to a selection element formed in the semiconductor material, such as for example the source region S as shown in
In accordance with
This liner deposition is followed by filling of the opening or contact hole with an electrically conductive filling layer 3B, which preferably involves tungsten being deposited over the entire surface and then etched back to a predetermined depth (e.g. 10 nm) into the opening or contact hole. An etchback of this type can be carried out, for example, by means of a dry etching process, and in particular by means of reactive ion etching (RIE). Furthermore, it is also possible for the liner layer 3A at the side walls of the contact hole to be removed in this upper section, resulting in the recess R in the contact hole or opening as illustrated in
Then, as shown in
Then, as shown in
This process can be used to produce nanocrystals or what are known as nanodots as masking elements K with a feature size of from 1 nm to 10 nm. In this case, in addition to the size of these nanodots or masking elements K, it is also possible for a surface density to be very accurately set or varied, which is important for the precise setting of a connection electrode surface area that is ultimately effective. It is preferable for the size of the nanodots or masking elements K to be at least one order of magnitude smaller than a feature size of the opening or contact hole, i.e. the masking elements K in grain form have a feature size of less than 1/10 F.
Then, in accordance with
In accordance with
Furthermore, in accordance with
Although, in accordance with
In accordance with
A nonvolatile memory cell of this type is then completed in the same way as in the prior art, for example as illustrated in
The result is a connection electrode 4 and an associated phase change memory element and an associated production process, in which the switching current required can be very accurately reduced and set by the spatial delimiting of the current path, with the result that even with high integration densities the required Joul heating can be realized using very low current intensities.
The variation in the connection electrode cross-sectional area can be set very accurately, in particular when using LPCVD Si nanocrystal processes, by varying the size and density of the nanodots. On account of the random distribution of the nanodots, the result is a very uniform distribution of the flow of current over the contact surface of the connection electrode, resulting in a very high scalability of the process irrespective of the lithography and the nanodot sizes used.
In accordance with this second exemplary embodiment, following a step as shown in
Finally, as in the first exemplary embodiment shown in
The disclosure has been described above on the basis of GexSbyTez as phase change material. However, it is not restricted to this particular compound, and equally also encompasses alternative phase change materials.
In the same way, the further materials are not restricted to the materials described above, but rather may also encompass alternative materials. In particular, the dielectric 2 does not have to have a multilayer structure.
Furthermore, the disclosure is not restricted to an Si semiconductor substrate as carrier layer 1, but rather in the same way may also be formed on other carrier layers and in particular in wiring layers located above.
It is therefore intended that the foregoing detailed description be regarded as illustrative rather than limiting, and that it be understood that it is the following claims, including all equivalents, that are intended to define the spirit and scope of this disclosure.
Number | Date | Country | Kind |
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10 2005 014 645.7 | Mar 2005 | DE | national |