Patent Grant
8575023
This is a U.S. National Phase Entry of PCT Application No. PCT/JP2009/068233, filed Oct. 23, 2009, with a priority date of Oct. 30, 2008, based upon Japanese Patent Application No. 2008-279536.
This invention relates to an MIS semiconductor device widely used in an IC, an LSI, and the like and, in particular, to a structure of a source/drain electrode and/or a structure of a gate electrode.
In a semiconductor device, performance improvement, such as improvement in operating frequency, has been strongly desired. However, in the semiconductor device, a series resistance between two main electrodes, through which an electric current mainly flows, impedes the performance improvement. Patent Document 1 describes the necessity of reducing the series resistance and, specifically, the necessity of substantially reducing a contact resistance between a semiconductor region and an electrode.
Patent Document 1 proposes to use, as a material of an electrode contacting an n+ silicon region, Er, Mg, Mn, Cd, Hf, Y, or Zr each having a work function close to −4.05 eV which is a work function of the n+ silicon region, and to use, as a material of an electrode contacting a p+ silicon region, Pd, Pt, Co, Ni, or Ir each having a work function close to −5.15 eV which is a work function of the p+ silicon region.
However, Patent Document 1 does not sufficiently clarify which of the above-mentioned materials is practically preferable. Further, according to the knowledge of the present inventors, oxygen is inevitably mixed into a silicide and a gate metal during heat treatment for silicide formation or the like at a contact portion. This results in a problem that an increase of a resistance of the contact silicide or the gate metal is inevitable.
Patent Document 1: International Publication No. WO2008/007748
Therefore, an object of the present invention is to provide a contact formation method suitable for practical use.
Another object of the present invention is to provide a semiconductor device in which oxygen is prevented from being mixed into a contact silicide and a gate electrode metal.
According to a first aspect of the present invention, there is provided a method of forming a contact of a metal semiconductor compound on a predetermined region of a semiconductor device, characterized by comprising the steps of forming a layer of a first metal on the predetermined region, forming, on the layer of the first metal, a layer of a second metal for preventing oxidation of the first metal, and compounding only the first metal with a semiconductor by heat treatment, wherein, when the predetermined region is an n-type semiconductor region, the first metal is formed by a metal which has a work function whose absolute value is smaller than a value obtained by adding 0.3 eV to an absolute value of an energy level at the bottom of a conduction band of the semiconductor and wherein, when the predetermined region is a p-type semiconductor region, the first metal is formed by a metal which has a work function whose absolute value is greater than a value obtained by subtracting 0.3 eV from an absolute value of an energy level at the top of a valence band of the semiconductor. Herein, the semiconductor may include Si, Ge, SiGe, SiC, and the like.
According to a second aspect of the present invention, there is provided a semiconductor device manufacturing method characterized by comprising he steps of forming a layer of a first metal at a silicon portion to be a p-type or an n-type contact region of a semiconductor device, forming, on the layer of the first metal, a layer of a second metal for preventing oxidation of the first metal, and forming a silicide of the first metal by reacting only the first metal with the silicon portion, wherein, when the contact region is of an n-type, a metal which is selected and used as the first metal has a work function whose absolute value is smaller than a value obtained by adding 0.3 eV to an absolute value of an energy level at the bottom of a conduction band of silicon and wherein, when the contact region is of a p-type, the metal which is selected and used as the first metal has a work function whose absolute value is greater than a value obtained by subtracting 0.3 eV from an absolute value of an energy level at the top of a valence band of silicon.
According to a third aspect of the present invention, there is provided a semiconductor device characterized by comprising a silicide layer of a silicide of a first metal formed on a surface of a silicon portion as a p-type or an n-type contact region of the semiconductor device, wherein, when the contact region is of the n-type, the silicide layer is formed by the first metal which has a work function whose absolute value is smaller than a value obtained by adding 0.3 eV to an absolute value of an energy level at the bottom of a conduction band of silicon, wherein, when the contact region is of the p-type, the silicide layer is formed by the first metal which has a work function whose absolute value is greater than a value obtained by subtracting 0.3 eV from an absolute value of an energy level at the top of a valence band of silicon; and wherein the amount of mixed oxygen in the silicide layer is 1 mass % or less.
According to the present invention, it is possible to form a practical contact having a low contact resistivity. Further, according to the present invention, it is possible to prevent oxygen from being mixed during silicidation.
Before describing embodiments of the present invention, at first referring to
First, as shown in
Next, in the insulating film 101 formed on the surface of the silicon substrate 100, an opening portion 102 is formed. As a consequence, the silicon substrate 100 is selectively exposed at the opening portion 102. The exposed portion (contact region) has an area of 1×10−3 cm2. Processes of exposing and cleaning the silicon substrate 100 are performed in a high-purity nitrogen atmosphere and the silicon substrate is delivered to a metal forming device (not shown in the figure) without being exposed to air. As described above, the substrate is delivered in the high-purity nitrogen atmosphere without being exposed to air. Therefore, it is possible to suppress growth of a natural oxide film on the surface of the silicon substrate 100 before a low-work-function metal film is formed.
Subsequently, on the silicon substrate 100, a low-work-function metal layer 10 is formed in the metal forming device. In order to minimize mixture of impurities, sputtering is desirably used as a metal forming method. A metal material for forming the low-work-function metal layer 10 is selected from metal materials each of which forms, with the silicon substrate 100, a metal silicide and has a specific work function with respect to the silicon substrate 100.
Herein, referring to
On the other hand,
For the purpose of reducing the amount of silicon consumption of the silicon substrate 100, use may be made of, as a sputtering target, a silicide of a rare-earth metal which has, when the silicon substrate 100 is of the n-type, a work function whose absolute value is smaller than a value obtained by adding 0.3 eV to an absolute value of the energy level at the bottom of the conduction band of silicon and which has, when the silicon substrate is of the p-type, a work function whose absolute value is greater than a value obtained by subtracting 0.3 eV from an absolute value of the energy level at the top of the valence band.
Referring back to
Subsequently, a heat treatment is performed at 600° C. to cause solid-phase reaction of the low-work-function metal layer 10 with the silicon substrate 100 so that a silicide layer 11 is formed as shown in
The heat treatment for forming the silicide layer 11 may be performed by a clustered heat treatment device including the film forming device for the low-work-function metal layer 10 and a film forming device for the oxidation-resistant metal layer 12. Actually, however, oxidation of the underlying low-work-function metal layer 10 can be prevented due to the effect of the oxidation-resistant metal layer 12, even if the substrate is delivered in air. Therefore, the substrate may be delivered out of the film forming device and treated by another heat treatment device. As an atmosphere during the heat treatment, an inactive gas atmosphere, such as high purity nitrogen or argon, is desirable.
After the silicide layer 11 is formed, the oxidation-resistant metal layer 12 except a predetermined pattern and the unreacted low-work-function metal layer on the insulating film 101 are removed. Thereafter, sintering may be performed in a dilute hydrogen atmosphere.
The structure shown in
Referring to
From inclinations of the characteristics with respect to the p-type and the n-type silicon substrates, which are shown in
As described above, the holmium (Ho) silicide and the erbium (Er) silicide have the low barrier height with respect to the n-type silicon. Therefore, a contact resistance with respect to the n-type high-concentration region can be reduced to a very small value of 1×10−9 Ωcm2 or less.
Herein, an effect of the tungsten (W) layer formed as the oxidation-resistant metal layer 12 will be described.
Referring to
As apparent from comparison between
Likewise, referring to
As apparent from comparison between
Thus, it is understood that the tungsten layer serves as an oxidation-resistant layer for preventing oxidation of the low-work-function metal layer formed of rare-earth metal.
Next, referring to
On the other hand, it is understood that, between the silicon substrate and the holmium layer, silicon is diffused into the holmium layer to form holmium silicide. Therefore, it is understood that silicidation of holmium is achieved in a state where the tungsten layer prevents oxidation of the holmium layer as an under layer. As a result of the analysis, the amount of oxygen mixed into the silicide layer formed of holmium silicide was 1 mass % or less.
Referring to
In
On the other hand, as shown in
Referring to
As shown in
Thereafter, in order to ensure insulation with respect to the gate electrode 28, a side wall 30 comprising a silicon oxide film or a silicon nitride film is formed on the gate insulating film 26 and the gate electrode 28. Subsequently, over the entire surface, an interlayer insulating film 31 of BPSG (Boro-Phospho Silicate Glass) is formed. Thereafter, selective etching is performed to open and expose source/drain regions 32.
Thereafter, ion-implantation of an n-type impurity (herein, arsenic (As)) is performed to form the source/drain regions 32. Subsequently, the implanted impurity is activated by heat treatment. This process may be performed after metal formation which will be described hereinunder. As a result of activation, an impurity concentration of each of the source/drain regions 32 becomes 2×1020 cm−3.
In the first embodiment according to the present invention, a silicon surface of each of the source/drain regions 32 after the ion implantation mentioned above is exposed in a high-purity nitrogen atmosphere in a manner similar to that described in connection with
On the exposed surface of each of the source/drain regions 32, a low-work-function metal layer 34 is formed in a metal forming device. In this case, for the purpose of minimizing mixture of impurities, sputtering is desirably used as a metal forming method. Herein, by sputtering in an Ar atmosphere, holmium (Ho) is deposited to a thickness of 10 nm. It is noted here that the sputtering atmosphere may be Xe and that Er may be used instead of Ho. As a material of the low-work-function metal layer 34, holmium (Ho) or erbium (Er) is desirable but other rare-earth metals, such as samarium (Sm) and ytterbium (Yb) are also usable, as described above.
For the purpose of reducing the amount of silicon consumption of the silicon substrate 20, a silicide of a rare-earth metal may also be used as a sputtering target.
Specifically, the low-work-function metal layer 34 must be formed of a metal material which forms a metal silicide with the source/drain region 32 and which has, when the source/drain region 32 is of an n-type, a work function whose absolute value is smaller than a value obtained by adding 0.3 eV to an absolute value of an energy level at the bottom of a conduction band of silicon.
After formation of the low-work-function metal layer 34, the silicon substrate 20 is delivered in an inactive gas atmosphere, such as reduced-pressure nitrogen or argon, so as not to be exposed to air, to a second metal film forming chamber where an oxidation-resistant metal layer 36 is formed over the entire exposed surface. Herein, the oxidation-resistant metal layer 36 is formed by using tungsten (W) and by depositing W to a thickness of 300 nm by sputtering in an Ar atmosphere in a sputtering chamber.
Thereafter, the low-work-function metal layer 34 and the oxidation-resistant metal layer 36 are subjected to heat treatment (annealing) at 600° C. in a manner similar to that described in connection with
At this time, by increasing the thickness of the oxidation-resistant metal layer 36 to be greater than that of the low-work-function metal layer 34 as described above, it is possible to reduce a surface roughness of the silicide layer 34a so that breaking of shallow pn junction is prevented. Specifically, it is understood that, if there is no W, Ho (or Er) moves during annealing and therefore defects are caused to occur at an interface with silicon (significant unevenness is generated on a surface of the silicide) while, if there is W, the movement is prevented and defects are not caused to occur. When the thickness of W is 100 nm or more, the above-mentioned effect is obtained. Although a necessary thickness of W depends on a thickness of Ho (or Er), the thickness of the oxidation-resistant metal layer 36 is basically selected so that the surface of the silicide layer 34a has a predetermined flatness.
In
Subsequently, a surface oxide film of the oxidation-resistant metal layer 36 is removed and an interlayer insulating film 40 is formed on the entire surface by CVD. The interlayer insulating film 40 in this case may be formed of various kinds of materials. Thereafter, opening of a contact hole and formation of a wiring using Cu, Al, or the like may be carried out by a method same as a manufacturing method usually performed. In this case, the oxidation-resistant metal layer 36 may be removed entirely, including a part on the silicide layer 34a, and a wiring may be formed on the silicide layer directly or via a barrier conductive layer. Obviously, a multilayer wiring layer may be formed further thereon.
In any case, it is possible to obtain a contact having a low resistance of 10−9 Ωcm2 or less with respect to the n-type silicon forming the source/drain regions 32.
In the first embodiment, the inversion mode n-channel field-effect transistor has been described. However, the present invention is applicable also to an inversion mode p-channel field-effect transistor.
As described in the foregoing, when the contact is formed in the high-concentration n-type silicon region, it is possible to form a low-resistance contact as compared to a case where the contact is formed in a p-type silicon region. Specifically, in the embodiment shown in
Referring to
In the bulk-current controlled type accumulation mode n-channel transistor illustrated in the figure, on a supporting substrate 50 formed of p-type silicon, an n-type semiconductor layer 54 is formed and isolated by a buried oxide film 52 having a thickness of about 100 nm. Herein, the semiconductor layer 54 forms a channel region. A surface of the channel region illustrated in the figure has a (100) orientation. The semiconductor layer 54 has a film thickness of 50 nm. On both sides of the channel region formed of the n-type semiconductor layer 54, source/drain regions 56 are formed each of which has a conductivity type identical with that of the channel region and each of which is formed of an n+ semiconductor having an impurity atomic concentration higher than that of the channel region.
On the channel region formed of the semiconductor layer 54, a gate insulating film 58 formed of an oxide film having an electrically equivalent film thickness (EOT: Equivalent Oxide Thickness) of 7.5 nm is formed. On the gate insulating film 58, a gate electrode 60 of p+ polysilicon is formed. The n-channel transistor illustrated in the figure has a gate length of 0.6 μm and a gate width of 20.0 μm.
Herein, the channel region has an average impurity atomic concentration of 2×1017 cm−3. Each of the source/drain regions 56 in contact with the channel region is formed of an n-type semiconductor having an impurity concentration of 2×1020 cm−3.
Like in the first embodiment shown in
Herein, as a material of the low-work-function metal layer 62, holmium or erbium is desirable. However, use may be made of a metal material having a work function whose absolute value is smaller than a value obtained by adding 0.3 eV to an absolute value of an energy level at the bottom of a conduction band of n+ silicon forming each of the source/drain regions 56, for example, other rare-earth metals, such as samarium and ytterbium.
According to the second embodiment of the present invention, a contact resistance with a semiconductor is suppressed to 1×10−9 Ωcm2 or less. Even in combination with a series resistance of semiconductor portions of the source/drain regions, a series resistance of the transistor can be reduced to 1.0Ωμm.
In the foregoing, only a case where the present invention is applied to the accumulation mode n-channel transistor has been described. However, the present invention is similarly applicable to an accumulation mode p-channel transistor also.
As described above, the second embodiment of the present invention is applicable to a case where a transistor formed on a SOI (Silicon-On-Insulator) substrate is operated in either an inversion mode or an accumulation mode. However, for the purpose of a high-speed operation, it is desirable to operate the transistor in the accumulation mode.
Referring to
A manufacturing process for obtaining the structure shown in
Next, for the purpose of forming p+ regions 76 and n+ regions 77 in the n-well 72 and the p-well 73, boron and phosphorus are ion-implanted into the n-well 72 and the p-well 73 by 6×1015 cm2, respectively. As a consequence, the high-concentration regions 76 (p+ regions) and 77 (n+ regions), each having a thickness of 20 nm, are formed.
In this state, for the purpose of activation of the high-concentration regions 76 and 77, heat treatment may be performed. However, in this example, without performing heat treatment in this state, an oxide film is deposited by CVD (Chemical Vapor Deposition) and etching is performed to form side walls 78 as shown in
In the third embodiment of the present invention, in a state where the low-work-function metal layer is formed, a tungsten layer is further formed as an oxidation-resistant metal layer. Next, in a state where the low-work-function metal layer and the oxidation-resistant metal layer are laminated, heat treatment is performed in a nitrogen atmosphere at 550° C. for 1 hour. Thus, not only silicidation (formation of a contact silicide layer 79) but also activation of the high-concentration layers 76 and 77, which has not previously been performed, is simultaneously achieved. Because of the heat treatment at a low temperature, diffusion of the high-concentration regions can be suppressed. At this time, palladium and holmium consume silicon of the high-concentration layers 76 and 77 only in an underling part of 13.6 nm, respectively, to form a silicide. Next, the oxidation-resistant metal layer is entirely removed. A schematic view in this state is shown in
As described above, after the ion-implantation for forming the high-concentration layers is performed, metal deposition is carried out without performing heat treatment for impurity activation. Thereafter, by performing heat treatment, formation of the high-concentration Si layer due to impurity activation and formation of the metal silicide are simultaneously achieved. Thus, it is possible to realize a transistor having a work function difference of 0.3 eV or less and a contact resistivity of 8.0×10−10 Ωcm2.
Referring to
The semiconductor device, namely, the inversion mode field-effect transistor illustrated in the figure is characterized in that a gate electrode 28 formed on a gate insulating film 26 comprises a zirconium (Zr) layer 28a and a tungsten (W) layer 28b. By constituting the gate electrode by the metals as described above, it is possible to reduce a resistance as compared to a case where the gate electrode of the transistor is formed of n+ polysilicon. Further, Zr constituting the zirconium layer 28a has a work function same as that of n+ polysilicon. Furthermore, in the gate electrode 28 shown in the figure, the zirconium layer 28a is covered with the tungsten layer 28b (preferably formed simultaneously with the tungsten layer 36 on source/drain regions) having an oxidation-resistant function. Therefore, it is possible to prevent oxidation of the zirconium layer 28a during annealing.
When the gate electrode is formed by n+ polysilicon, a depletion layer formed along a surface of a channel region becomes thick. This brings about the same disadvantage as that caused in a case where a gate insulating film becomes thick. However, when the gate electrode 28 is formed of a metal layer, such as the zirconium layer 28a, there is an effect that the depletion layer on the surface of the channel region can be reduced in thickness.
Referring to
Further, the p-channel transistor illustrated in the figure has a gate electrode 28 having a structure comprising a palladium layer 28c and a tungsten layer 28d formed on a gate insulating film 26. Side surfaces of the gate insulating film 26 and the gate electrode 28 are covered with side walls 30. As described above, as the gate electrode 28, the palladium layer 28c is formed which is a metal having a work function same as that of p+ polysilicon and a lower resistance. Therefore, as compared to a case where the gate electrode is formed of p+ polysilicon, it is possible to reduce a resistance and to reduce a thickness of a depletion layer.
Referring to
On a surface of each of the source/drain regions 56, a contact region is formed. In the example shown in the figure, the contact region comprises a holmium silicide layer 62 and a tungsten layer 64. This structure is obtained by performing annealing in a state where the holmium layer as a low-work-function metal layer is covered with the tungsten layer as an oxidation-resistant metal layer, like in the other embodiments.
In the example shown in the figure, a gate insulating film 58 and a gate electrode 60 are formed on the n-type semiconductor layer 54 forming the channel region. The gate electrode 60 comprises a palladium layer 60a and a tungsten layer 60b.
The gate electrode 60 shown in
Referring to
A contact region in this example comprises a palladium silicide (Pd2Si) layer 62a and a tungsten layer 64. The contact region shown in the figure is also obtained by performing annealing in a state where the palladium layer as a low-work-function metal layer is covered with the tungsten layer, as described above. With this structure, it is possible to remarkably reduce a resistance of the contact region, like in the other embodiments.
Further, on the channel region, a gate insulating film 58 is formed and, on the gate insulating film 58, a gate electrode 60 comprising a zirconium layer 60c and a tungsten layer 60d is formed.
With this structure also, a resistance of the gate electrode 60 can be reduced as compared to a case where polysilicon is used. Like in
In the cases of the n-channel transistors shown in
As regards the gate electrode, zirconium is used in
In the present invention, by performing annealing in a state where the low-work-function metal layer is covered with the oxidation-resistant metal layer, it is possible to form the silicide layer having an extremely low resistance. Therefore, a high-performance semiconductor device can be constructed. Further, the present invention is applicable not only to a MOSFET but also to other various types of semiconductor devices having a contact region.
Description Of Reference Numerals
| Number | Date | Country | Kind |
|---|---|---|---|
| 2008-279536 | Oct 2008 | JP | national |
| Filing Document | Filing Date | Country | Kind | 371c Date |
|---|---|---|---|---|
| PCT/JP2009/068233 | 10/23/2009 | WO | 00 | 4/27/2011 |
| Publishing Document | Publishing Date | Country | Kind |
|---|---|---|---|
| WO2010/050405 | 5/6/2010 | WO | A |
| Number | Name | Date | Kind |
|---|---|---|---|
| 20020111018 | Tai | Aug 2002 | A1 |
| 20030045098 | Verhaverbeke et al. | Mar 2003 | A1 |
| 20030209715 | Ikeda et al. | Nov 2003 | A1 |
| 20040080001 | Takeuchi | Apr 2004 | A1 |
| 20050139926 | Shimizu et al. | Jun 2005 | A1 |
| 20060051961 | Cabral et al. | Mar 2006 | A1 |
| 20060071291 | Yagishita | Apr 2006 | A1 |
| 20060134848 | Lander et al. | Jun 2006 | A1 |
| 20060163670 | Ellis-Monaghan et al. | Jul 2006 | A1 |
| 20060211244 | Deshpande et al. | Sep 2006 | A1 |
| 20060258154 | Sandhu et al. | Nov 2006 | A1 |
| 20060273409 | Lee et al. | Dec 2006 | A1 |
| 20070052039 | Iinuma et al. | Mar 2007 | A1 |
| 20080014666 | Takayama et al. | Jan 2008 | A1 |
| 20080191285 | Ko et al. | Aug 2008 | A1 |
| 20080251855 | Besser | Oct 2008 | A1 |
| 20090011537 | Shimizu et al. | Jan 2009 | A1 |
| 20090057788 | Hattendorf et al. | Mar 2009 | A1 |
| 20090129174 | Madurawe | May 2009 | A1 |
| 20100059830 | Ohmi et al. | Mar 2010 | A1 |
| Number | Date | Country |
|---|---|---|
| 2347789 | Sep 2000 | GB |
| 11-26397 | Jan 1999 | JP |
| 2000-252370 | Sep 2000 | JP |
| 2001-015453 | Jan 2001 | JP |
| 2003-249660 | Sep 2003 | JP |
| 2003-332259 | Nov 2003 | JP |
| 2005-191354 | Jul 2005 | JP |
| 2007-067225 | Mar 2007 | JP |
| 2008-529302 | Jul 2008 | JP |
| 10-2005-009447 | Sep 2005 | KR |
| 2008007748 | Jan 2008 | WO |
| Entry |
|---|
| Translation of JP2003-249660 (Sep. 2003) 46 pages. |
| Office Action mailed Nov. 23, 2012 in the corresponding Korean Application No. 10-2012-7024359. |
| Number | Date | Country | |
|---|---|---|---|
| 20110198702 A1 | Aug 2011 | US |
