Claims
- 1. A multilayer integrated circuit structure, comprising:a semiconductor substrate having a surface, a plurality of semiconductor devices having been provided in or on the surface of said substrate, further conductive points of electrical contact having been provided in or on the surface of said substrate; first metal plugs being provided on the surface of the substrate, said first metal plugs being imbedded in a first layer of dielectric deposited over the surface of said substrate, said first metal plugs being aligned with said conductive points of electrical contact having been provided in or on the surface of said substrate, said first metal plugs having a surface comprising a first surface area and a therein centrally located second surface area, said second surface being smaller than said first surface by a measurable amount; a second layer of dielectric deposited over the surface of said first layer of dielectric, including the surface of said first metal plugs; an etch stop layer deposited of the surface of said second layer of dielectric, said etch stop layer having been patterned and etched, creating openings in said etch stop layer that align with said second surface area of said first metal plugs, exposing the surface of said first layer of dielectric, said openings in said etch stop layer having a surface area that is about equal to said second surface area of said first metal plugs; a third layer of dielectric deposited over the surface of said etch stop layer, including the exposed surface of said second layer of dielectric; first openings created in said third layer of dielectric, said first openings having sloping sidewalls, said first openings in said third layer of dielectric having a surface area that is about equal to said first surface area of said first metal plugs, said first openings in said third layer of dielectric extending to said openings created in said layer of etch stop; second openings created in said second layer of dielectric, said second openings having sloping sidewalls, said second openings in said second layer of dielectric extending from said openings created in said layer of etch stop to said second surface of said first metal plugs; a barrier layer deposited over sidewalls of said first openings in said third layer of dielectric, over said second openings in said second layer of dielectric, over said second surface of said first metal plugs; and a layer of conductive material deposited over the surface of said barrier layer, excess conductive material having been removed from above the surface of said third layer of dielectric, furthermore said barrier layer having been removed from above the surface of said second layer of dielectric.
- 2. The structure of claim 1, with the addition of a seed layer deposited over the surface of said barrier layer, said seed layer equally having been removed from above the surface of said second layer of dielectric.
- 3. The structure of claim 1, said conductive points of electrical contact having been provided in or on the surface of said substrate comprising copper.
- 4. The structure of claim 1, said layer of conductive material deposited over the surface of said barrier layer comprising copper.
- 5. The structure of claim 2, said seed layer comprising copper.
Parent Case Info
This is a division of patent application Ser. No. 09/859,353, filing date May 18, 2001, now U.S. Pat. No. 6,649,517, Novel Copper Metal Structure For The Reduction Of Intra-Metal Capacitance, assigned to the same assignee as the present invention.
US Referenced Citations (8)