Patent Application
20240178159
The present disclosure relates generally to the field of semiconductor packaging. More particularly, the present disclosure relates to a coreless substrate package and a method for making the same.
As known in the art, Chip-on-Wafer-on-Substrate (CoWoS) is a 2.5D wafer-level multi-chip packaging technology that incorporates multiple dies side-by-side on a silicon interposer substrate in order to achieve better interconnect density and performance. Individual chips are bonded through micro-bumps on the silicon interposer substrate forming a chip-on-wafer (CoW). The CoW is then subsequently thinned such that the through substrate via (TSV) perforations are exposed. C4 bumps formation and singulation are then carried out. A CoWoS package is completed through bonding to a package substrate.
The core of the package substrate is typically made of woven glass layers pre-impregnated with an epoxy resin material, such as the prepreg laminate FR-4 commonly used for printed circuit boards. Connection pads and conductive copper traces are then formed on the core to provide the interconnection between the die and the system to which it is mounted. Using a core material increases the thickness of the package substrate which also increases the profile of the overall package thickness, and the routing between the upper layers and lower signal layers also get longer due to the thickness of the core material.
It is one object of the present disclosure to provide a coreless substrate package in order to solve the prior art deficiencies or shortcomings.
One aspect of the present disclosure provides a coreless substrate package including a coreless substrate; a package device mounted on a coreless substrate, wherein the package device comprises a function silicon die, wherein the function silicon die has an active front side facing downwardly to the coreless substrate, and an exposed, passive rear side opposite to the active front side, wherein the package device further comprises an encapsulant covering peripheral sidewalls of the function silicon die; an underfill material filling into a space between the package device and the coreless substrate; a stiffener ring disposed on a top surface of the coreless substrate along perimeter of the coreless substrate; and a gap fill material disposed in a gap between the stiffener ring and the package device.
According to some embodiments, the coreless substrate has a dimension of greater than 45 mm×45 mm.
According to some embodiments, a distance between an inner sidewall surface of the stiffener ring and a sidewall surface of the package device is not less than 10 mm.
According to some embodiments, the coreless substrate comprises at least one insulating layer and conductive layers in the at least one insulating layer.
According to some embodiments, the at least one insulating layer comprises Ajinomoto Build-up Film (ABF), polyimide, or prepreg.
According to some embodiments, the conductive layers comprise copper.
According to some embodiments, the conductive layers comprise connection pads exposed from the top surface of the coreless substrate and ball grid array (BGA) ball pads disposed at a bottom surface of the coreless substrate.
According to some embodiments, the package device is mounted on the top surface of the coreless substrate in a flip-chip fashion and is electrically connected to the connection pads through a plurality of C4 bumps
According to some embodiments, BGA balls are disposed on the BGA ball pads, respectively.
According to some embodiments, the coreless substrate does not include a permanent core structure.
According to some embodiments, the stiffener ring is coplanar with the package device and is affixed onto the top surface of the coreless substrate by using an adhesive layer.
According to some embodiments, the gap fill material comprises a molding compound.
According to some embodiments, the gap fill material and the underfill material have different compositions.
According to some embodiments, the gap fill material and the encapsulant have different compositions.
According to some embodiments, the gap fill material has a top surface that is flush with a top surface of the stiffener ring, a top surface of the encapsulant, and the passive rear surface of the function silicon die.
According to some embodiments, the package device comprises a Chip-on-Wafer package or a fan-out package.
According to some embodiments, the function silicon die comprises a System on Chip (SoC) die, an RF die, or an application processor (AP) die.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings:
In the following detailed description of embodiments of the invention, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific preferred embodiments in which the disclosure may be practiced.
These embodiments are described in sufficient detail to enable those skilled in the art to practice them, and it is to be understood that other embodiments may be utilized and that mechanical, chemical, electrical, and procedural changes may be made without departing from the spirit and scope of the present disclosure. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of embodiments of the present invention is defined only by the appended claims.
It will be understood that when an element or layer is referred to as being “on”, “connected to” or “coupled to” another element or layer, it can be directly on, connected or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly connected to” or “directly coupled to” another element or layer, there are no intervening elements or layers present. Like numbers refer to like elements throughout. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
The present disclosure pertains to a coreless substrate package with a big package size (substrate dimension greater than 45 mm×45 mm). Coreless substrates are preferred for their superior electrical performance and thin profile compare to conventional substrates with core. However, one major concern with coreless substrates is warpage control. The instant invention addresses this issue.
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According to an embodiment, the function silicon die 101 has an active front side 101a facing downwardly to the coreless substrate 20, and an exposed, passive rear side 101b opposite to the active front side 101a. According to an embodiment, the peripheral sidewalls 101w of the function silicon die 101 are covered with an encapsulant 110.
In a case that the package device 10 is a fan-out package, for example, a re-distribution layer (RDL) structure 120 may be formed on the active front side 101a and the encapsulant 110. According to an embodiment, for example, the RDL structure 120 may comprise a dielectric layer 121 and metal interconnect structures 122 in or on the dielectric layer 121. According to an embodiment, for example, the dielectric layer 121 may comprise silicon oxide or silicon nitride, but not limited thereto. According to an embodiment, for example, the metal interconnect structures 122 may comprise copper, tungsten, aluminum, titanium, titanium nitride, but not limited thereto.
According to an embodiment, the coreless substrate 20 has a dimension of greater than 45 mm×45 mm and may comprise at least an insulating layer 210 and conductive layers 212 in the insulating layer 210. According to an embodiment, the coreless substrate 20 does not include a permanent core structure. According to an embodiment, for example, the insulating layer 210 may comprise Ajinomoto Build-up Film (ABF), polyimide, prepreg, or any suitable build-up film materials, but not limited thereto. According to an embodiment, for example, the conductive layers 212 may comprise copper, but not limited thereto. According to an embodiment, for example, the conductive layers 212 may be formed by electroplating methods, but not limited thereto.
According to an embodiment, for example, the conductive layers 212 may comprise connection pads 212a exposed from the top surface 20a of the coreless substrate 20 and ball grid array (BGA) ball pads 212b disposed at the bottom surface 20b of the coreless substrate 20. According to an embodiment, for example, the package device 10 is mounted on the top surface 20a of the coreless substrate 20 in a flip-chip fashion and may be electrically connected to the connection pads 212a through a plurality of C4 bumps BC comprising, for example, copper and solder. The coreless substrate package 1 may be mounted on a system board or a mother board 2 through a plurality of BGA balls BA formed on the BGA ball pads 212b, respectively.
According to an embodiment, for example, the space between the package device 10 and the coreless substrate 20 may be filled with an underfill material 310. The C4 bumps BC are surrounded by the underfill material 310. To cope with the warpage problem of the coreless substrate package 1, a stiffener ring 40 such as a metal ring is disposed on the top surface 20a of the coreless substrate 20 along the perimeter of the coreless substrate 20. According to an embodiment, for example, the stiffener ring 40 is coplanar with the package device 10 and may be affixed onto the top surface 20a of the coreless substrate 20 by using an adhesive layer 410. According to an embodiment, for example, the distance d between the inner sidewall surface of the stiffener ring 40 and the sidewall surface of the package device 10 is not less than 10 mm.
According to an embodiment, for example, a gap fill material 50 such as molding compound or an underfill material is disposed in the gap between the stiffener ring 40 and the package device 10. According to an embodiment, for example, the gap fill material 50 and the underfill material 310 may have different compositions. According to an embodiment, for example, the gap fill material 50 and the encapsulant 110 may have different compositions. According to an embodiment, for example, the gap fill material 50 may have a top surface 50a that is flush with the top surface 40a of the stiffener ring 40, the top surface 110a of the encapsulant 110, and the passive rear surface 101b of the function silicon die 101.
According to an embodiment, the peripheral sidewalls 101w of the function silicon die 101 are covered with an encapsulant 110. In a case that the package device 10 is a fan-out package, for example, a re-distribution layer (RDL) structure 120 may be formed on the active front side 101a and the encapsulant 110. C4 bumps BC comprising copper and solder may be formed on the RDL structure 120 for further connection purposes.
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According to an embodiment, for example, the conductive layers 212 may comprise connection pads 212a exposed from the top surface 20a of the coreless substrate 20 and ball grid array (BGA) ball pads 212b disposed at the bottom surface 20b of the coreless substrate 20. According to an embodiment, for example, the package device 10 is mounted on the top surface 20a of the coreless substrate 20 in a flip-chip fashion and may be electrically connected to the connection pads 212a through the C4 bumps BC.
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Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
This application claims the benefit of U.S. Provisional Application No. 63/385,443, filed on Nov. 30, 2022. The content of the application is incorporated herein by reference.
| Number | Date | Country | |
|---|---|---|---|
| 63385443 | Nov 2022 | US |
