This application claims priority from Italian patent application No. MI2002A 001185, filed May 31, 2002, which is incorporated herein by reference.
The present invention relates generally to a method for reading non-volatile memories having at least one pseudo-parallel communication interface.
An embodiment of the invention concerns a testing and debugging method for use at the EWS/Final Test stage of integrated flash memories in PC Bios applications operating on a PCI bus at 33 MHz. The method provides a comprehensive test procedure that covers all possible device defects.
Another embodiment of the invention relates to an electronic memory device which is monolithically integrated on a semiconductor and has a pseudo-parallel interface associated therewith.
Yet another embodiment of the invention particularly relates to a standard flash memory which is integrated with an LPC (Low Pin Count) interfacing block used in normal operation applications, and with a parallel interfacing block primarily used for testing. Accordingly, the memory device incorporates two communication interfaces: namely a serial interface and a parallel or pseudo-parallel interface.
The electronic integrated memory device to which the embodiments of the invention are directed has eleven address outer pins, eight data pins and some control pins, among which are provided a synchronism or clock signal, CLK, and a signal used for setting the two IC interfaces provided.
Currently, testing flux software both for EWS or on-wafer testing and Final Test for testing on an assembled device has been intended for operation in the parallel mode.
Briefly, all the addresses and data under consideration have been used in the parallel mode during testing operation, whereas only the clock signal CLK and another four pins are necessary for the serial communication protocol.
As it is well known in the art, reading a memory location from the cell matrix requires that the address of the location is input first. This operation is usually performed according to a timing procedure, shown in
Referring to the timing diagram of
Thus, it is only at the end of a signal cycle RC that a complete address of the memory location to be read can be fully reconstructed. In other words, all of the internal reading timings start only at the end of the cycle RC.
More particularly, the rising edge of the control signal RC will cause the known ATD (Address Transition Detection) pulse, which will set off the whole reading mechanism.
As mentioned, the rising edge of the signal RC sets off the ATD signal, which in turn will generate the signal READING and consequently the signal SALATCH, which stores data output from the reading sense amplifiers.
It can be appreciated that the address inputting mechanism described above is fairly complicated and it involves, especially while testing, a more elaborate control software and also extended duration for the whole testing procedure, which immediately results in increased cost of the integrated-memory-circuit product.
Therefore, a need has arisen for a novel testing procedure with appropriate functional features that allow the procedure to be carried out through the parallel interface, so that higher output levels than in the prior art can be achieved.
One embodiment of the invention involves exploiting the falling edge of the control signal RC to generate an additional ATD pulse and thus start a new reading, after storing only the columns in the internal addresses.
More specifically, this embodiment includes a method for testing non-volatile memory devices that have at least one parallel communication interface, and have a matrix of non-volatile memory cells with respective reading, changing, and erasing circuits, wherein during the testing step, a reading mode is entered for reading a memory location upon the rising edge of a control signal producing a corresponding signal; characterized in that a subsequent reading operation is started also upon the falling edge of said control signal.
Another embodiment of the invention relates to an electronic memory device being monolithically integrated on a semiconductor and having at least one parallel interface and a matrix of non-volatile memory cells with respective row and column decoding circuits and circuits for reading, changing, and erasing the contents of the memory cells, characterized in that it comprises a first generator block for generating impulsive row and column addressing signals, said first generator block receiving a control signal, and comprises a second generator block for generating an ATD signal, said second generator block receiving in turn said control signal and being operatively linked to both the rising and the falling edges of said control signal.
Features and potential advantages of the various aspects of the invention should become apparent from the following description of embodiments thereof, given by way of non-limitative examples with reference to the accompanying drawings.
Referring to
The device 1 is a non-volatile memory integrated on a semiconductor, such as a flash EEPROM, of a kind that can be electrically written and erased. However, the following considerations can be applied to other memory devices as well.
The device 1 has a parallel interface 2 for testing operations.
The device 1 conventionally comprises a matrix 3 of non-volatile memory cells and respective row and column decoding circuits, as well as circuit portions (not shown because they are conventional) for reading, changing, and erasing data stored in the memory.
The device 1 also comprises a number of circuit blocks, to be described herebelow, which are interlinked through a set of bus connections.
A first block 7 is a pulse generator that receives a control signal RC.
The block 7 outputs two different types of pulses: a column pulse Col-Pulse and a row pulse Row-Pulse, both applied to an address storage block 6.
The storage block 6 comprises a number of latch registers and receives, additionally to the signals from the block 7, an eleven-bit address on an address bus ADD<10:0>, and temporarily stores the addresses of certain locations of the memory 3.
The storage block 6 has an output connected to the memory-cell matrix 3 through a twenty-two bit internal address bus ADD—INT<21:0>. The matrix 3 outputs data through a data bus DATA<7:0>.
A branch of the signal RC is applied to a block 5 generating ATD signals, this block outputting an impulsive signal ATD—Pulse applied to a read-timing circuit block 4.
This block 4 outputs a pair of signals READING and SALATCH, which are transmitted to the matrix 3 in order to enable data reading operations.
Referring to
It can be seen in
Briefly, this subsequent reading operation will be performed upon the pulse Col—Pulse being received, before the pulse Row—Pulse is also received.
In this way, by suitably shifting the addresses through the testing procedure managing programs, the whole matrix can be read thus significantly reducing testing time, since at each cycle of the control signal RC two memory locations are read, instead of one as in the prior art.
Of course, the first ATD pulse 9 will in turn set off the whole mechanism that issues the read enabling signals READING and SALATCH for the sense amplifiers.
As a result, the second ATD pulse 8, produced on the falling edge of the signal RC, will also activate a full reading cycle upon the read enabling signals READING and SALATCH being issued.
The reading mechanism takes a shorter time than 100 ns, this typically being the shortest duration of the RC pulse as per the specifications of integrated memory circuits.
The above-described embodiments of this invention do solve the technical problem, and offer a number of advantages, the first advantage is that reading time during the testing procedure is dramatically reduced because the memory can be accessed twice during a single cycle of the control signal RC.
Furthermore, all the above is achieved at the expense of only minor modifications to the memory device construction and at low cost.
An integrated circuit, such as the memory circuit 1 of
From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention. For example, the above technique can also be used to write data to a memory.
Number | Date | Country | Kind |
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