Patent Application
20250204185
The present disclosure relates to the technical field of display, and particularly to a display panel and a display device.
As shown in
Therefore, it is necessary to propose a technical solution to solve the problem that some input pins far from the redundant pins are tilted and cannot be attached to the display panel, which causes the display panel to fail to work normally.
The present disclosure provides a display panel and a display panel to simplify the circuit structure complexity of a display panel for multi-gray level display.
To solve the above technical problems, the technical solutions provided by the disclosure as follows. The display panel is provided in present disclosure. The display panel includes a display area and a pad area. The pad area is disposed on one side of the display area. The display panel includes:
The present disclosure further provides a display device, the display device includes the display panel described above.
Beneficial effect are as follows.
The present disclosure provides a display panel and a display device, the thickness of the first pin is different from the thickness of the second pin to compensate for the height difference caused by the partial warpage of the pins on the driving chip when binding the driving chip, so as to ensure that the driving chip can be well attached to the display panel.
In order to explain embodiments or technical solutions in the prior art more clearly, the following will briefly introduce drawings involved in a following description of the embodiments or the prior art. Obviously, the drawings in the following description are merely inventions. Those of ordinary skill in the art can obtain other drawings based on these drawings without creative work.
Reference signs are as follows:
300, display panel; 300a, display area; 300b, pad area; 300b2, blank area; 31, array substrate; 311, first conductive pad; 311a, first bonding surface; 312, second conductive pad; 312a, second bonding surface; 313, substrate; 313a, bearing surface; 314, light-shielding layer; 3141, light-shielding pattern; 3142, light-shielding piece; 3143, first light-shielding member; 3144, second light-shielding member; 315, buffer layer; 316, semiconductor layer; 3161, active pattern; 3162, semiconductor member; 317, gate insulating layer; 318, first metal layer; 3181, gate; 3182, first metal member; 3183, second metal member; 3184, fifth metal member; 3185, sixth metal member; 3186, ninth metal member; 319, interlayer insulating layer; 319a, third through hole; 319b, fourth through hole; 320, second metal layer; 3201, source electrode; 3202, drain electrode; 3203, third metal member; 3204, fourth metal member; 3205, seventh metal member; 3206, eighth metal member; 3207, tenth metal member 321, planarization layer; 321a, first opening; 322, first transparent conductive layer; 323, passivation layer; 323a, second opening; 323b, third opening; 324, second transparent conductive layer; 3241, pixel electrode; 3242, first transparent conductive member; 3243, second transparent conductive member; 3244, third transparent conductive member; 3245, fourth transparent conductive member; 3246, fifth transparent conductive member; 325, conductive member; 326, third conductive pad; 326a, third bonding surface; 327, redundant conductive pad; 327a, redundant bonding surface; 328, fourth conductive pad; 328a, fourth bonding surface; 329, fifth conductive pad; 329a, fifth bonding surface; 33, driving chip; 330, base body; 331, first pin; 332, second pin; 333, third pin; 334, redundant pin; 335, fourth pin; 336, fifth pin; 330a, first edge; 330b, second edge; 34, flexible printed circuit board; 341, main body; 342, first binding part; 343, second binding part; 401, first conductive adhesive layer; 401a, first surface; 402, second conductive adhesive layer; 402a, second surface; 40a, conductive particles.
In order to make the purpose, technical solutions, and effects of this disclosure clearer and clearer, the following further describes this disclosure in detail with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described here are only used to explain the present disclosure, and are not used to limit the present disclosure.
In view of the problem of the background technology, the inventor found that a main reason for a lifting of some pins on a driving chip is that the pins on the driving chip are unevenly distributed, a supporting force of the pins is unevenly distributed, and the uneven distribution of the supporting force causes some of the pins on the driving chip to be lifted and cannot be attached to pads of a display panel. In view of this, in this disclosure, the first conductive adhesive layer is electrically connected to the first conductive pads and the first pins, the second conductive adhesive layer is electrically connected to the second conductive pads and the second pins, a distance from the first conductive adhesive layer, close to the first pins, to the substrate is different from a distance from a surface of the second conductive adhesive layer, close to the second pins, to the substrate, so that the elevated pins on the driving chip are combined with either the conductive first conductive adhesive layer or the conductive second conductive adhesive layer, whichever has a larger distance to the substrate, so as to ensure that the pins of the driving chip is elevated upwards. The pins can thus be attached to the display panel normally. Wherein, the first conductive pad and the second conductive pad are both disposed on the bearing surface of the substrate, and both are located in the pad area.
Please refer to
In this embodiment, a portion of the display panel 300 corresponding to the display area 300a is used for display. In the display area 300a, the array substrate 31 includes a plurality of thin film transistors disposed in an array, pixel electrodes, common electrodes, scan lines, and data lines.
In this embodiment, the pad area 300b is provided with a plurality of conductive pads, and the driving chip 33 is attached to the plurality of conductive pads of the pad area 300b, that is, the driving chip 33 of the display panel 300 is attached on glass (Chip On Glass, COG). Part of the conductive pads is used to input electrical signals and transmit to the driving chip 33, and to provide working signals for the driving chip 33 to work; part of the conductive pads is used to output electrical signals to the display area 300a of the display panel 300 to provide display signals for the display panel 300. The plurality of conductive pads includes a plurality of first conductive pads 311 and a plurality of second conductive pads 312. The plurality of first conductive pads 311 are disposed side by side in a straight line along a first direction, and the plurality of second conductive pads 312 are disposed side by side in a straight line along the first direction; the second conductive pads 312 are located on one side of the first conductive pad 311 away from the display area 300a, and the plurality of second conductive pads 312 and the plurality of first conductive pads 311 are disposed in a staggered manner along a second direction, and then a wiring connected to the conductive pad 312 can extend from an area between two adjacent first conductive pads 311. The second direction is a direction that the display area 300a points toward the pad area 300b, and the first direction is perpendicular to the second direction.
In this embodiment, the driving chip 33 includes a base 330, a plurality of first pins 331, and a plurality of second pins 332. The driving chip 33 includes a first edge 330a and a second edge 330b. The first edge 330a is opposite to the second edge 330b. When the driving chip 33 is attached to the array substrate 31, the first edge 330a is close to the display area 300a and the second edge 330b is far away from the display area 300a. The plurality of first pins 331 and the plurality of second pins 332 are disposed on the base 330 and close to the second edge 330b. A distance from the first pins 331 to the first edge 330a is greater than a distance from the first pins 331 to the second edge 330b, and a distance from the second pins 332 and the first edge 330a is greater than a distance from the second pins 332 to the second edge 330b. The plurality of first pins 331 are located on a side of the plurality of second pins 332 away from the second edge 330b, that is, the second pins 332 are located on one side of the first pins 331 away from the display area 100a, and the first pins 331 and the second pins 332 are disposed staggered along the second direction.
In this embodiment, the array substrate 31 includes a substrate 313, a light-shielding layer 314, a buffer layer 315, a semiconductor layer 316, a gate insulating layer 317, a first metal layer 318, an interlayer insulating layer 319, a second metal layer 320, a planarization layer 321, a first transparent conductive layer 322, a passivation layer 323, and a second transparent conductive layer 324 stacked in sequence.
In this embodiment, the substrate 313 is a glass substrate, the substrate 313 includes a bearing surface 313a, and the bearing surface 313a is a flat horizontal surface.
In this embodiment, the light-shielding layer 314 includes a light-shielding pattern 3141 and a light-shielding piece 3142. The light-shielding pattern 3141 is formed on the bearing surface 313a of the substrate 313 and located in the display area 300a. The light-shielding pattern 3141 is configured for light-shielding. The light-shielding piece 3142 is formed on the substrate 313 and located in the pad area 300b, the light-shielding piece 3142 is disposed correspondingly to the second conductive pads 312. The light-shielding layer 314 is a metal layer. A thickness of the light-shielding layer 314 is about 450 angstroms to 550 angstroms. The light-shielding layer 314 is made of a material selected from a group consisting of molybdenum, aluminum, titanium, copper, and silver.
In this embodiment, the buffer layer 315 covers the light-shielding layer 314 and the substrate 313, and the buffer layer 315 is located in the display area 300a and the pad area 300b. A thickness of the buffer layer 315 is 2500 angstroms to 3500 angstroms. The buffer layer 315 includes a silicon nitride layer and a silicon oxide layer. The silicon nitride layer is close to the substrate 313 and the silicon oxide layer is away from the substrate 313.
In this embodiment, the semiconductor layer 316 is formed on the buffer layer 315, and the semiconductor layer 316 includes active pattern 3161. The active pattern 3161 is located in the display area 300a and disposed corresponding to the light-shielding pattern 3141. The semiconductor layer 316 is made from a material selected from any one of amorphous silicon, polysilicon, and metal oxide. A thickness of the semiconductor layer 316 is 400 angstroms to 500 angstroms.
In this embodiment, the gate insulating layer 317 covers the semiconductor layer 316 and the buffer layer 315, and the gate insulating layer 317 is located in the display area 300a and the pad area 300b. A thickness of the gate insulating layer 317 is 1000 angstroms to 1500 angstroms. The gate insulating layer 317 is made of silicon nitride or silicon oxide.
In this embodiment, the first metal layer 318 is disposed on the gate insulating layer 317. The first metal layer 318 includes a gate 3181, a first metal member 3182, and a second metal member 3183. The gate 3181 is located in the display area 300a and disposed corresponding to the source patterns 3161. The first metal member 3182 and the second metal member 3183 are both located in the pad area 300b, the second metal member 3183 is located on one side of the first metal member 3182 away from the display area 300a, the second metal member 3183 is located directly above the light-shielding piece 3142, a thickness of the gate 3181, a thickness of the first metal member 3182, and a thickness of the second metal member 3183 are same. A thickness of the first metal layer 318 is between 2500 angstroms and 3500 angstroms. The first metal layer 318 is made from a material selected from a group consisting of molybdenum, aluminum, titanium, copper, and silver.
In this embodiment, the interlayer insulating layer 319 covers the first metal layer 318 and the gate insulating layer 317, and the interlayer insulating layer 319 is located in the display area 300a and the pad area 300b. A thickness of the interlayer insulating layer 319 is 5500 angstroms to 6500 angstroms. The interlayer insulating layer 319 is made from a material selected from at least one of silicon nitride and silicon oxide.
In this embodiment, the second metal layer 320 is disposed on the interlayer insulating layer 319. The second metal layer 320 includes a source electrode 3201, a drain electrode 3202, a third metal member 3203, and a fourth metal member 3204. The source electrode 3201 and the drain electrode 3202 are located in the display area 300a and are disposed on opposite sides of the gate 3181. The source electrode 3201 is in contact with the active pattern 3161 through a first through hole penetrating the interlayer insulating layer 319 and the gate insulating layer 317, and the drain electrode 3202 is in contact with the active pattern 3161 through a second through hole penetrating the interlayer insulating layer 319 and the gate insulating layer 317. The third metal member 3203 is disposed corresponding to the first metal member 3182 and electrically connected to the first metal member 3182 through a third through hole 319a penetrating the interlayer insulating layer 319, and the fourth metal member 3204 is disposed corresponding to the second metal member 3183 and electrically connected to the second metal member 3183 through a fourth through hole 319b penetrating the interlayer insulating layer 319. The source electrode 3201, the drain electrode 3202, the third metal member 3203, and the fourth metal member 3204 have same thickness. A thickness of the second metal layer 320 is about 4000-6500 angstroms. A material of the second metal layer 320 is selected from a group consisting of molybdenum, aluminum, titanium, copper, and silver.
In this embodiment, the planarization layer 321 covers the second metal layer 320 and the interlayer insulating layer 319. The planarization layer 321 includes a first opening 321a located in the pad area 300b. The first opening 321a exposes the third metal member 3203 and the fourth metal members 3204. A thickness of the planarization layer 321 is 2.0 micrometers to 3.0 micrometers. The planarization layer 321 is made from polyimide or polyacrylate.
In this embodiment, the first transparent conductive layer 322 is formed on the planarization layer 321 and located in the display area 300a, and the first transparent conductive layer 322 is a common electrode layer. A material of the first transparent conductive layer 322 is indium tin oxide. A thickness of the first transparent conductive layer 322 is 500 angstroms to 700 angstroms.
In this embodiment, in the display area 300a, the passivation layer 323 covers the first transparent conductive layer 322; in the pad area 300b, the passivation layer 323 covers the planarization layer 321, the interlayer insulating layer 319, the third metal member 3203, and the fourth metal member 3204. The passivation layer 323 includes a second opening 323a corresponding to the third metal member 3203 and a third opening 323b corresponding to the fourth metal member 3204. A thickness of the passivation layer 323 is 800 angstroms to 1200 angstroms. The passivation layer 323 is made from any one of silicon nitride or silicon oxide.
In this embodiment, the second transparent conductive layer 324 of the display area 300a is formed on the passivation layer 323. The second transparent conductive layer 324 includes a plurality of mutually independent pixel electrodes 3241, a first transparent conductive member 3242, and a second transparent conductive member 3243. At least a part of the first transparent conductive member 3242 is located in the second opening 323a and located on the third metal member 3203, and at least a part of the second transparent conductive member 3243 is located in the third opening 323b and located on the fourth metal member 3204. The pixel electrode 3241, the first transparent conductive member 3242 and the second transparent conductive member 3243 have a same thickness. The second transparent conductive layer 324 is made from indium tin oxide. A thickness of the second transparent conductive layer 324 is 450 angstroms to 550 angstroms.
In this embodiment, the first metal member 3182, the third metal member 3203, and the first transparent conductive member 3242 together form a first conductive pad 311. The first conductive pad 311 includes a first bonding surface 311a for bonding to the driving chip 33. At least a part of the first bonding surface 311a is parallel to the bearing surface 313a. The second metal member 3183, the fourth metal member 3204, and the second transparent conductive member 3243 together form a second conductive pad 312. The second conductive pad 312 includes a second bonding surface 312a for bonding to the driving chip 33. At least part of the second bonding surface 312a is parallel to the bearing surface 313a. A thickness of the first conductive pad 311 is equal to a thickness of the second conductive pad 312. Since the light-shielding piece 3142 is disposed between the second conductive pad 312 and the substrate 313, the second conductive pad 312 is elevated higher relative to the first conductive pad 311, and a distance between the at least a part of the first bonding surface 311a parallel to the bearing surface 313a and the substrate 313 is less than a distance between the at least a part of the second bonding surface 312a parallel to the bearing surface 313a and the substrate 313. As shown in
In this embodiment, as shown in
It should be noted that in other embodiments, the distance from the first bonding surface 311a to the substrate 313 may also be equal to the distance from the second bonding surface 312a to the substrate 313. At this time, the thickness of the first conductive adhesive layer 401 is less than the thickness of the second conductive adhesive layer 401; alternatively, the thickness of the first conductive adhesive layer 401 is less than the thickness of the second conductive adhesive layer 401, in combination with the distance from the first bonding surface 311a to the substrate 313 less than the distance from the second bonding surface 312a to the substrate 313, so that a distance between a first surface 401a of the first conductive adhesive layer 401 close to the first pins 331 and the substrate 313 is less than a distance between a second surface 402a of the second conductive adhesive layer 402 close to the second pins 332 and the substrate 313.
As shown in
In this embodiment, as shown in
It should be noted that the array substrate 31 also includes flexible printed circuit board binding areas (not shown) disposed on opposite sides of the pad area, and the flexible printed circuit board binding area of the array substrate is also provided with pads. The flexible printed circuit board is electrically connected to the bonding pads of the flexible printed circuit board. The existing technology is used here, and no detailed description is given here.
The display panel provided in this embodiment, a light-shielding member is provided under the second conductive pad corresponding to the elevated second pins on the driving chip to raise the second conductive pad. The elevated second conductive pads and the elevated second pins can be attached and electrically connected.
Please refer to
Compared with the display panel shown in
Please refer to
Compared with the display panel shown in
Please refer to
Specifically, the light-shielding layer 314 includes a first light-shielding member 3143 provided in the pad area 300b and a second light-shielding member 3144 provided in the pad area 300b. The first film layer is the first light-shielding member 3143, and the second film layer is the second light-shielding member 3144. The first shading member 3143 is disposed corresponding to each first conductive pad 311, each second shading member 3144 is disposed corresponding to each second conductive pad 312, and a thickness of the first shading member 3143 is less than a thickness of the second shading member 3144. It is understandable that the first film layer can also be other film layers between the first conductive pads and the substrate, and the second film layer can also be other film layers between the plurality of the second conductive pad and the substrate, such as the first film layer and the second film layer are in a same layer as the active pattern.
In the display panels shown in
Please refer to
In this embodiment, the number of film layers of the first conductive pad 311 is less than the number of film layers of the second conductive pad 312. Specifically, the first conductive pad 311 includes the first metal member 3182, the third metal member 3203, and the first transparent conductive member 3242; and the second conductive pad 312 includes the second metal member 3183, the fourth metal member 3204, the second transparent conductive member 3243, and the conductive member 325. The conductive member 325 is disposed on the second transparent conductive member 3243, that is, the number of film layers of the second conductive pad 312 is increased, so that the number of film layers of the first conductive pad 311 is less than the number of film layers of the second conductive pad 312. Wherein, the conductive member 325 may be a transparent conductive layer or a metal conductive layer. It is understandable that the first conductive pad 311 can also include the first metal member 3182 and the third metal member 3203, and the second conductive pad 312 can include the second metal member 3183, the fourth metal member 3204 and the second transparent conductive member 3243, such that the number of film layers of the first conductive pad 311 is reduced, so that the number of film layers of the first conductive pad 311 is less than the number of film layers of the second conductive pad 312.
The display panel shown in
Please refer to
Specifically, each the first conductive pad 311 includes the first metal member 3182, the third metal member 3203, and the first transparent conductive member 3242; and the second conductive pad 312 includes the second metal member 3183, the fourth metal member 3204, and the second transparent conductive member 3243. A thickness of the first metal member 3182 is equal to a thickness of the second metal member 3183, a thickness of the third metal member 3203 is less than a thickness of the fourth metal member 3204, and a thickness of the first transparent conductive member 3242 is equal to a thickness of the second transparent conductive member 3243. It is understandable that a thickness of the first metal member 3182 can be less than a thickness of the second metal member 3183, a thickness of the third metal member 3203 is equal to a thickness of the fourth metal member 3204, and a thickness of the first transparent conductive member 3242 is equal to a thickness of the second transparent conductive member 3243.
The display panel shown in
The display panel shown in
It should be noted that, as shown in
Please refer to
In this embodiment, the driving chip 33 includes the first pins 331, the second pins 332, the third pins 333, and the redundant pins 334. The driving chip 33 includes a first edge 330a and a second edge 330b. The first edge 330a is opposite to the second edge 330b. When the driving chip 33 is attached to the display panel 300, the first edge 330a is close to the display area 300a, and the second edge 330b is away from the display area 300a. The redundant pins 334 are disposed side by side in a straight line close to the first edge 330a so that the plurality of redundant pins 334 are disposed close to the display area 300a, and the redundant pins 334 will not be connected to electrical signals. The first pins 331 are disposed side by side in a straight line close to the second edge 330b, the plurality of the second pins 332 and the plurality of the third pins 333 are located on the side of the plurality of the first pins 331 away from the display area 300a, and the plurality of the second pins 332 are disposed on opposite sides of the plurality of the third pins 333 along the first direction, a part of the first pin 331 is disposed adjacent and staggered disposed to the second pins 332 along the second direction and the part of the first pins 331 are located on opposite sides of the plurality of redundant pins 334 along the first direction, the other part of the first pins 331 is disposed adjacent and staggered disposed to the third pin 333 along the second direction and the plurality of the second pins 332 are symmetrically located on opposite sides of the plurality of redundant pins 334 along the first direction. A thickness of the first pins 331, a thickness of the second pins 332, a thickness of the third pins 333, and a thickness of the redundant pins 334 are all same.
When the driving chip 33 is attached to the display panel 300, the plurality of the redundant pins 334 and the plurality of the redundant conductive pads 327 are disposed one-to-one and electrically connected to each other, the plurality of the first pins 331 and the plurality of the first conductive pads 311 are disposed one-to-one and electrically connected to each other. The plurality of the third pins 333 and the plurality of the third conductive pads 326 are disposed one-to-one, and a conductive adhesive layer is filled between the third bonding surface 326a and the third pins 333. The wiring area 300b1 on opposite sides of the plurality of redundant conductive pad 327 is provided with a plurality of wirings. As a result, the redundant conductive pad 327 is not provided in the wiring area 300b1. The driving chip 33 is without support and is tilted down in the wiring area 300b1. Correspondingly, a plurality of the second pins 332 of the driving chip 33 are elevated, the plurality of the raised second pins 332 and a second bonding surface 312a of the elevated second conductive pad 312 are combined by a second conductive adhesive layer 402 filled between the two, and the second pins 332 are electrically connected to the second conductive pads 312, further, the plurality of the second pins 332 can be attached to the array substrate and the second pins 332 are electrically connected to the corresponding second conductive pads 312.
In this embodiment, since the plurality of second pins 332 are located on opposite sides of the plurality of redundant conductive pads 327 along the first direction, a supporting force provided by the redundant conductive pads 327 is different, and the lifted degree of the plurality of second pins 332 is also different. The farther the second pin 332 is from the redundant conductive pad 327, the less the supporting force will be, and the higher the upturn of the second pins 332, the distance between at least part of the second bonding surface 312a of the plurality of second conductive pads 312 parallel to the bearing surface 313a and the substrate 313 increases from close to the third conductive pad 326 to far away from the third conductive pad 326, so as to adapt elevated when the driving chip 33 is attached to the array substrate, the distance from the lifted second pins 332 to the substrate 313 increases from being close to the third conductive pad 326 to away from the third conductive pad 326.
It should be noted that, a distance from the at least part of the first bonding surface 311a of the first conductive pad 311, parallel to the bearing surface, to the substrate less than a distance from at least part of the second bonding surface 312a of the second conductive pad 312, parallel to the bearing surface, to the substrate. A distance from the bearing surface parallel to at least part of the substrate can be achieved by the aforementioned method, which will not be described in detail here.
Please refer to
Specifically, each the fourth conductive pad 328 is consisted of a ninth metal member 3186, a tenth metal member 3207, and a fifth transparent conductive member 3246. The ninth metal members 3186 of the plurality of the fourth conductive pads 328 have same thickness. The fifth transparent conductive members 3246 of the fourth conductive pad 328 have same thickness, and the thickness of the tenth metal members 3207 of at least two rows of the fourth conductive pad 328 increases from close to the display area 300a to far from the display area 300a, so that the distance between the part of the fourth bonding surface 328a of the at least two rows of the fourth conductive pad 328, parallel to the bearing surface 313a, and the substrate 313 increases from being close to the display area 300a to far away from the display area 300a along the second direction.
It should be noted that, along the second direction, the opposite two sides of the plurality of the redundant conductive pads are blank areas without the redundant conductive pads. When the driving chip 33 is attached to the array substrate, the driving chip 33 without support in the blank areas will tilt down and be further away from the display area 300A, the higher the tilt of the fourth pins 335. Correspondingly, the fourth bonding surface 328a of the fourth conductive pads 328 corresponding to the fourth pins 335 needs to be higher. Along the first direction, since the plurality of the fourth conductive pads 328 are located on opposite sides of the plurality of the redundant conductive pads 327 along the first direction, the further the plurality of the fourth conductive pad 328 are from the redundant conductive pad 327, the less the support of the redundant conductive pad 327 is obtained by the fourth conductive pad 328, and the higher the lift of the fourth pins 335 are on the driving chip. Along the first direction, a distance between the at least part of the fourth bonding surfaces 328a of the at least two rows of the fourth conductive pads 328 parallel to the bearing surface 313a and the substrate 313 increases from close to the second conductive pad 312 to away from the second conductive pad 312, and a distance between the at least part of the fourth bonding surface 328a of the fourth conductive pad 328 adjacent to the second conductive pad 312 parallel to the bearing surface 313a and the substrate 313 is greater than a distance between the at least a part of the second bonding surface 312a of the second conductive pads 328 adjacent to the fourth conductive pad 312 parallel to the bearing surface 313a and the substrate 313.
Please refer to
Specifically, since when the driving chip 33 is attached to the display panel 300, one end of the driving chip 33 close to the display area 300a is not supported, and when the plurality of the first pins 331 of the driving chip 33 are attached to the first conductive pads 311 and the third pins 333 are attached to the third conductive pads 326, the end of the driving chip 33 close to the display area 300a is tilted down, and a plurality of the second pins 332 of the driving chip 33 are elevated, and the distance between the at least part of the first bonding surface 311a of the first conductive pad 311, parallel to the bearing surface 313a, to the substrate 313 is less than the distance between the at least part of the second bonding surface 312a of the second conductive pad 312, parallel to the bearing surface 313a, to the substrate 313, so that the elevated second pins 332 of the driving chip 33 is bonded with the elevated second bonding surface 312a of the corresponding second conductive pads 312.
Please refer to
When the driving chip 33 is attached to the array substrate 31, the third conductive pads 326 and the third pins are electrically connected through a conductive adhesive layer, and the first conductive pads 311 and the first pins 331 are electrically connected one-to-one through the first conductive adhesive layer, the second conductive pads 312 and the second pins 332 are electrically connected one-to-one through the second conductive adhesive layer, and the redundant conductive pads 327 and the redundant pins 334 are disposed and connected one-to-one. In the at least two rows of the second conductive pads 312, the distance from a part of at least two rows of the second bonding face 312a of the second conductive pads 312 in the second conductive pads 312, parallel to the bearing surface, to the substrate 313 is increased from close to the display area 300a to far away from the display area 300a, so as to adapt to an increase in the elevated degree of the second pins 332 from being close to the display area 300a to far away from the display area 300a when the driving chip 33 is attached to the array substrate.
Please refer to
As shown in
In this embodiment, in the direction of the display area 300a pointing toward the pad area 300b, the thickness of the first conductive adhesive layer 401 increases, and the thickness of the second conductive adhesive layer 402 increases.
In this embodiment, the thickness of the first pins is different from the thickness of the second pins, so as to compensate the distance between an elevated one from the first pins and the second pins and the substrate to ensure that the elevated one from the first pins and the second pins can be bound on the array substrate and electrically connected with the corresponding conductive pads.
It should be noted that a control of a thickness difference of the pins on the driving chip in this embodiment and a control of a height difference of the bonding surface of the conductive pads on the array substrate in
The present disclosure also provides a display device. The display device includes any one of the above-mentioned display panels and a backlight module, and the display panel is located on a light-emitting side of the backlight module.
The foregoing embodiments are merely some embodiments of the present disclosure, and descriptions thereof are relatively specific and detailed. However, it should not be understood as a limitation to the patent scope of the present disclosure. It should be noted that a person of ordinary skill in the art may further make some variations and improvements without departing from the concept of the present disclosure, and the variations and improvements belong to the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202111164181.8 | Sep 2021 | CN | national |
This application is a continuation application of U.S. patent application Ser. No. 17/613,509, filed on Nov. 23, 2021, which is a US national phase application based upon an International Application No. PCT/CN2021/123357, filed on Oct. 12, 2021, which claims priority to Chinese Patent Application No. 202111164181.8, filed on Sep. 30, 2021. The disclosures of the aforementioned applications are incorporated herein by reference in their entireties.
| Number | Date | Country | |
|---|---|---|---|
| Parent | 17613509 | Nov 2021 | US |
| Child | 19071763 | US |
