Patent Application
20090017587
The present disclosure relates generally to semiconductor devices, and more particularly to methods for making CMOS devices with disposable spacers.
As MOSFETs are scaled down to channel lengths below 100 nm, interactions between the source and drain regions of the MOSFET begin to degrade the ability of the gate to switch the transistor on and off. This phenomenon, known in the art as the short channel effect, represents a significant challenge to CMOS scaling.
One approach which has been developed in the art for mitigating the short channel effect utilizes a double implant process to define the source and drain regions of the transistor. In this approach (which is typically implemented after the gate structure is defined on a semiconductor substrate), a dopant is implanted into a thin region just below the top surface of the substrate to form ultra-shallow source/drain extension regions. This implant step also forms a portion of the source/drain regions.
After the extension regions are defined, spacers are formed on the substrate such that they are adjacent to the sides of the gate structure and extend over the source and drain extension regions. Such spacers may be formed by depositing a conformal layer of silicon nitride or silicon oxide, and then subjecting the conformal layer to an anisotropic etch. The substrate is then subjected to a second implant to deepen the source and drain regions. The source and drain extensions are shielded from further doping during this process due to the presence of the spacers. The structure may then be subjected to a thermal anneal to induce dopant diffusion.
In one aspect, a method for making a semiconductor device is provided, comprising (a) providing a semiconductor structure comprising a first gate electrode; (b) forming a first set of organic spacers adjacent to said first electrode; (c) depositing a first photo mask over the structure; and simultaneously removing the first set of organic spacers and the first photo mask.
In another aspect, a method for making a semiconductor device is provided, comprising (a) providing a structure comprising first and second gate electrodes disposed on a semiconductor substrate; (b) depositing a first layer comprising a first organic material, the first layer having a first average thickness; (c) etching the first layer with a first etch to define a first set of spacer structures adjacent to the first electrode; (d) depositing a second layer comprising a second organic material, the second layer having a second average thickness which is different from the first average thickness; and (e) etching the second layer with a second etch to define a second set of spacer structures adjacent to the second electrode.
In a further aspect, a method for making a semiconductor device is provided which comprises (a) providing a semiconductor structure having a gate electrode disposed on a semiconductor substrate; (b) forming a set of organic spacers adjacent to the gate electrode; and (c) subjecting the structure to silicidation.
In still another aspect, a method for making a CMOS device is provided which comprises (a) providing a semiconductor structure having first and second gate electrodes disposed in first and second regions thereof, respectively; (b) forming a first set of organic spacers adjacent to each of said first and second electrodes by depositing a first layer comprising a first organic material having a first average thickness, and etching the first layer with a first etch; (c) depositing a first photo mask over the structure such that at least a portion of the first region is exposed, and at least a portion of the second region is covered; (d) subjecting the first region to an implantation process; (e) removing the first set of organic spacers; (f) forming a second set of organic spacers adjacent to each of said first and second electrodes by depositing a second layer comprising a second organic material having a second average thickness, and etching the second layer with a second etch; (g) depositing a second photo mask over the structure such that at least a portion of the second region is exposed and at least a portion of the first region is covered; (h) subjecting the second region to an implantation process; and (i) removing the second set of organic spacers.
Despite the advantages of the foregoing approach, the use of silicon oxide or silicon nitride spacers has some notable drawbacks. In particular, these spacers require the use of selective etch chemistries during their formation and removal, which places significant design constraints on the process flow. In addition, the removal of these spacers often results in silicon gouging, especially if the selectivity of the etch process used to remove the spacers is not sufficiently high.
Moreover, in many applications, it is desirable to remove spacers, and then possibly replace them, during a process of the type described above. Such applications may include, but are not limited to, ultra-shallow junction formation, processes utilizing customizable NMOS or PMOS extension offsets or customizable source/drain main spacer widths or shapes, and contact ESL (Etch Stop Layer) stressor enhancement. In such applications, the use of easily removable spacers would be desirable.
It has now been found that the foregoing needs may be addressed by utilizing organic spacers in conjunction with a photo masking scheme to process a semiconductor device, after which the spacers may be stripped with the same chemistry used to strip the photo resist. Preferably, removal of the spacers occurs simultaneously with removal of the photoresist. This approach may be implemented in a stepwise fashion to independently process different regions of a semiconductor device.
Such a process eliminates the extra processing steps typically required for spacer and photoresist removal, while leveraging the greater ease with which organic spacers may be removed from semiconductor substrates as compared to silicon oxide or silicon nitride spacers. Thus, such a process may avoid or minimize silicon gouging. It has also been found that organic spacers of the type described herein may be advantageously utilized during silicidation, where their ease of removal and less stringent process chemistry requirements minimize damage to the substrate and provide a more versatile process flow.
The methodologies described herein may be advantageously leveraged in the fabrication of CMOS devices. In particular, first and second sets of organic spacers may be utilized for implantation of the source and drain regions in the NMOS and PMOS regions of a CMOS device. Since these spacers are easier to remove than conventional spacers, and since the removal of these spacers causes less damage to the substrate (and may be effected in the same step used to remove the associated photo mask), the first and second sets of spacers may be defined in multiple (separate) processing steps. Consequently, the dimensions of the spacers may be chosen to optimize the NMOS and PMOS regions of the device. Such an approach would be less desirable using conventional spacers (which would also typically require separate removal of the spacers and photo masks), due to the increased likelihood of damage to the semiconductor structure attendant to the additional etches required to define and remove the spacers and associated photo masks.
The devices and methodologies described herein may be better appreciated by first considering the prior art process depicted in
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The layer of organic spacer material 211 may also comprise amorphous carbon. Such a material may be formed, for example, by chemical vapor deposition (CVD) (or more specifically plasma enhanced CVD (PECVD)) using a process gas which preferably comprises propylene (C3H6), and which may also comprise one or more hydrocarbons such as, for example, methane (CH4), acetylene (C2H2), ethylene (C2H4), ethane (C2H6), or propane (C3H8). The flow rate of the propylene in the process chamber may be set, for example, to between about 500 standard cubic centimeters per minute (sccm) and about 3000 sccm. An additional gas, such as helium, may be also introduced into the chamber at a suitable flow rate. The flow rate of helium into the process chamber may be set, for example, between about 250 sccm and about 1000 sccm. During the process of forming the amorphous carbon layer, the deposition chamber is typically subjected to a suitable radio frequency (RF) power and is maintained at an appropriate pressure. In some embodiments, the radio frequency power is set between about 450 Watts and about 1000 Watts, and the pressure is set between about 4 Torr and about 6.5 Torr.
The layer of organic spacer material 211 may be deposited to various thicknesses, and the preferred thickness may depend, in part, on the particular application. Preferably, however, the layer of organic spacer material 211 is deposited to a thickness within the range of about 200 Å to about 1000 Å, more preferably to a thickness within the range of about 400 Å to about 800 Å, even more preferably to a thickness within the range of about 500 Å to about 700 Å, and most preferably to a thickness of about 600 Å. Optionally, a conventional dielectric (such as SiO2) may be used as a liner underneath the spacer to act as an etch stop or to provide protection to the gate stack during subsequent processing.
Referring now to
As a specific example of the foregoing, if the organic spacer material 211 is amorphous carbon, it may be etched in a plasma reactor equipped with decoupled source and bias powers to produce a high-density plasma. The reactor may be provided with hydrogen bromide (HBr) at a flow rate of about 50 sccm to about 200 sccm, and nitrogen (N2) at a flow rate of about 20 sccm to about 80 sccm. Power is then applied to the inductively coupled antenna of the reactor at between 500 to 1200 W with a cathode bias power of between 50 to 200 W, and the wafer temperature may be maintained within the range of about 10 to about 60° C. at a pressure in the process chamber of between 1 to 30 mTorr. The nitrogen (N2) may optionally be supplemented or replaced with oxygen (O2), argon (Ar), carbon monoxide (CO), or the like such that the gas chemistry may comprise, for example, HBr/N2/O2/Ar, HBr/O2/Ar, or HBr/N2/CO/Ar.
The advantage of using amorphous carbon as the spacer material is that these various chemistries used to etch it are capable of producing very minimal damage, or gouging, to the underlying substrate. Additionally, the ratio of process gases may be adjusted so as to modulate the shape and width of the organic spacer. This is possible because the properties of the amorphous carbon compared to traditional SiO2 or Si3N4 spacer material allow for more adjustment of isotropic versus anisotropic etch rates.
As shown in
The exposed region is then subjected to implantation to define source/drain regions 214 adjacent to the gate electrode 210. The layer of photoresist 215 is then stripped, and the organic spacers 213 are removed by oxygen ashing as shown in
A wide variety of spacer materials and photoresists (both positive and negative) may be utilized which permit the simultaneous removal of the photoresist (and more specifically, the cured or uncured portion thereof used to mask the substrate) and the spacers 213. For example, if the spacers 213 comprise amorphous carbon and the photoresist 215 comprises a polyhydroxystyrene-based polymer or a mixture of diazonaphthoquinone (DNQ) and a phenol formaldehyde resin, then oxygen ashing may be utilized to simultaneously remove both the spacers 213 and the photoresist 215.
Referring now to
The second layer of organic spacer material 217 may be deposited to various thicknesses, and the preferred thickness may depend, in part, on the particular application. Preferably, however, the second layer of organic spacer material 217 is deposited to a thickness within the range of about 600 Å to about 1400 Å, more preferably to a thickness within the range of about 800 Å to about 1200 Å, even more preferably to a thickness within the range of about 900 Å to about 1100 Å, and most preferably to a thickness of about 1000 Å.
The second layer of organic spacer material 217 is then etched back as described above to produce spacers 219 adjacent to the gate electrodes 210, 212 as shown in
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The process depicted in
By contrast, disposable spacers of the type described herein may be formed through low temperature deposition processes which avoid dopant diffusion. Typically, these materials may be deposited at temperatures of less than about 400° C. The organic spacers described herein assume standard sidewall spacer shapes, and may be readily removed, for example, through a comparatively gentle oxygen ashing process which avoids silicon gouging and which does not harm other parts of the device. Because of these properties, the sequence of organic spacer deposition, etch and strip can be done as many times as needed to fully customize the process flow. Moreover, the organic spacers described herein may be utilized with photoresist masking to selectively process a substrate in multiple process cycles, and both the organic spacers and the (developed) photoresist may be removed with the same chemistry.
The organic spacers described herein may be utilized in various additional embodiments in accordance with the teachings herein. For example, rather than utilizing organic spacers in each implant and silicidation step as described in
In other embodiments, a conventional process flow may be utilized up through gate formation. Thereafter, a first set of organic spacers may be formed followed by implantation of a P+ extension region, after which the first set of organic spacers may be stripped. A second set of organic spacers with the same or different thickness may be formed followed by implantation of an N+ extension region, after which the second set of organic spacers may be stripped. Conventional spacers may then be utilized to finish the source/drain implants. Of course, it will be appreciated that, in such embodiments, the N+ extension region may be formed before the P+ extension region, or vice versa.
In still other embodiments, a conventional process flow may be utilized through gate formation. First and second sets of spacers (which may be of first and second thicknesses, wherein the first and second thicknesses may be the same or different) may then be utilized during N+ and P+ source/drain implants, respectively. A high temperature source/drain anneal (which may, for example, be a spike anneal) may be utilized to induce dopant diffusion. Conventional spacers may then be utilized to finish the extension implants, followed by a lower Dt anneal. The low Dt anneal may be a laser anneal, a flash anneal, or the like, or may be used for solid phase epitaxial regrowth (SPER).
In still further embodiments, differential spacers may be achieved by using organic spacers of the type described herein in conjunction with an oxide hard mask. The oxide hard mask may comprise, for example, tetraethylorthosilicate (TEOS) or undoped oxide (UDOX). In such embodiments, a first set of organic spacers may be removed with a photoresist strip, while a second set of spacers is protected by the oxide hard mask and remains. The first and second sets of spacers may be disposed, for example, in the NMOS and PMOS regions of a CMOS device.
The above description of the present invention is illustrative, and is not intended to be limiting. It will thus be appreciated that various additions, substitutions and modifications may be made to the above described embodiments without departing from the scope of the present invention. Accordingly, the scope of the present invention should be construed in reference to the appended claims.
