Claims
- 1. A method of forming dual damascene openings in the fabrication of an integrated circuit device comprising:providing metal lines covered by an insulating layer overlying a semiconductor substrate; depositing an organic dielectric layer overlying said insulating layer; depositing an inorganic dielectric layer overlying said organic dielectric layer wherein no etch stop layer is formed between said organic dielectric layer and said inorganic dielectric layer; etching a via pattern into said inorganic dielectric layer; etching said via pattern into said organic dielectric layer using patterned said inorganic dielectric layer as a mask; and thereafter etching a trench pattern into said inorganic dielectric layer wherein said organic dielectric layer acts as an etch stop to complete said forming of said dual damascene openings in the fabrication of said integrated circuit device.
- 2. The method according to claim 1 further comprising forming semiconductor device structures including gate electrodes and source and drain regions in and on said semiconductor substrate wherein said metal lines overlie and contact said semiconductor device structures.
- 3. The method according to claim 1 wherein said organic dielectric layer comprises polyimides, hydrido organo polymer, polyphenylene polymers, poly(arylene) ethers, benzocyclobutene, methylsilsesquioxane, or organic polymers.
- 4. The method according to claim 1 wherein said inorganic dielectric layer comprises carbon-doped oxides, silicon oxide-based low-k films, flourinated silicate glass, carbon-doped flourinated silicate glass, nitrogen-doped flourinated silicate glass, trimethylsilane flourinated silicate glass, hydrogen silsesquioxane based materials flourinated silicate glass, or hydrogen silsesquioxane.
- 5. The method according to claim 1 further comprising filling said dual damascene openings with a metal layer.
- 6. A method of forming dual damascene openings in the fabrication of an integrated circuit device comprising:providing metal lines covered by an insulating layer overlying a semiconductor substrate; depositing an organic dielectric layer overlying said insulating layer; depositing an inorganic dielectric layer overlying said organic dielectric layer wherein no etch stop layer is formed between said organic dielectric layer and said inorganic dielectric layer; etching a trench pattern into said inorganic dielectric layer; and thereafter etching a via pattern into said organic dielectric layer through said trench pattern to complete said forming of said dual damascene openings in the fabrication of said integrated circuit device.
- 7. The method according to claim 6 further comprising forming semiconductor device structures including gate electrodes and source and drain regions in and on said semiconductor substrate wherein said metal lines overlie and contact said semiconductor device structures.
- 8. The method according to claim 6 wherein said organic dielectric layer comprises polyimides, hydrido siloxane organo polymer, polyphenylene polymers poly(arylene) ethers, benzocyclobutene, methylsilsesquioxane, or organic polymers.
- 9. The method according to claim 6 wherein said inorganic dielectric layer comprises carbon-doped oxides, silicon oxide-based low-k films, flourinated silicate glass, carbon-doped flourinated silicate glass, nitrogen-doped flourinated silicate glass, trimethylsilane flourinated silicate glass, hydrogen silsesquioxane based materials flourinated silicate glass, or hydrogen silsesquioxane.
- 10. The method according to claim 6 further comprising filling said dual damascene openings with a metal layer.
RELATED PATENT APPLICATION
U.S. patent application Ser. No. 09726657 (CS-00-024) to Q. S. Fong et al., filed Nov. 30, 2000, now U.S. Pat. No. 6,406,994.
US Referenced Citations (18)
Foreign Referenced Citations (1)
Number |
Date |
Country |
10-112503 |
Oct 1996 |
JP |
Non-Patent Literature Citations (2)
Entry |
Toshiaki, Manufacture of Semiconductor Device, Oct. 3, 1996, Computer translation of JP 10-112503, 6 pages.* |
Chang et al., ULSI Technology, The McGraw Hill Companies, Inc., NY, NY, c.1996, pp. 444-445. |