With each successive semiconductor technology generation, wafer diameters tend to increase and transistor sizes decrease, resulting in the need for an ever higher degree of accuracy and repeatability in wafer processing. Semiconductor substrate materials, such as silicon wafers, are processed by techniques which include the use of vacuum chambers. These techniques include non-plasma applications such as electron beam evaporation, as well as plasma applications, such as sputter deposition, plasma-enhanced chemical vapor deposition (PECVD), resist strip, and plasma etch.
Exemplary plasma processing chambers are described in commonly owned U.S. Pat. Nos. 4,340,462, 4,948,458, 5,200,232, 6,090,304 and 5,820,723, which are hereby incorporated by reference. A plasma processing chamber can comprise an upper electrode assembly and a lower electrode assembly. Details of exemplary upper electrode assemblies are disclosed in U.S. Pat. Nos. 6,333,272, 6,230,651, 6,013,155 and 5,824,605, which are hereby incorporated by reference. Directly below the upper electrode assembly, is the lower electrode assembly which can comprise an electrostatic chuck (ESC) on which the substrate being processed is supported. Exemplary ESCs are described in commonly owned U.S. Pat. Nos. 7,161,121, 6,669,783 and 6,483,690, which are incorporated by reference. The ESC can have micro channels on its upper surface in fluidic communication with a helium gas source. Helium gas can be used to cool the substrate during processing. A method of controlling a temperature of a substrate by a pressurized gas is disclosed in commonly-owned U.S. Pat. No. 6,140,612, which is hereby incorporated by reference. The lower electrode assembly can further comprise an edge ring fitted around the substrate. Exemplary edge rings are described in commonly owned U.S. Patent Application Publication No. 2009/0186487 and U.S. Pat. Nos. 5,805,408, 5,998,932, 6,013,984, 6,039,836 and 6,383,931, which are incorporated by reference.
In a typical plasma processing chamber, plasma density is lower near the edge of the substrate, which can lead to accumulation of a byproduct layer (such as polymer, poly-silicon, nitride, metal, etc.) on the top and bottom surfaces of the substrate edge and surfaces of chamber components nearby. Excessive byproduct accumulation can lead to many problems in plasma processing such as particle contamination, unreliable substrate clamping, cooling He gas leakage, reduced efficiency and reduced device yield. Therefore, it is highly desirable to remove the byproduct. The byproduct layer on the substrate edge can be removed by using a plasma bevel etcher. An exemplary plasma bevel etcher is described in commonly owned U.S. Patent Application Publication No. 2008/0227301, which is hereby incorporated by reference. The byproduct layer on chamber components is more difficult to remove, partially due to their complicated shapes. A typical plasma processing chamber can run a chamber clean process, in which a plasma is used to etch the byproduct layer from chamber components without presence of the substrate.
Described herein is a substrate support for supporting a substrate in a plasma processing chamber which comprises an upper substrate support surface dimensioned to support the substrate during plasma processing such that the substrate extends outward of an outer periphery of the upper substrate support surface, and an angled sidewall extending outward and downward from the outer periphery of the upper substrate support surface, the angled sidewall configured to have an outer periphery substantially coplanar with an upper surface of an edge ring surrounding the substrate support, the upper surface of the edge ring at least partially under a peripheral portion of the substrate, wherein the angled sidewall accumulates byproduct deposition during plasma processing.
During processing, a byproduct deposit 100 can accumulate on a portion of the vertical sidewall 22 exposed in the gap 60. Excessive byproduct on the vertical sidewall 22 can cause He leakage from the pattern of grooves, mesas, openings or recessed regions 23 and affect electrostatic clamping of the substrate 10. The byproduct deposit 100 can be minimized by having a large substrate overhang and precise control on the size of the gap 60. However, in current semiconductor fabrication practice, a width of the substrate overhang can be as little as 1 mm in order to maximize device yield from the substrate. A substrate overhang with a small width such as 1 mm can lead to byproduct accumulation on the vertical sidewall 22 at a faster rate than desired.
As shown in
Described herein is an ESC with an angled sidewall, configured to enhance the sputter efficiency during the chamber clean process.
An embodiment is shown in
Because the ESC 520 is configured such that only the angled surface 522 is exposed during plasma processing of a substrate, byproduct deposit 400 occurs only on the angled surface 522. In the chamber clean process as shown in
While the ESC with angled sidewall has been described in detail with reference to specific embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications can be made, and equivalents employed, without departing from the scope of the appended claims. For example, the angled sidewall can be incorporated in other chamber components that suffer from byproduct deposition, such as other types of substrate support (e.g. vacuum chucks), edge rings, coupling rings and the like.
This application claims priority under 35 U.S.C. §119 to U.S. Provisional Application No. 61/265,200 entitled AN ELECTROSTATIC CHUCK WITH AN ANGLED SIDEWALL, filed Nov. 30, 2009, the entire content of which is hereby incorporated by reference.
Number | Date | Country | |
---|---|---|---|
61265200 | Nov 2009 | US |