Embodiments of the present disclosure relate to electronic systems, and more particularly to electronic packages with embedded interconnect bridges that include integrated inductors for power delivery applications.
Passive electrical components (e.g., capacitors and inductors) are important components of substrate packaging that enable efficient power delivery to voltage regulators located on the overlying dies. Logic-side power delivery currently requires passive components attached to the land/die side of the substrate surface (e.g., multi-layer ceramic capacitors, magnetic inductor arrays, etc.) or embedded within the substrate core. These passive components help to maintain constant voltage and reduce noise and impedance to voltage regulator rails.
Land/die side capacitors and inductors have significant performance limitations due to the routing losses that accumulate over the long-distance power-delivery signals must travel between the components and the die-side voltage regulator rails. Embedding these passive components into the substrate core to lower the routing length is one possible solution path. However, current processes are primarily limited to ultra-thin-core products due to significant processing difficulties with thicker core products. Coaxial inductor solutions embedded in the core is another solution path, but is limited due to a tradeoff between inductor performance and manufacturability. Thus, limiting their effective performance envelope.
Described herein are electronic systems, and more particularly, electronic packages with embedded interconnect bridges that include integrated inductors for power delivery applications, in accordance with various embodiments. In the following description, various aspects of the illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. However, it will be apparent to those skilled in the art that the present invention may be practiced with only some of the described aspects. For purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the illustrative implementations. However, it will be apparent to one skilled in the art that the present invention may be practiced without the specific details. In other instances, well-known features are omitted or simplified in order not to obscure the illustrative implementations.
Various operations will be described as multiple discrete operations, in turn, in a manner that is most helpful in understanding the present invention, however, the order of description should not be construed to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation.
As noted above, existing architectures for the integration of passive components are limited. For example, discrete passive components lead to high routing losses due to their distance from the voltage regulator. Integrated passives, such as coaxial inductor structures embedded in the core, are also limited in design due to material and manufacturability concerns.
Accordingly, embodiments disclosed herein provide integrated passive devices (e.g., inductors and capacitors) directly on the embedded bridge. Having power delivery components within the embedded bridge offers an optimized routing distance to the die-side voltage regulator (VR) rails. Further, high capacitance density and inductance density can be achieved using silicon processing technologies compatible with the bridge die. Additionally, utilizing existing embedding process flows for embedded bridge architectures will make the package substrate processing relatively straight forward since integrated passives may be omitted from the package substrate. Integration of passives into the embedded bridge also utilizes existing silicon real estate within the bridge body that currently has no functional purpose.
More particularly, embedded bridge architectures disclosed herein include an inductor layer. The inductor layer may be provided over the bridge die or under the bridge die. The inductor layer comprises conductive traces that are formed in an inductive pattern (e.g., coil pattern or serpentine pattern). Vias to the conductive traces may then be formed to the front side or backside of the bridge. The inductor layer may include a magnetic material over the inductive pattern in order to further increase the inductance of the inductor layer. In some embodiments, two or more inductor layers may be provided over each other as well. While inductor architectures are described in detail herein, it is to be appreciated that integrated capacitor structures may be used in conjunction with the integrated inductor architectures.
Referring now to
In an embodiment, the bridge 150 may comprise a substrate 101. The substrate 101 may be a silicon substrate. Though, the substrate 101 may be other materials, such as glass or the like. In some embodiments, the substrate 101 may be a dummy substrate. That is, there may not be any active circuitry (e.g., transistors, etc.) on the substrate 101. The substrate 101 may serve as a dimensionally stable base onto which interconnects and passives are formed.
In an embodiment, an inductor layer may be provided over a top surface of the substrate 101. The inductor layer may comprise electrically conductive traces 112. The traces 112 may terminate at pads 114. In an embodiment, the traces 112 may have a pattern suitable for providing high inductances. For example, the traces 112 may be coils or a serpentine pattern. In an embodiment, the inductor layer may further comprise a magnetic material 110 over the traces 112. The magnetic material 110 may be any suitable magnetic material that is compatible with bridge 150 fabrication. For example, the magnetic material 110 may comprise cobalt and iron, any other ferrite material, any high permeability material, or the like.
In an embodiment, routing layers 120 may be provided above the inductor layer. The routing layers 120 may include electrically conductive traces 127 that couple together pads 125. The traces 127 may be provided in one or more routing layers 120. The traces 127 may be high density traces. For example, a line/spacing (L/S) dimension of the traces 127 may be approximately 5 μm/5 μm or less, or approximately 2 μm/2 μm or less. As used herein, “approximately” may refer to a range of values that are within ten percent of the stated value. For example, approximately 5 μm may refer to a range between 4.5 μm and 5.5 μm.
In an embodiment, the inductor layer may be coupled to the top surface of the bridge 150 by vias 115. The vias 115 may pass through the routing layers 120 and the magnetic material 110 in order to contact pads 114 in the inductor layer. Pads 117 may be provided over the vias 115 on the top side of the bridge 150. The pads 117 may be positioned so that they are proximate to VR devices in the overlying dies (not shown). As such, the distance between the inductor and the VR is minimized.
Referring now to
Referring now to
Referring now to
Referring now to
In an embodiment, the inductor layer may include a dual layer inductor. For example, a first layer including first traces 212A may be provided over a second layer including second traces 212B. A pad 214A in the first layer may be electrically coupled to a pad 214B in the second layer by a via 211. The first traces 212A may form a first inductor, and the second traces 212B may form a second inductor. In an embodiment, the first inductor is connected to the second inductor in series. An input and an output to the connected inductors may be provided through vias 215 and pads 217.
In an embodiment, a magnetic material 210 is provided over and around the first traces 212A and the second traces 212B. The magnetic material 210 may be any suitable magnetic material, such as a ferrite, or any high permeability material. For example, the magnetic material 210 may comprise cobalt and iron in some embodiments. The magnetic material 210 may be applied as multiple layers. For example, a first layer of the magnetic material 210 may be applied around the second traces 212B, and a second layer of the magnetic material 210 may be applied around the first traces 212A. As such, there may be a seam within the magnetic material 210 in some embodiments.
Referring now to
Referring now to
In an embodiment, an inductor layer is provided on a backside of the substrate 301. That is, the inductor layer is provided on a surface of the substrate 301 opposite from the routing layers 320. The inductor layer may include traces 312. The traces may include any suitable pattern for generating inductance. For example, the traces 312 may have a coil pattern, a serpentine pattern, or the like. In an embodiment, the traces 312 may be surrounded by a magnetic material 310. The magnetic material 310 may be a ferrite, such as a material comprising cobalt and iron, or any high permeability material. In an embodiment an insulating layer 313 may be provided over the magnetic material 310.
Ends of the traces 312 may terminate at pads 314. In an embodiment, the pads 314 may be coupled to pads 317 on the front side of the bridge 350 by vias 315. More particularly, the vias 315 may pass through the substrate 301 and the routing layers 320. The portion of the via 315 that passes through the substrate 301 may be considered a through silicon via (TSV) in some embodiments.
Referring now to
In an embodiment, an inductor layer is provided on a backside of the substrate 301. That is, the inductor layer is provided on a surface of the substrate 301 opposite from the routing layers 320. The inductor layer may include traces 312. The traces may include any suitable pattern for generating inductance. For example, the traces 312 may have a coil pattern, a serpentine pattern, or the like. In an embodiment, the traces 312 may be surrounded by a magnetic material 310. The magnetic material 310 may be a ferrite, such as a material comprising cobalt and iron, or any high permeability material. In an embodiment an insulating layer 313 may be provided over the magnetic material 310.
Ends of the traces 312 may terminate at pads 314. In an embodiment, the pads 314 may be coupled to pads 319 on the backside of the bridge 350 by vias 315. More particularly, the vias 315 may pass through the magnetic material 310 and the insulating layer 313. As such, embodiments may include bridge 350 architectures with pads on both the top and bottom of the bridge 350. That is, pads 325 for die-to-die connections may be provided on the top surface of the bridge 350, and pads 319 for power delivery passives may be provided on the bottom surface of the bridge 350.
Referring now to
In an embodiment, routing layers 420 are provided over the top surface of the magnetic material 410. The routing layers 420 may comprise electrically conductive traces 427 that are used to communicatively couple multiple dies together. The conductive traces 427 may be provided in one or more of the routing layers 420. Additionally, the traces 427 may be coupled to pads 425 at the top surface of the bridge 450.
In an embodiment, the pads 414 in the inductor layer may be coupled to pads 417 on a top surface of the bridge 450 by vias 415. The vias 415 may pass through the magnetic material 410 and the routing layers 420. In an embodiment, the vias 415 may be provided along edges of the bridge 450.
Referring now to
Referring now to
Referring now to
Referring now to
Referring now to
Referring now to
Referring now to
Referring now to
Referring now to
In
Referring now to
In an embodiment, the bridge 750 may be similar to any of the bridge architectures described herein. For example, the bridge 750 may comprise a substrate 701, such as a silicon substrate or the like. A magnetic layer 710 may be provided over the substrate 701. Inductor traces 712 may be embedded within the magnetic layer 710. The inductor traces 712 may be coupled to pads 717 on the top of the bridge 750 by pads 714 and vias 715. The top pads 717 may be coupled to VR regions 766 of the dies 765.
Referring now to
Referring now to
In an embodiment two or more dies 865 may be provided over the package substrate 861. The dies 865 may be compute dies. For example, the dies 865 may include a central processing unit (CPU), a graphics processing unit (GPU), an XPU, a system on a chip (SoC), a communications die, a memory die, or the like. In an embodiment, the dies 865 may be communicatively coupled together by a bridge 850 that is embedded in the package substrate 861.
In an embodiment, the bridge 850 may be similar to any of the bridge architectures described herein. In a particular embodiment, the bridge 850 comprises a substrate 801, such as a silicon substrate. In an embodiment, a magnetic layer 810 embeds inductor traces 812. Routing layers 820 may be provided above the magnetic layer 810. In an embodiment, the inductor traces 812 are coupled to VR regions in the overlying dies 865.
Referring now to
These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).
The communication chip 906 enables wireless communications for the transfer of data to and from the computing device 900. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 906 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device 900 may include a plurality of communication chips 906. For instance, a first communication chip 906 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 906 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.
The processor 904 of the computing device 900 includes an integrated circuit die packaged within the processor 904. In some implementations of the invention, the integrated circuit die of the processor may be part of an electronic package with an embedded bridge that includes an integrated inductor, in accordance with embodiments described herein. The term “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
The communication chip 906 also includes an integrated circuit die packaged within the communication chip 906. In accordance with another implementation of the invention, the integrated circuit die of the communication chip may be part of an electronic package with an embedded bridge that includes an integrated inductor, in accordance with embodiments described herein.
In an embodiment, the computing device 900 may be part of any apparatus. For example, the computing device may be part of a personal computer, a server, a mobile device, a tablet, an automobile, or the like. That is, the computing device 900 is not limited to being used for any particular type of system, and the computing device 900 may be included in any apparatus that may benefit from computing functionality.
The above description of illustrated implementations of the invention, including what is described in the Abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific implementations of, and examples for, the invention are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize.
These modifications may be made to the invention in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific implementations disclosed in the specification and the claims. Rather, the scope of the invention is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.
Example 1: an interconnect bridge, comprising: a substrate; a first trace on the substrate; a first layer on the first trace, wherein the first layer comprises a magnetic material; a second layer over the substrate, wherein the second layer comprises an insulating material; and a second trace embedded in the second layer.
Example 2: the interconnect bridge of Example 1, wherein the substrate comprises silicon or glass.
Example 3: the interconnect bridge of Example 1 or Example 2, wherein the
first trace is a spiral trace.
Example 4: the interconnect bridge of Example 1 or Example 2, wherein the first trace is a serpentine trace.
Example 5: the interconnect bridge of Examples 1-4, wherein the first trace is an inductor trace.
Example 6: the interconnect bridge of Examples 1-5, wherein the first layer is between the second layer and the substrate.
Example 7: the interconnect bridge of Examples 1-5, wherein the substrate is between the first layer and the second layer.
Example 8: the interconnect bridge of Examples 1-7, further comprising: a third trace over the first trace, wherein the first layer is on the third trace.
Example 9: the interconnect bridge of Example 8, wherein a shape of the first trace and a shape of the third trace are chiral images of each other.
Example 10: the interconnect bridge of Examples 1-8, further comprising: a trench inductor into a cavity into the substrate.
Example 11: an electronic package, comprising: a package substrate; a bridge on the package substrate, wherein the bridge comprises: first traces; and a second trace, wherein the second trace is surrounded on at least three sides by a magnetic layer; a first die coupled to the package substrate; and a second die coupled to the package substrate, wherein the first traces communicatively couple the first die to the second die.
Example 12: the electronic package of Example 11, wherein the second trace is below the first traces.
Example 13: the electronic package of Examples 11-12, wherein the second trace comprises a spiral pattern or a serpentine pattern.
Example 14: the electronic package of Examples 11-13, further comprising: a third trace over the second trace.
Example 15: the electronic package of Example 14, wherein the third inductor trace is chiral with respect to the second trace.
Example 16: the electronic package of Examples 11-15, wherein the first die comprises a first voltage regulator and the second die comprises a second voltage regulator, and wherein the first voltage regulator and the second voltage regulator are coupled to the second trace.
Example 17: the electronic package of Example 11, wherein the bridge is embedded in the package substrate.
Example 18: an electronic system, comprising: a board; a package substrate coupled to the board; a bridge on the package substrate, wherein the bridge comprises: an inductor embedded in a magnetic layer; a first die coupled to the package substrate; and a second die coupled to the package substrate, wherein the first die is communicatively coupled to the second die by the bridge.
Example 19: the electronic system of Example 18, wherein the inductor comprises a spiral trace or a serpentine trace.
Example 20: the electronic system of Example 18 or Example 19, wherein the electronic system is part of a personal computer, a server, a mobile device, a tablet, or an automobile.