Patent Application
20080260044
The present invention relates to the field of video reception.
Historically, tuner demodulators (“tuner cans”) for video band applications have been implemented entirely in the analog domain, using up to several hundred discrete components and consuming as much as two to three watts of power. Unfortunately, despite their low cost and robust performance, tuner cans are generally limited to single-channel selection and thus are typically replicated in applications that require simultaneous receipt of more than one video channel, thus multiplying the number of required components, and therefore the power and space consumed, by the number of channels to be simultaneously received.
The present invention is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which:
In the following description and in the accompanying drawings, specific terminology and drawing symbols are set forth to provide a thorough understanding of the present invention. In some instances, the terminology and symbols may imply specific details that are not required to practice the invention. For example, the interconnection between circuit elements or circuit blocks may be shown or described as multi-conductor or single conductor signal lines. Each of the multi-conductor signal lines may alternatively be single-conductor signal lines, and each of the single-conductor signal lines may alternatively be multi-conductor signal lines. Signals and signaling paths shown or described as being single-ended may also be differential, and vice-versa. A signal driving circuit is said to “output” a signal to a signal receiving circuit when the signal driving circuit asserts (or deasserts, if explicitly stated or indicated by context) the signal on a signal line coupled between the signal driving and signal receiving circuits. The term “coupled” is used herein to express a direct connection as well as connections through one or more intermediary circuits or structures. The term “exemplary” is used herein to express an example, not a preference or requirement.
Video receiver architectures that may be implemented in a single integrated circuit (i.e., single chip) and that employ digital signal processing techniques to simultaneously demodulate multiple video channels are disclosed herein in various embodiments. In one multichannel receiver embodiment, for example, an integrated tuner and demodulator employ digital signal processing specifically targeted at mitigating the performance requirements in the analog domain while maintaining overall tuner performance, thereby providing the equivalent performance of N parallel tuner cans where die area and power consumption scale only weakly with N.
A signal received via signal input 101 (e.g., an antenna or jack for receiving a cable or other electrically or optically conductive medium) is amplified by the low-noise amplifier 103 to provide an input video signal that may be digitized and processed in downstream circuit blocks. In one embodiment, the low-noise amplifier 103 is designed to amplify signals falling within a video frequency band (e.g., 50-850 MHz), although virtually any frequency band may be encompassed within the range of the amplifier in alternative embodiments (e.g., a cable spectrum from 50 MHz-1 GHz, or any other spectrum). At the output of the amplifier 103, a pilot tone (which may be out-of-band with respect to the amplified frequency band or potentially in-band) is injected into the amplified signal. The amplified received signal (i.e., output of amplifier 103), along with the pilot, is converted into the digital domain by the ADC bank 105. In the embodiment shown, the ADC bank 105 includes a set of K M-bit resolution ADCs (ADC1-ADCK), triggered by a time-staggered set of sampling clock signals 120 (i.e., a multi-phase clock signal) to provide an effective sampling rate of K times the sampling clock frequency. In a particular embodiment, for example, the ADC bank 105 includes eight 10-bit ADCs each triggered by a respective time-staggered 250 MHz sampling clock signal to provide an effective sampling rate of 2 GHz. Background calibration may be used (e.g., a sinusoidal pilot tone or a pseudo-noise sequence) to ensure matching between the constituent ADCs within ADC bank 105 as well as correct relative time-staggering (time-phasing) between them.
The output of the ADC bank 105 is supplied to the FFT engine 107 which, for example, executes an overlap/add-type FFT operation to generate the equivalent frequency domain representation of the received signal and pilot tone. Assuming, for example, that the received signal includes all of the video channels between the upper and lower bounds of the desired frequency band (e.g., all of the 6 MHz video channels between 50 MHz and 850 MHz), the information in each “bin” of the FFT (i.e., the information-bearing signal present at each spectral offset) may be viewed as a representation of the data of each video channel itself. Also, because both the FFT and video channels themselves are separated in frequency (i.e., by the orthogonality property of the FFT), the effective dynamic range of the ADC bank 105 with respect to each individual video channel is generally far greater than the M-bit resolution of the ADC output. Continuing with the 250 MHz sampling clock, 8-ADC example above, for instance, each video channel within the video band of interest is effectively sampled at 2 GHz, which in the case of a standard 6 MHz video channel yields a tremendous oversampling ratio. The FFT is the averaging by which the oversampling gain is realized and hence increases the signal-to-noise ratio (SNR) for each individual channel.
With respect to pilot tone calibration of the ADC bank 105, in one embodiment a single sinusoidal pilot 118 having a frequency outside the desired video band (e.g., 1 GHz or above) is injected into the amplified received signal (i.e., at the input of the ADC bank). Because the pilot tone 118 has a constant frequency and amplitude, the FFT engine 107 will generate a constant output at the frequency of the pilot tone. That is, the data in the “bin” of the pilot tone should remain substantially unchanged over time. Accordingly, any modulation or error of the pilot tone's bin, detected in pilot extraction circuit 121, indicates an imperfection in the sampling operation itself, either due to phase noise or an error in the relative timing between the individual ADCs that constitute the ADC bank 105. Thus, by measuring the pilot in the FFT generated by the FFT engine 107, pilot extraction circuit 121 may adjust the frequency of the VCO and/or the phasing of ADCs within the ADC bank 105 to achieve improved performance, thereby mitigating phase noise in the sampling clock signals 120 as well as compensating for operational variation (e.g., due to process, temperature, voltage, etc.) within the constituent ADCs themselves.
Final frequency adjustment may also be carried out in the frequency domain. For example, by performing frequency-domain interpolation in interpolation frequency correction circuit 109, the effective demodulating carrier frequency may be adjusted to meet the tolerance required to demodulate video transmissions (e.g., 50 KHz in an NTSC standard video transmission). Further, the entire carrier-to-baseband operation may be carried out in the frequency domain so that demodulating operations conventionally carried out in analog mixer stages in time-domain systems may instead be performed using straightforward digital shifting operations in the (digital) frequency domain in the embodiment of
After frequency correction in circuit 109 and channel selection, video signals for a desired set of channel signal may be transformed back into the time domain via an inverse FFT (IDFT) operation carried out, for example, in constituent IDFT circuits of IDFT bank 111. The desired video signals, now at baseband, may be further processed in the time domain within respective baseband processing circuits of baseband processing bank 113 to extract the video information. Referring to the embodiment of a baseband processing circuit shown in
The final video output is a digital stream that may be fed into a video display and/or a MPEG (Moving Picture Experts Group) decoder. The digital stream may be compliant with any number of industry standards (e.g., CCIR/ITU 601/656 or SPI).
It should be noted that a programmed processor may be used to implement the functions or any subset thereof of the digital processing functions described above including, without limitation, the functions of an FFT engine, interpolated frequency correction circuit, IDFT circuit, DDS Frequency correction circuit, channel selection filter, subcarrier separation circuit, and any MPEG decoding therein. The processor may be formed on the integrated circuit with the video receiver or may be formed on a separate integrated circuit die in the same or different integrated circuit package. The processor may be virtually any type of processor including, without limitation, a general purpose processor or special purpose processor (e.g., a microcontroller (which may include an integrated ADC bank), digital signal processor (DSP) or the like) and may include an internal program store to store program code that is executed by the processor to perform the above-described functions. Alternatively, a separate on-chip or off-chip program store (e.g., a volatile or non-volatile memory, not shown or any other processor or computer-readable media including without limitation, semiconductor memory and magnetic and/or optical media) may be provided and coupled to the processor, for example, via a dedicated or shared bus. The program code stored within the program store may include instructions and/or data that, when executed by the processor, causes the processor to perform the above described functions.
It should also be noted that the various circuits disclosed herein may be described using computer aided design tools and expressed (or represented), as data and/or instructions embodied in various computer-readable media, in terms of their behavioral, register transfer, logic component, transistor, layout geometries, and/or other characteristics. Formats of files and other objects in which such circuit expressions may be implemented include, but are not limited to, formats supporting behavioral languages such as C, Verilog, and HLDL, formats supporting register level description languages like RTL, and formats supporting geometry description languages such as GDSII, GDSIII, GDSIV, CIF, MEBES and any other suitable formats and languages. Computer-readable media in which such formatted data and/or instructions may be embodied include, but are not limited to, non-volatile storage media in various forms (e.g., optical, magnetic or semiconductor storage media) and carrier waves that may be used to transfer such formatted data and/or instructions through wireless, optical, or wired signaling media or any combination thereof. Examples of transfers of such formatted data and/or instructions by carrier waves include, but are not limited to, transfers (uploads, downloads, e-mail, etc.) over the Internet and/or other computer networks via one or more data transfer protocols (e.g., HTTP, FTP, SMTP, etc.).
When received within a computer system via one or more computer-readable media, such data and/or instruction-based expressions of the above described circuits may be processed by a processing entity (e.g., one or more processors) within the computer system in conjunction with execution of one or more other computer programs including, without limitation, net-list generation programs, place and route programs and the like, to generate a representation or image of a physical manifestation of such circuits. Such representation or image may thereafter be used in device fabrication, for example, by enabling generation of one or more masks that are used to form various components of the circuits in a device fabrication process.
Various aspects of the subject-matter described herein are set out non-exhaustively in the following numbered clauses:
Although the invention has been described with reference to specific embodiments thereof, it will be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense. In the event that provisions of any document incorporated by reference herein are determined to contradict or otherwise be inconsistent with like or related provisions herein, the provisions herein shall control at least for purposes of construing the appended claims.
This application is a division of U.S. patent application Ser. No. 11/120,439 filed May 2, 2005 and entitled “FFT-Based Multichannel Video Receiver,” which claims priority from U.S. Provisional Application No. 60/567,333, filed Apr. 30, 2004 and entitled “FFT-Based Multichannel Tuner/Decoder Architecture,” both of which are hereby incorporated by reference in their entireties.
| Number | Date | Country | |
|---|---|---|---|
| 60567333 | Apr 2004 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 11120439 | May 2005 | US |
| Child | 12123845 | US |
