Patent Application
20240290617
The disclosure relates to semiconductor devices and integrated circuit manufacture and, more specifically, to structures for a field-effect transistor and methods of forming a structure for a field-effect transistor.
Wide bandgap semiconductors, such as silicon carbide, may be used in high-power applications and/or high-temperature applications. Silicon carbide is well suited for power switching because of advantageous properties, such as a high saturated drift velocity, a high critical field strength, an exceptional thermal conductivity, and a significant mechanical strength. A metal-oxide-semiconductor field-effect transistor is a type of gate-voltage-controlled power switching device that uses field inversion as a current control mechanism. A metal-oxide-semiconductor field-effect transistor may leverage the favorable properties of a silicon carbide substrate to enable, for example, power converters, motor inverters, and motor drivers that are characterized by high reliability and high efficiency when operating at a high voltage.
The metal-oxide-semiconductor field-effect transistor may include a gate structure having a gate dielectric layer that contains silicon dioxide formed by thermal oxidation process of the silicon carbide substrate. The silicon dioxide may incorporate carbon from the silicon carbide substrate during thermal oxidation, which results in a significant number of interface traps and degradation in the electrical properties of the gate dielectric layer. The interface traps may lower the carrier mobility in an inversion layer formed in the silicon carbide beneath the gate dielectric layer during operation of the metal-oxide-semiconductor field-effect transistor.
Improved structures for a field-effect transistor and methods of forming a structure for a field-effect transistor are needed.
In an embodiment of the invention, a structure for a field-effect transistor is provided. The structure comprises a semiconductor substrate comprising a wide bandgap semiconductor material, a gate electrode, a first gate dielectric layer disposed on the semiconductor substrate, and a second gate dielectric layer disposed between the first gate dielectric layer and the gate electrode.
In an embodiment of the invention, a method of forming a structure for a field-effect transistor is provided. The method comprises forming a first gate dielectric layer on a semiconductor substrate, forming a second gate dielectric layer on the first gate dielectric layer, and forming a gate electrode. The semiconductor substrate comprises a wide bandgap semiconductor material, and the second gate dielectric layer is disposed between the gate electrode and the first gate dielectric layer.
In an embodiment of the invention, a method of forming a structure for a field-effect transistor is provided. The method comprises cleaning a surface of a semiconductor substrate with atomic layer etching. The semiconductor substrate comprises a wide bandgap semiconductor material. The method further comprises forming a gate dielectric layer on the surface of the semiconductor substrate.
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate various embodiments of the invention and, together with a general description of the invention given above and the detailed description of the embodiments given below, serve to explain the embodiments of the invention. In the drawings, like reference numerals refer to like features in the various views.
With reference to
A doped region 16 may be formed in the semiconductor layer 14 adjacent to a top surface 13 of the semiconductor substrate 11. The doped region 16 is doped to have an opposite conductivity type from the semiconductor layer 14. The doped region 16 has a lower boundary that defines an interface with the underlying semiconductor material of the semiconductor layer 14 across which the dopant type changes. In an embodiment, the doped region 16 may define a body of the field-effect transistor.
The doped region 16 may be formed by introducing a dopant of a given conductivity type by, for example, ion implantation into the semiconductor layer 14. An implantation mask may be formed to define a selected area on a top surface 13 of the semiconductor substrate 11 that is exposed for the implantation of ions. The implantation mask may include a hardmask that is applied and patterned to form an opening exposing the selected area on the top surface 13 and determining, at least in part, the location and horizontal dimensions of the doped region 16. The implantation conditions (e.g., ion species, dose, kinetic energy, substrate temperature) may be selected to tune the electrical and physical characteristics of the doped region 16, to minimize defects, and to maximize the ionization and activation of the implanted dopants. In an embodiment, the ion implantation may be performed at substrate temperature in a range of 200° C. to 600° C. to minimize defect formation. The implantation mask, which is compatible with the implantation conditions and is stripped following implantation, has a thickness and stopping power sufficient to block the implantation of ions in masked areas. In an embodiment, the doped region 16 may be doped with a concentration of a p-type dopant (e.g., aluminum) to provide p-type electrical conductivity.
A doped region 19 may be formed in the doped region 16. The doped region 19 may provide a body contact to the body of the field-effect transistor defined by the doped region 16. The doped region 19 may be formed by introducing a dopant of a given conductivity type by, for example, ion implantation into the semiconductor layer 14. An implantation mask may be formed to define a selected area on a top surface 13 of the semiconductor substrate 11 that is exposed for the implantation of ions. The implantation mask may include a hardmask that is applied and patterned to form an opening exposing the selected area on the top surface 13 and determining, at least in part, the location and horizontal dimensions of the doped region 19. The implantation conditions (e.g., ion species, dose, kinetic energy, substrate temperature) may be selected to tune the electrical and physical characteristics of the doped region 19, to minimize defects, and to maximize the ionization and activation of the implanted dopants. In an embodiment, the ion implantation may be performed at substrate temperature in a range of 200° C. to 600° C. to minimize defect formation. The implantation mask, which is compatible with the implantation conditions and is stripped following implantation, has a thickness and stopping power sufficient to block the implantation of ions in masked areas. In an embodiment, the doped region 19 may be doped with a concentration of a p-type dopant (e.g., aluminum) to provide p-type electrical conductivity, and the dopant concentration of the doped region 19 may be greater than the dopant concentration of the doped region 16. In an alternative embodiment, additional regions similar to the doped region 19 may be disposed within the doped region 16.
A doped region 18 may be formed in the semiconductor layer 14 adjacent to a top surface 13 of the semiconductor substrate 11. The doped region 18 has the same conductivity type as the semiconductor layer 14 but at a higher dopant concentration. The doped region 18 has an upper boundary that may be coplanar or substantially coplanar with the top surface 13 of the semiconductor substrate 11 and a lower boundary that defines an interface with the doped region 16 across which the conductivity type changes. In an embodiment, the doped region 18 may define a source of the field-effect transistor.
The doped region 18 may be formed by introducing a dopant of a given conductivity type by, for example, ion implantation into the semiconductor layer 14. An implantation mask may be formed to define a selected area on a top surface 13 of the semiconductor substrate 11 that is exposed for the implantation of ions. The implantation mask may include a hardmask that is applied and patterned to form an opening exposing the selected area on the top surface 13 of the semiconductor substrate 11 and determining, at least in part, the location and horizontal dimensions of the doped region 18. The implantation conditions (e.g., ion species, dose, kinetic energy, substrate temperature) may be selected to tune the electrical and physical characteristics of the doped region 18. In an embodiment, the ion implantation may be performed at substrate temperature in a range of 200° C. to 600° C. to minimize defect formation. The implantation mask, which is compatible with the implantation conditions and is stripped following implantation, has a thickness and stopping power sufficient to block the implantation of ions in masked areas. In an embodiment, the doped region 18 may be doped (e.g., heavily doped) with a concentration of an n-type dopant (e.g., nitrogen and/or phosphorus) to provide n-type electrical conductivity. In an embodiment, the doped region 18 may be doped with a higher concentration of the n-type dopant than the semiconductor layer 14.
With reference to
A doped region 28 may be formed in the semiconductor layer 14 beneath and adjacent to the trench bottom 26 of each trench 22. The doped regions 28 are positioned in a vertical direction between the trenches 22 and the bulk substrate 12 operating as the drain of the field-effect transistor. The doped regions 28 have an opposite conductivity type from the semiconductor layer 14 and the doped region 16. The doped regions 28, which are formed after forming the trenches 22 and are self-aligned to the trenches 22, may define p-shields of the field-effect transistor and may be connected to the doped region 16.
The doped regions 28 may be formed by introducing a dopant of a given conductivity type by, for example, ion implantation into the semiconductor layer 14. The trenches 22 may determine, at least in part, the location and horizontal dimensions of the doped regions 28. The dielectric layer 20 has a thickness and stopping power sufficient to block the implantation of ions in masked areas. The implantation conditions (e.g., ion species, dose, kinetic energy, substrate temperature, tilt angle) may be selected to tune the electrical and physical characteristics of the doped regions 28. In an embodiment, the ion implantation may be performed at substrate temperature in a range of 200° C. to 600° C. to minimize defect formation. In an embodiment, the doped regions 28 may be doped with a concentration of a p-type dopant (e.g., aluminum) to provide p-type electrical conductivity.
A high-temperature anneal may be performed following the implantations to activate the implanted dopants and to alleviate post-implantation crystal damage. The high-temperature anneal may be performed with a removable carbon capping layer applied as a temporary coating and at a high temperature, such as a temperature in a range of 1600° C. to 1900° C. The dielectric layer 20, which cannot withstand the high anneal temperature, is removed from the top surface 13 before the anneal is performed and before the carbon capping layer is applied. The removable carbon capping layer may prevent silicon outgassing during the high-temperature anneal. The carbon capping layer, which may be comprised of a cured and/or baked photoresist or a deposited layer of carbon, is removed following the high-temperature anneal.
With reference to
The semiconductor layer 14 bordering the sidewalls 24 and trench bottoms 26 of the trenches 22, as well as the top surface 13, may be subjected to a cleaning pre-treatment, before depositing the gate dielectric layer 32, that removes a thin surface layer of the semiconductor material. In an embodiment, the cleaning pre-treatment may include a wet chemical cleaning process. In an embodiment, the cleaning pre-treatment may include a plasma etching process. In an embodiment, the cleaning pre-treatment may include a thermal oxidation process to form a thin sacrificial oxide layer followed by a strip of the sacrificial oxide layer. In an embodiment, the cleaning pre-treatment may include a bake in a hydrogen atmosphere at a substrate temperature in the range of 1100° C. to 1500° C. to etch and remove a thin surface layer of the semiconductor material of the semiconductor layer 14 bordering the trenches 22 and the top surface 13. The hydrogen bake may also function to round the corners of the trenches 22 at the trench bottoms 26. In an embodiment, an isotropic etching process may be employed to provide the surface clean and the corner rounding.
In an embodiment, the cleaning pre-treatment may utilize an atomic layer etching process that relies on cyclic exposure to a process gas and ion bombardment to treat the exposed surface of the semiconductor layer 14 before forming the gate dielectric layer 32. In an embodiment, atoms from a process gas, such as chlorine, are absorbed onto the surface of the semiconductor layer 14 bordering the sidewalls 24 and trench bottoms 26 of the trenches 22, as well as the top surface 13. The absorbed process gas weakens the binding energy of the surface so that atoms at the surface of the semiconductor layer 14 are easier to remove than the atoms in the underlying bulk. Ion bombardment with energetic ions, such as argon ions, removes the absorbed atoms of process gas together with chemisorbed atoms of the semiconductor material of the semiconductor layer 14. The removal portion of the process may be self-limiting and stop after the absorbed atoms of process gas are exhausted. For example, the semiconductor material of the semiconductor layer 14 may be removed with a precision of a single atomic monolayer at the surface and with minimal damage to underlying monolayers of atoms in the bulk. The atomic layer etching process may also function to round the corners of the trenches 22 at the trench bottoms 26, and the corner rounding may differ from the corner rounding observed following a hydrogen bake.
The atomic layer etching process may smooth the surface of the semiconductor layer 14, thereby reducing surface roughness scattering that may limit channel mobility at high gate fields. The atomic layer etching process may also remove asperities in the surface of the semiconductor layer 14 and thereby reduce or prevent the formation of locally-thinner regions of the gate dielectric layer 32. The elimination of such locally-thinner regions may improve the performance of gate dielectric layer 32 at small thicknesses (e.g., a thickness of 30 nm or less). In an embodiment, the atomic layer etching process may remove a thickness of about 2.5 nanometers to about 20 nanometers from the surface of the semiconductor layer 14. In an embodiment, the atomic layer etching process may remove a thickness of about 5 nanometers to about 10 nanometers from the surface of the semiconductor layer 14.
With reference to
In an embodiment, the gate dielectric layer 34 may be a high temperature oxide (HTO) deposited by low pressure chemical vapor deposition at a substrate temperature in a range between 400° C. and 1000° C. In an embodiment, the gate dielectric layer 34 may be deposited at a higher substrate temperature than the gate dielectric layer 32. In an embodiment, the gate dielectric layer 34 may be a high temperature oxide (HTO) deposited by low pressure chemical vapor deposition at a substrate temperature of about 800° C. and using dichlorosilane and oxygen as reactants. In an alternative embodiment, the gate dielectric layer 34 may be silicon dioxide deposited by chemical vapor deposition using tetraethoxysilane as a reactant. In an alternative embodiment, the gate dielectric layer 34 may be silicon dioxide deposited by low pressure chemical vapor deposition at a substrate temperature of about 400° C. and using silane and oxygen as reactants. In an alternative embodiment, the gate dielectric layer 34 may be silicon dioxide deposited by plasma enhanced chemical vapor deposition at a substrate temperature of about 400° C.
In an embodiment, the gate dielectric layer 34 may have a thickness in a range between 10 nm and 50 nm. In an embodiment, the gate dielectric layer 34 may be thicker than the gate dielectric layer 32. In an embodiment, the gate dielectric layer 32 may have a thickness in a range between 2.5 nm and 10 nm, the gate dielectric layer 34 may have a thickness in a range between 10 nm and 50 nm, and the gate dielectric layer 34 may be thicker than the gate dielectric layer 32. The total thickness of the gate dielectric layers 32, 34, which define a conformal liner inside each of the trenches 22, may be contingent upon the gate-source voltage for a given application. In an embodiment, the total thickness of the gate dielectric layers 32, 34 may be in a range between 12.5 nm and 60 nm.
The gate dielectric layers 32, 34 may be annealed to reduce defects, such as interface traps. In an embodiment, the gate dielectric layers 32, 34 may be annealed in an ambient including nitric oxide. In an embodiment, the gate dielectric layers 32, 34 may be annealed in an ambient including nitric oxide at a substrate temperature in a range between 1100° C. and 1350° C. In an embodiment, the gate dielectric layers 32, 34 may be annealed in an ambient including only nitrogen. In an embodiment, the gate dielectric layers 32, 34 may be annealed in an ambient including only nitrogen at a substrate temperature in a range between 1250° C. and 1400° C. In an embodiment, the gate dielectric layers 32, 34 may be annealed in a forming gas ambient including a mixture of hydrogen and nitrogen. In an embodiment, the gate dielectric layers 32, 34 may be annealed in a forming gas ambient at a substrate temperature in a range between 1000° C. and 1400° C. In an alternative embodiment, two or more annealing process may be sequentially preformed, such as an anneal in a nitrogen ambient followed by an anneal in a nitric oxide ambient. In an embodiment, the gate dielectric layers 32, 34 may be annealed in an ambient including nitrous oxide.
With reference to
With reference to
With reference to
Silicide layers 42 are formed by a silicidation process on exposed areas of the top surface 13. The silicide layers 42 may be comprised of a metal, such as nickel. An electrode 44 comprised of, for example, aluminum may be formed that is coupled by the silicide layers 42 to the doped region 19 and doped region 18. A barrier layer 41, such as a bilayer of titanium and titanium nitride, may be disposed between the electrode 44 and the silicide layers 42. The dielectric layer 38 inside each trench 22 electrically isolates the electrode 44 from the gate electrodes defined by the gate conductor layers 36 in the trenches 22.
The deposition of multiple gate dielectric layers 32, 34 eliminates the need to thermally grow an oxide layer on the surfaces bordering the trenches 22. The amount of carbon incorporated from the semiconductor layer 14 into the deposited gate dielectric layers 32, 34 may be significantly reduced in comparison with carbon incorporation into silicon dioxide formed by thermal oxidation. For example, the substrate temperature used when deposited in the gate dielectric layer 32 may be significantly lower than the substrate temperature during thermal oxidation. As a result, the gate dielectric layers 32, 34 may include exhibit a lower interface trap number density and a lower interface trap level density in comparison with an oxide layer formed by thermal oxidation, and the carrier mobility in an inversion layer beneath the gate dielectric layers 32, 34, during operation, may be higher due to the reduction in interface traps.
Reliance upon multiple gate dielectric layers 32, 34 permits the gate dielectric layer 32 to be deposited at a lower substrate temperature than the gate dielectric layer 34 to limit carbon incorporation, and then to add the gate dielectric layer 34 at a higher substrate temperature with the silicon dioxide of the gate dielectric layer 32 sealing the wide bandgap semiconductor material. The gate dielectric layer 32 may be thinner than the gate dielectric layer 34, and the gate dielectric layer 32 may have a higher quality than the gate dielectric layer 34. Quality for silicon dioxide may refer to the electrical properties of the silicon carbide-oxide interface and the oxide density. For example, the silicon dioxide of the gate dielectric layer 32 may have a higher density than the silicon dioxide of the gate dielectric layer 34.
With reference to
With reference to
With reference to
The methods as described above are used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (e.g., as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. The chip may be integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either an intermediate product or an end product. The end product can be any product that includes integrated circuit chips, such as computer products having a central processor or smartphones.
References herein to terms modified by language of approximation, such as “about”, “approximately”, and “substantially”, are not to be limited to the precise value specified. The language of approximation may correspond to the precision of an instrument used to measure the value and, unless otherwise dependent on the precision of the instrument, may indicate a range of +/−10% of the stated value(s).
References herein to terms such as “vertical”, “horizontal”, etc. are made by way of example, and not by way of limitation, to establish a frame of reference. The term “horizontal” as used herein is defined as a plane parallel to a conventional plane of a semiconductor substrate, regardless of its actual three-dimensional spatial orientation. The terms “vertical” and “normal” refer to a direction in the frame of reference perpendicular to the horizontal, as just defined. The term “lateral” refers to a direction in the frame of reference within the horizontal plane.
A feature “connected” or “coupled” to or with another feature may be directly connected or coupled to or with the other feature or, instead, one or more intervening features may be present. A feature may be “directly connected” or “directly coupled” to or with another feature if intervening features are absent. A feature may be “indirectly connected” or “indirectly coupled” to or with another feature if at least one intervening feature is present. A feature “on” or “contacting” another feature may be directly on or in direct contact with the other feature or, instead, one or more intervening features may be present. A feature may be “directly on” or in “direct contact” with another feature if intervening features are absent. A feature may be “indirectly on” or in “indirect contact” with another feature if at least one intervening feature is present. Different features “overlap” if a feature extends over, and covers a part of, another feature.
The descriptions of the various embodiments of the present invention have been presented for purposes of illustration but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
This application is a continuation-in-part of application Ser. No. 18/114,313, filed Feb. 27, 2023, which is hereby incorporated by reference herein in its entirety.
| Number | Date | Country | |
|---|---|---|---|
| Parent | 18114313 | Feb 2023 | US |
| Child | 18228713 | US |
