Patent Application
20080079159
Novel features believed characteristic of the present disclosure are set forth in the appended claims. The disclosure itself, however, as well as a preferred mode of use, various objectives and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings. The functionality of various circuits, devices or components described herein may be implemented as hardware (including discrete components, integrated circuits and systems-on-a-chip ‘SoC’), firmware (including an application specific integrated circuit ‘ASIC’ and programmable chips) and software or a combination thereof, depending on the application requirements. Similarly, the functionality of various mechanical elements, members, and components, or a combination thereof for forming modules, sub-assemblies and assemblies assembled in accordance with a structure for an apparatus may be implemented using various materials and coupling techniques, depending on the application requirements.
Traditional tools and methods for strengthening low k dielectric materials may be inadequate to withstand high stress conditions encountered during the fabrication and testing of semiconductor devices. In addition, some of the traditional methods may be costly, time consuming, and ineffective in being integrated into existing integrated circuit fabrication processes. This problem may be addressed by an improved system and method for a focused strengthening of the structure of low k dielectric materials to reduce the induced stress. According to an embodiment, in an improved system and method for relieving stress induced within a dielectric layer of a semiconductor device, areas in the dielectric layer where the stress exceeds a threshold are identified. The areas, which are in parallel alignment with electrical interconnects such as conductive bumps, include a selected number of outer rows of the conductive bumps having a high stress level. Within the identified areas where the stress exceeds the threshold, patterned zones having an adjustable zone density are provided by adding reinforcing elements to relieve the stress below the threshold.
The following terminology may be useful in understanding the present disclosure. It is to be understood that the terminology described herein is for the purpose of description and should not be regarded as limiting.
Electrical Interconnect—A technique to provide electrical coupling between two electrical elements. The electrical interconnect uses conductive material such as metal (e.g., aluminum, copper, silver, gold, and similar others including alloys) to achieve the electrical interconnection. The interconnect, which is an essential part of any semiconductor device, may include conductive traces, conductive bumps, solder bumps, vias, metal planes, bond wires, metal lands, metal planes, bond wire areas, conductive pads, metal studs, and similar others.
Ball grid array (BGA)—A type of chip package type that enables direct mounting of the chip to a substrate or printed circuit board via solder balls or bumps. The solder balls or bumps are arranged in a grid-style array and found on the underside of the chip to make the electrical connection to the outside.
Flip Chip (FC)—A technique to surface mount a chip or die on to a substrate (or a board) by flipping and directly connecting the chip or die to the substrate without using traditional wire bonding technique. The direct connection is typically via solder balls or conductive bumps. The gap between the chip and the substrate is underfilled with a polymeric material. A FC package configuration includes at least one semiconductor chip or die mounted in an active surface-down manner over a substrate (or another semiconductor chip) electrically and mechanically coupled to the same by means of the conductive bumps.
Chip scale package (CSP)—A chip package in which the total package size is no more than 20% greater than the size of the die within.
Low k dielectric—A dielectric material having a constant k value of less than 4.0, preferably below 2.5. Low k dielectric materials may be formed from hybrids of organic and silicate materials, such as organosilicate glass (OSG).
Wirebond package—Wirebonding is an electrical interconnection technique that uses thin wires and a bonding agent such as a heat, pressure and ultrasound energy or a combination thereof. Well known semiconductor device packages that use wirebonding (referred to as a ‘wirebond package’) include ball grid array (single chip and multi-chip), ceramic and plastic quad flat packages, chip scale packages, and a chip on board (COB) package.
Mechanical or structural strength of a dielectric—The mechanical or structural strength of a dielectric is a property of the dielectric that enables it to resist deformation under load or stress. The mechanical or structural strength of the dielectric material is primarily determined by factors such as the density and porosity of the bulk material forming the dielectric. The strength of the dielectric may refer to its tensile strength, shear strength, cohesive and adhesive strength, and/or fracture toughness. Ultimate strength is the maximum stress level that the material can withstand without a failure. The ultimate strength may be classified into three main groups according to the applied stress type, e.g., ultimate tensile strength (UTS), ultimate compression strength, and ultimate shear strength. Tensile strength is measured in units of force per unit area, e.g., newtons per square meter (N/m2) or pascals (Pa), with prefixes as appropriate.
Reinforcing Elements—Conductive elements such as metal vias that are selectively added to a dielectric layer of a semiconductor device to specifically reinforce and improve the stress bearing capability of the dielectric layer. The reinforcing elements are positioned to absorb a large portion of the induced stress within the dielectric layer, thereby providing improved stress protection to the semiconductor device. Specifically, the reinforcing elements are intentionally added to relieve the stress below the threshold. The process to form the reinforcing elements is identical to the well-known process to form vias.
Zone Density—The zone density is an indicator of a ‘local’ density of a material within a selectable zone. The zone density is a ratio of a cross sectional area of the reinforcing elements included within the selectable zone to an area, e.g., cross sectional area, of the selectable zone. The zone density may also be computed as a ratio of a volume of metal contained within a volume of the selectable zone to the volume of the selectable zone. The zone density computed as a ratio of areas generally assumes a uniform distribution of the volume of the metal. In applications, where distribution of the metal volume is not uniform, e.g., conically shaped vias, volume based zone density computations may be more desirable compared to area based computations.
The present disclosure provides the tools and methods for focused strengthening of low k dielectric material by selectively adding reinforcing elements to high stress areas. Patterned zones having increased density due to the addition of the reinforcing elements are formed in the high stress areas of the dielectric layer. The addition of the reinforcing elements advantageously improves the stress bearing capability of the dielectric layer to withstand the stress induced during the assembly and testing process, as described with reference to
A plurality of contact pads 116 are disposed on the stack 180. In an exemplary, non-depicted embodiment, the plurality of contact pads 116 may include 3 layers with the first layer being preferably made of aluminum, copper-doped aluminum, or copper or a combination thereof, a second layer made from a refractory metal such as titanium or tungsten, and a third layer made from a noble metal such as palladium, gold, or platinum.
The die 110 is mounted on the substrate 120 integral with interconnections and a plurality of terminal pads 122, yet spaced apart by the gap 140. The substrate 120 preferably includes a printed circuit board made of FR-4 or a glass-epoxy laminate, and the plurality of terminal pads 122 are preferably composed of solder-wettable copper. The die 110 is attached by reflowable solder bumps 130, which extend across the gap 140 and connect the plurality of contact pads 116 on the die 110 to a corresponding one of the plurality of terminal pads 122 on the substrate 120 both electrically and mechanically. Preferably, tin or a tin alloy (such as tin/indium, tin/bismuth, tin/lead) of a desirable melting temperature is chosen for the conductive bumps 130 to accomplish the reflow at a practical temperature. For silicon packages, a protective “solder mask” (not shown) may be made of a variety of insulating materials including polymers such as polyimide. Although the die 110 is shown to be mounted as a flip chip, other types of mounting such as upright with wire bonding are also contemplated. In a particular embodiment, the semiconductor device assembly 100 may be packaged as at least one of a chip scale package (CSP) and a ball grid array (BGA) package. In an exemplary, non-depicted embodiment, the semiconductor device assembly 100 may be packaged as a traditional wirebond package.
In the presence of an induced stress, the IMD layer may be exposed to a lower risk compared to the ILD layer, since the IMD layer has a higher metal density compared to the ILD layer. That is, due to the presence of the interconnect metal 228 in the IMD layer such as IMD1220, IMD2222, IMD3224, and IMD4226, the density and hence the stress bearing capability of this layer may be greater than the stress induced. However, a non-reinforced ILD layer such as ILD2230, ILD3232, and ILD4234 may not have sufficient strength to withstand the stress induced. As such, the non-reinforced ILD layer may be subject to damage when the induced stress exceeds its strength. Thus, within one interconnect layer, the IMD layer may be better equipped to handle induced stress, whereas the non-reinforced ILD layer may be unable to handle the induced stress due to the difference in their respective densities.
In an embodiment, areas within the non-reinforced ILD layer where the stress exceeds a threshold are identified by using modeling and simulation tools, by conducting a stress test, or by a combination thereof. The threshold stress value for a selected area within an ILD layer is a particular stress value, which if exceeded may cause an undesirable change in the ILD layer. The threshold value is dependent on the materials selected to form the ILD layer, and may be determined by using well-known material properties, modeling and simulation tools, by conducting a stress test or by a combination thereof. Since the stress induced during processes such as die attach, propagates radially outward in three dimensions from the conductive bumps 130, the areas in the non-reinforced ILD layer that experience stress levels exceeding the threshold are radially aligned with the conductive bumps 130.
Selective and intentional addition of the reinforcing elements 240 advantageously improves the stress bearing capability of the ILD layers such as ILD2R 236, ILD3R 238, and ILD4R 242 by adjusting a zone density to reduce the induced stress within these layers to be less than the threshold. Additional details of adjusting the zone density to reduce induced stress levels are described with reference to
In the depicted embodiment, the reinforcing elements 240 comprise a conductor material, which is selectable to be one of copper, gold, aluminum, tungsten, and a combination thereof. In an embodiment, the reinforcing elements are metal vias. The effective strength of the stack 202 is improved when the ILD layer (ILD2R 236, ILD3R 238, and ILD4R 242) is selectively reinforced with metal vias. The overall ILD layer acts as a composite of the two materials, e.g., the low k dielectric and the metal via, with most of the load or stress being supported by the stiffer metal vias. This has the effect of reducing the stresses in the low-k dielectric and thus reducing the chances of failure due to cohesive fracture, which may lead to an electrical failure in the metallization around this layer.
In an exemplary, non-depicted embodiment, the reinforcing elements 240 may be formed from materials other than metal. For example, the reinforcing elements 240 may be fabricated from an electrically or thermally conductive material or an insulating material provided the mechanical strength of the composite of the two materials (e.g., low k dielectric and other reinforcing material) is greater than the induced stresses. That is, provided the reinforcing material formed from materials other than metal results in stress relief in the low-k dielectric. In an embodiment, the reinforcing elements 240 comprise a dielectric material having a stress bearing capability that is greater than the stress induced by a predefined amount. In an embodiment, the dielectric material is selectable to be one of silicon oxide, silicon nitride, and silicon carbide. The materials for the reinforcing elements other than metal may also include any chemically vapor deposited (or atomic layer deposited) dielectric whose stress bearing capability exceeds that of the underlying low K material by a predefined amount. As described earlier, the reinforcing elements 240 may be arranged in the patterned zone 250 that has a shape other than a circle. For example, the reinforcing elements 240 may be arranged to from patterned zones having a cross sectional shape of an annular ring, a crescent, or a square bar. In an embodiment, each one of the cross sectional areas may vary between approximately 75% and 125% of a cross sectional area of one of the conductive bumps 130. In a particular embodiment, a ratio of the diameter of each one of the conductive bumps 130 to the diameter of each one of the reinforcing elements 240 may vary from approximately 50 to approximately 1000.
As described earlier, the zone density is an indicator of a local density of a material within a selectable zone. The zone density is a ratio of a cross sectional area of the reinforcing elements 240 included within the patterned zone 250 to an area, e.g., cross sectional area, of the patterned zone 250. In an embodiment, the zone density may also be computed as a ratio of a volume of metal contained within a volume of the patterned zone 250 to the volume of the patterned zone. The zone density computed as a ratio of areas generally assumes a uniform distribution of the volume of the metal. In applications, where distribution of the metal volume is not uniform, e.g., conically shaped vias, volume based zone density computations may be more desirable compared to area based computations. In an embodiment, the ratio may be adjustable between 0 and 95 percent.
Referring back to
Adherence to particular design rules such as ‘active and/or dummy vias or metal not to exceed 10%’, which may be used in processes such as chemical mechanical planarization (CMP), may not necessarily always provide sufficient stress relief. Hence, tools and techniques described herein that first determine areas of high stress levels followed by the focused use of reinforcing elements may be desired to provide the sufficient stress relief. In the depicted embodiment, for the particular set of materials used, the reinforcing elements advantageously reduce the stress level below the threshold. That is, the approximate 50% reduction was sufficient for the material used to lower the stress level below the threshold. It is understood, that depending on the materials used in the fabrication of the semiconductor device, adjustment of the zone density above 25% may be desirable to obtain a higher and/or lower reduction in the maximum stress level to achieve a desired level that is at least below the threshold. However, as described earlier, it is desirable that the overall ILD layer density is less than 10% to retain the dielectric properties. Although the graphical representation 300 illustrates stress induced during the die attach process and during temperature cycling, it is understood that the semiconductor device assembly 100 having the reinforced elements 240 substantially reduces stress induced during other processes such as reflow, wirebond formation, die probing and similar others.
Various steps described above may be added, omitted, combined, altered, or performed in different orders. For example, an additional step may be added to vary the density to maximize the stress relief. At step 430, the number of reinforcing elements added within the pattern zone (which determines the zone density) is adjusted to provide a desirable zone density varying from 0% to about 95%.
Several advantages are achieved by the method and system according to the illustrative embodiments presented herein. The embodiments advantageously provide for selectively adding the reinforcing elements 240 in the ILD layer of the semiconductor device assembly 100 to improve the stress bearing capability. In an exemplary semiconductor device, increasing density of the reinforcing elements 240 advantageously results in reducing the stress in the ILD layer compared to an ILD layer without the reinforcing elements. Thus, the focused approach of reinforcement provides targeted stress relief without substantially compromising insulation properties of the ILD. This advantageously enables semiconductor manufacturing facilities to improve production rates, quality and reliability.
Although illustrative embodiments have been shown and described, a wide range of modification, change and substitution is contemplated in the foregoing disclosure and in some instances, some features of the embodiments may be employed without a corresponding use of other features. Those of ordinary skill in the art will appreciate that the hardware and methods illustrated herein may vary depending on the implementation. As described earlier, while certain aspects of the present disclosure have been described in the context of flip chip mounting, those of ordinary skill in the art will appreciate that the processes disclosed are capable of being used for assembly of semiconductor devices using different types of mounting techniques including conventional mounts with wire bonding. For example, in a flip chip the stress concentration in the back end of line (BEOL) is primarily under the bumps, as bumps form the link between the die and the substrate. Similar issues exist in wirebond packages when the bond pad is probed, during wire bonding process, and during temperature cycling. Additionally, although stresses generated within the chip are described as being both mechanical and thermomechanical, additional types of stresses may also be created due to other types of loads.
The methods and systems described herein provide for an adaptable implementation. Although certain embodiments have been described using specific examples, it will be apparent to those skilled in the art that the invention is not limited to these few examples. The benefits, advantages, solutions to problems, and any element(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or an essential feature or element of the present disclosure.
The above disclosed subject matter is to be considered illustrative, and not restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments, which fall within the true spirit and scope of the present disclosure. Thus, to the maximum extent allowed by law, the scope of the present disclosure is to be determined by the broadest permissible interpretation of the following claims and their equivalents, and shall not be restricted or limited by the foregoing detailed description.
