Patent Application
20120002377
The present invention relates to galvanic isolation in an electrical system and, in particular, to formation of a galvanic isolation transformer on a dielectric (e.g., quartz or glass) substrate.
Any electrical system that includes systems that have different ground references or that have the capability to produce current surges is required to incorporate galvanic isolation to protect both the system and the user.
Galvanic isolation for integrated circuits requires a device that electrically isolates two systems to a high target isolation voltage, e.g. 5 kV, but that transmits data between systems that are at different ground potentials. There are a number of solutions available that offer galvanic isolation between two systems. One solution is a multi-die approach that utilizes a transformer between the die that are to be isolated from each other; short pulses generated on one die system are transmitted across the transformer to be decoded by the second die system. Another solution is similar to that just described, but uses a capacitor to isolate the two die systems instead of a transformer. Yet another solution utilizes optical coupling, whereby a light emitting diode (LED) on one die system emits light and a photodiode on the second die system detects the light and generates corresponding electrical current.
There are two basic types of integrated circuit (IC) transformers commonly utilized in the semiconductor IC industry: an inter-wound planar type and a stacked type. The inter-wound type utilizes a single metal layer and the windings are separated based upon layout design. The stacked type utilizes two layers of metal that are separated by a distance that is great enough to hold off the voltage difference in the two windings.
In order to provide galvanic isolation of, for example an IC having a voltage of greater than or equal to the isolation target voltage of, e.g., 5 kV associated therewith, at least four types of isolation are required: winding-to-winding isolation, winding-to-substrate isolation, bond wire-to-bond wire isolation and die-to-die isolation. The minimum distance for winding-to-winding isolation is determined from the dielectric strength of the insulator used between the windings. Table 1 below provides an overview of several dielectric materials commonly utilized in the semiconductor processing and packaging industry and the distance required for isolation of 5 kV. Typically, the distances utilized in an actual device are greater to safely account for differences in dielectric quality and uniformity.
The minimum distance for winding-to-substrate isolation is determined differently for a stacked transformer and an inter-wound transformer. For a stacked transformer, the high voltage side is in the top metal layer which, by design, is located a sufficient distance from the substrate to avoid dielectric breakdown to the substrate. For an inter-wound transformer, however, the metal layer, i.e. both windings of the transformer, must be sufficiently distanced from the silicon substrate so that dielectric breakdown does not occur at the isolation voltage. The distance is similar to the distances shown in Table 1 and depends upon the material stack between the metal layers and the substrate.
The bond wire-to-bond wire spacing is dictated by the molding compound with which the final package is injected. A typical compound might be the Sumitomo G700 series of molding compounds that has a listed dielectric strength of 15 V/μm. The spacing between bond pads and wires must be sufficiently large that breakdown will never occur in the molding compound. The molding compound is the least well controlled of all materials within the package and, therefore, would introduce too much variation.
The die-to-die breakdown voltage is similarly defined through the molding compound. Typically, integrated circuits are built on silicon substrates on copper leadframes, which means that two silicon die cannot be mounted on the same die attach pad (DAP). This forces the use of two DAP leadframes with a space in between which is subsequently filled with molding compound. Similarly to the wire bonds, the distance between the two DAPs must be sufficient to exceed the rated dielectric withstand voltage.
In an embodiment of the subject matter claimed herein, an integrated circuit system comprises a first integrated circuit die having a first integrated circuit formed thereon, a second integrated circuit die having a second integrated circuit formed thereon, and a transformer formed on a dielectric substrate (e.g., quartz or glass) and electrically connected between the first integrated circuit and the second integrated circuit to provide galvanic isolation therebetween.
In another embodiment of the subject matter claimed herein, an integrated circuit system comprises a quartz or glass substrate, a first integrated circuit die system attached to the substrate and having a first voltage associated therewith, a second integrated circuit die system attached to the substrate and having a second voltage associated therewith, the second voltage being less than the first voltage, and a transformer formed on the substrate and electrically connected between the first integrated circuit die system and the second integrated circuit die system to provide galvanic isolation therebetween.
In another embodiment of the subject matter claimed herein, a method of forming an integrated circuit system comprises providing a first integrated circuit die having a first integrated circuit formed thereon, providing a second integrated circuit die having a second integrated circuit formed thereon, and electrically connecting a transformer formed on a dielectric substrate (e.g., quartz or glass) between the first integrated circuit and the second integrated circuit to provide galvanic isolation therebetween.
The features and advantages of the various aspects of the subject matter disclosed herein will be more fully understood and appreciated upon consideration of the following detailed description and the accompanying drawings, which set forth illustrative embodiments in which the concepts of the claimed subject matter are utilized.
As discussed above, typical integrated circuit transformer processes for galvanic isolation of high voltage, e.g., voltage levels of equal to or greater than 5 kV, require that the high voltage winding of the transformer (interwoven or stacked) be a significant distance above the semiconductor (e.g., silicon) wafer substrate in order to avoid leakage or dielectric breakdown to the substrate. This results in significant additional processing and cost. The subject matter disclosed and claimed herein provides a process whereby a galvanic isolation transformer may be created in one or more layers of metal, but above a quartz wafer rather than a silicon wafer. Quartz, similar to silicon dioxide, is a dielectric isolator, which therefore means that the breakdown from the high voltage winding of the transformer to the substrate is removed.
The integrated circuit system design shown in
The transformer 202 may be either an inter-wound type that utilizes a single metal layer and windings that are separated by dielectric material based upon layout design or a stacked type that utilizes two layers of metal that are separated by dielectric material by a distance that is great enough to hold off the voltage difference between the two windings. In both the inter-wound transformer type and the stacked transformer type, the dielectric material may be selected from (but not limited to) the dielectric material identified in Table 1 above. The transformers described herein are air core transformers; however, those skilled in the art will appreciate that the concepts disclosed herein are also applicable to transformers with magnetic cores.
The processing aspects of the inter-wound planar transformer embodiment 300 shown in
An additional advantage in using a quartz substrate is in the frequency domain where the common figure of merit, used for inductors, is called “the Q factor” and is defined as the ratio of the Imaginary impedance to the Real impedance. In an inductor or transformer formed on a silicon substrate, as the frequency increases, eddy currents occur in the silicon substrate. This is a well known phenomenon in integrated spiral inductors in silicon. Utilization of a quartz substrate effectively removes the presence of eddy currents and allows the inductor or transformer to attain its maximum possible frequency response. The result is that the maximum Q is greatly increased. (It is noted that those skilled in the art will appreciate that the concepts and subject matter disclosed herein with respect to transformers formed on quartz substrates are equally applicable to inductors formed on quartz substrates.)
It should be understood that the particular embodiments described herein have been provided by way of example and that other modifications may occur to those skilled in the art with departing from the scope of the claimed subject matter as expressed in the appended claims and their equivalents.
