Patent Application
20100148174
The present invention relates to GaN epitaxial wafers and semiconductor devices, and to methods of manufacturing GaN epitaxial wafers and semiconductor devices.
In order to improve light-emitting efficiency and other microelectronic element properties in the fabrication of semiconductor devices such as LEDs, monocrystalline GaN wafers have conventionally been employed. The below-referenced Patent Document 1, for example, discloses a method of producing a wafer of GaN single crystal by growing a ZnO layer onto a substrate of a high-quality material such as sapphire, and thereafter changing the crystallographic polarity of the ZnO layer and growing on it a GaN single crystal and then dissolving off the ZnO layer.
Patent Document 1: Japanese Unexamined Pat. App. Pub. No. 2004-284831
When monocrystalline GaN wafers are employed to attempt to fabricate semiconductor devices, however, the following problem occurs. Namely, in the process of growing epitaxial layers onto single-crystal wafers and in the process of singulating the semiconductor devices after epitaxial-layer formation, cracks are likely to occur in the epitaxial layers and single-crystal wafers. In employing single-crystal wafers to fabricate semiconductor devices, the occurrence of faults is thus frequent, such that production yields have not necessarily been high.
An object of the present invention, brought about taking the above into consideration, is to make available GaN epitaxial wafers designed to improve production yields, as well as semiconductor devices utilizing such GaN epitaxial wafers, and methods of manufacturing such GaN epitaxial wafers and semiconductor devices.
In order to achieve the above object, a GaN epitaxial wafer of the present invention is characterized in including: a first GaN layer formation step of epitaxially growing a first GaN layer onto a substrate; a pit formation step, following the first GaN layer formation step, of forming pits in the front side of the substrate; and a second GaN layer formation step, following the pit-formation step, of epitaxially growing a second GaN layer onto the first GaN layer.
According to the foregoing manufacturing method, forming pits in the front side of the substrate after epitaxially growing a first GaN layer onto the substrate alters the growth direction of the first GaN layer in the proximity of the pits. Because the first GaN layer growth direction in the other regions does not alter, areas appear where the growth direction differs from the growth direction that the first GaN layer epitaxially grown at the beginning possesses, bringing about a state in which zones having a plurality of growth directions exist within the first GaN layer. When the second GaN layer is thereafter epitaxially grown onto the first GaN layer having a plurality of growth directions, the GaN layer where the growth direction differs grows as different crystal, whereby a GaN epitaxial wafer having a polycrystalline GaN layer is fabricated.
The present inventors, capping intensive research efforts, discovered that utilizing GaN epitaxial wafers obtained by the present manufacturing method to fabricate semiconductor devices made it possible to reduce the above-described occurrence of cracking in the epitaxial layers and in the wafers, enabling improvement in production yields in the fabrication of semiconductor devices to be realized.
A GaN epitaxial wafer manufacturing method of the present invention may be conditioned by having a mask-layer formation step, prior to the first GaN layer formation step, of patterning a mask layer onto the front side of the substrate.
A GaN epitaxial wafer manufacturing method of the present invention may also be conditioned by the substrate being constituted by a single layer. In that case, in the pit formation step the pits are formed onto the single-layer substrate.
The method alternatively may be conditioned by the substrate being constituted by a plurality of layers, wherein in the pit formation step the pits are formed on the uppermost layer of the substrate. According to these terms, the materials that may be selected for the substrate multiply. GaN epitaxial wafers involving the present invention can therefore be fabricated under broader-ranging production requisites.
In a semiconductor device manufacturing method of the present invention, included are: a first GaN layer formation step of epitaxially growing a first GaN layer onto a substrate; a pit formation step, following the first GaN layer formation step, of forming pits in the front side of the substrate; a second GaN layer formation step, following the pit-formation step, of epitaxially growing a second GaN layer onto the first GaN layer to fabricate a GaN epitaxial wafer; and a device manufacturing step of utilizing the GaN epitaxial wafer to fabricate semiconductor devices.
In this implementation, forming pits in the front side of the substrate after growing a first GaN layer onto the substrate alters the growth direction of the first GaN layer in the proximity of the pits. Because the first GaN layer growth direction in the other regions does not alter, areas appear having a growth direction that differs from the growth direction of the first GaN layer epitaxially grown at the beginning, bringing about a state in which zones that possess a plurality of growth directions exist within the first GaN layer. Utilizing to fabricate semiconductor devices the GaN epitaxial wafer obtained by thereafter epitaxially growing the second GaN layer onto the first GaN layer having a plurality of growth directions makes it possible to reduce incidents of cracking in fabricating the semiconductor devices, enabling improvement in production yields to be realized.
A semiconductor device manufacturing method of the present invention may also include a mask-layer formation step, prior to the first GaN layer formation step, of patterning a mask layer onto the front side of the substrate.
In a semiconductor device manufacturing method of the present invention, the substrate may be constituted by a single layer.
A semiconductor device manufacturing method of the present invention alternatively may be conditioned by the substrate being constituted by a plurality of layers, wherein in the pit formation step the pits are formed on the uppermost layer of the substrate.
Furthermore, a semiconductor device manufacturing method of the present invention may be conditioned by, for the device manufacturing step, utilizing to fabricate the semiconductor devices a GaN wafer obtained by removing the substrate from the GaN epitaxial wafer. Not using the substrate in the semiconductor devices lessens the restrictions on the material selected for the substrate, making it possible to employ a wider range of materials for the substrate. What is more, the fact that in the semiconductor devices only layers composed of polycrystalline GaN laminae are utilized enables semiconductor devices of superior device properties to be obtained, which can serve to further improve production yields.
A GaN epitaxial wafer of the present invention is characterized in being furnished with a substrate having pits in the major surface, and a polycrystalline GaN layer layered onto the major surface. The fact that the GaN layer laminated onto the major surface of the substrate is polycrystalline makes it possible to minimize the occurrence of cracking in semiconductor device fabrication, which can serve to further improve production yields.
A GaN epitaxial wafer of the present invention also may be furnished with a mask layer, disposed in between the substrate and the polycrystalline GaN layer.
A GaN epitaxial wafer of the present invention may also be conditioned by the substrate being constituted by a single layer.
A GaN epitaxial wafer of the present invention alternatively may be conditioned by the substrate being constituted by a plurality of layers, and therein by having the pits in the uppermost layer of the substrate.
Semiconductor devices of the present invention are characterized by having a substrate that has pits in its major surface, a GaN epitaxial wafer that has a polycrystalline GaN layer layered onto the major surface, and a semiconductor layer layered onto the polycrystalline GaN layer on the GaN epitaxial wafer. Accordingly, the fact that the GaN layer laminated onto the major surface of the substrate is polycrystalline minimizes incidents of cracking during semiconductor device fabrication, thus serving to improve production yields.
The present invention makes available GaN epitaxial wafers serving to improve production yields, and also affords semiconductor devices utilizing the GaN epitaxial wafers, and methods of manufacturing the GaN epitaxial wafers and the semiconductor devices.
Hereinafter, referring to the accompanying drawings, an explanation of embodiments of the present invention will be made in detail. It should be understood that in describing the drawings, with the same reference marks being used for identical or equivalent features, reduplicating description will be omitted.
To begin with, a single-crystal substrate 10, represented in
Next, as the first GaN layer formation step, a first GaN layer 11 is epitaxially grown onto the substrate 10, as indicated in
Subsequently, as the pit formation step, pits 10a are formed in the front side of the substrate 10, as indicated in
When GaN further grows epitaxially onto the front side of the first GaN layer 11a, a second GaN layer 12, as illustrated in
The crystal structure of the GaN epitaxial wafer 51 obtained in the manner set forth above will now be described, in comparison with a conventional, monocrystalline GaN wafer.
Given that the monocrystalline GaN wafer 50 is monocrystalline, its growth directions also, as indicated in
The present inventors discovered that utilizing a GaN epitaxial wafer composed of a GaN polycrystal in which split peaks are characterized in its XRD pattern, as sketched in
To begin with, strain can be considered to be a cause of cracking. Specifically, when semiconductor devices are fabricated using a monocrystalline GaN wafer as the foundation, epitaxial layers whose composition differs, or whose impurity level differs, from that of GaN are formed onto the substrate. The lattice constants and thermal expansion coefficients in the monocrystalline GaN wafer and the epitaxial layers therefore do not agree, owing to which in the midst of formation or following formation of the epitaxial layer, strain occurs at the interface between the wafer and epitaxial layers. The strain causes cracking.
Furthermore, another cause of cracking is believed to be that when thermal or mechanical external forces are imparted in the course of cooling the epitaxial layers after they have been formed—and further, during post-formation back side processing of the epitaxial layers and in the dicing process—cracking is likely to occur.
Yet in instances in which the GaN wafer has grain boundaries, as in the present embodying mode, the grain boundaries are believed to act as a cushioning element (function as a buffer). Specifically, it is believed that a phenomenon obtains whereby for example when strain is produced in a GaN wafer, dislocations multiply at the grain boundaries, where crystal defects are largely incorporated, mitigating the strain, or the crystal slips along the crystal defects, mitigating the strain. Accordingly, fabricating semiconductor devices utilizing a GaN epitaxial wafer constituted by polycrystal GaN in the manner of the present embodying mode is thought to make it possible to obtain the devices at, with a low incidence of cracking, high production yields.
A method, involving Embodying Mode 2, of manufacturing a GaN epitaxial wafer 52 differs compared with Embodying Mode 1, in the respect that as a mask-layer formation step a mask layer 21 is patterned onto the front side of the substrate 20. As the mask layer 21 an SiO2 film, for example, is ideally suitable. And the method whereby the mask layer is patterned may be a general formation technique. As a specific example, an SiO2 film may be applied over the entire surface, after which a mask layer 21, as indicated in
Thus, with an implementation in which the mask layer 21 is formed on the front side of the substrate 20, when pits 20a are formed in the front side of the substrate 20, as illustrated in
In Embodying Mode 2, similarly as in Embodying Mode 1, a GaN epitaxial wafer 52 incorporating a polycrystalline GaN layer can be produced as described above. Then utilizing the GaN epitaxial wafer 52 to fabricate semiconductor devices enables the devices to be obtained with minimal occurrence of cracks, for high production yields.
A method, involving Embodying Mode 3, of manufacturing a GaN epitaxial wafer 53 differs from Embodying Mode 1 and Embodying Mode 2 in the respect that the substrate 30A is composed of a plurality of layers. With an implementation in which the substrate 30A is made a plurality of layers, in the pit formation step in the present embodying mode, the pits are formed in the second substrate layer 31, which is the uppermost layer of the substrate. As the semiconductor material utilized for the second substrate layer 31, compounds such as InP, GaAs, GaP, GaN and AlN, which facilitate the forming of pits in the pit formation step, are preferable. Also, in the present embodying mode the material utilized as the first substrate layer 30 is not limited to the just-mentioned InP, GaAs, GaP, GaN, AlN and the like; materials such as sapphire substrates, for example, that do not corrode easily under etching or a like process can be utilized. An example of a specific technique whereby the second substrate layer 31 is formed onto the first substrate layer 30 is a method whereby a (0001) c-plane sapphire substrate top is readied as the first substrate layer 30, onto which a GaN crystal layer is grown using the metalorganic chemical vapor deposition (MOCVD) technique to form the second substrate layer 31.
In accordance with Embodying Mode 3 as just described, a GaN epitaxial wafer 53 incorporating a polycrystalline GaN layer can be produced. Then utilizing the GaN epitaxial wafer 53 to fabricate semiconductor devices enables the devices to be obtained with minimal occurrence of cracks, for high production yields. Furthermore, according to the present embodying mode, the fact that the substrate 30A is made up of a plurality of layers increases the choice of materials utilized for substrate 30A, enabling the GaN epitaxial wafer 53 to be produced under a broader range of manufacturing conditions.
A method, involving Embodying Mode 4, of manufacturing a GaN epitaxial wafer 54 is similar to Embodying Mode 3 in the respect that the substrate 40A is made up of a plurality of layers.
The present embodying mode is further characterized in having, similar to Embodying Mode 2, a mask-layer formation step, prior to the first GaN layer growth step, of patterning a mask layer 42.
In accordance with Embodying Mode 4 as just described, a GaN epitaxial wafer 54 incorporating a polycrystalline GaN layer can be produced. Then utilizing the GaN epitaxial wafer 54 to fabricate semiconductor devices enables the devices to be obtained with minimal occurrence of cracks, for high production yields. Furthermore, according to the present embodying mode, the fact that the substrate 40A is made up of a plurality of layers increases the choice of materials utilized for substrate 40A, enabling the GaN epitaxial wafer 54 to be produced under a broader range of manufacturing conditions.
The GaN epitaxial wafers 51 through 54 obtained according to Embodying Mode 1 through Embodying Mode 4 can be utilized without modification to fabricate semiconductor devices. Alternatively, as needed the laminar part consisting of the first GaN layer and second GaN layer can be separated from the substrate 10, 20, 30A or 40A and utilized as a polycrystalline GaN wafer in the manufacture of semiconductor devices. When a wafer obtained by separating the substrates 10, 20, 30A or 40A from GAN epitaxial wafers 51 through 54 is used as the GAN wafer from which semiconductor device with a high performance is made, because the device is provided with only a layer composed of GAN.
In the following semiconductor-device embodying modes involving the present invention, semiconductor devices utilizing polycrystalline GaN wafers 1, obtained by separating the substrates 10, 20, 30A and 40A from the GaN epitaxial wafers 51 through 54 produced according to Embodying Mode 1 through Embodying Mode 4, will be described.
The light-emitting layer 203 may be a multiquantum-well (MQW) structure—for example, in which a bilaminar GaN-layer and In0.2Ga0.8N-layer structure is stacked multi-tiered.
The semiconductor device 110 of the present embodying mode is fabricated by the following method for example. To begin with, for the device manufacturing step, the n-type GaN layer 201, the n-type AlGaN layer 202, the light-emitting layer 203, the p-type AlGaN layer 204, and the p-type GaN layer 205 are formed, in order, by MOCVD onto the front side of the GaN wafer 1. Subsequently, the p-electrode 251, at a thickness of 100 nm, is formed onto the front side of the p-type GaN layer 205. Further, the n-electrode 252 is formed on the back side of the GaN wafer 1, thereby yielding an LED—i.e., semiconductor device 110.
In accordance with Embodying Mode 5 as just described, utilizing a polycrystalline-GaN-layer-incorporating GaN epitaxial wafer to fabricate a semiconductor device makes it possible to produce a semiconductor device (LED) in which cracking is minimal and the yield rate is superior.
The semiconductor device 120 of the present embodying mode is fabricated by the following method for example. To begin with, for the device manufacturing step, as shown in
Here, to form the SiO2 film methods such as vacuum deposition or sputtering method may be employed, while etching of the SiO2 film may be by an RIE technique employing a fluorine-containing etchant gas.
In accordance with Embodying Mode 6 as just described, utilizing a polycrystalline-GaN-layer-incorporating GaN epitaxial wafer to fabricate a semiconductor device 120 makes it possible to produce a semiconductor device (LD) 120 in which cracking is minimal and the yield rate is superior.
The semiconductor device 130 of the present embodying mode is fabricated by the following method for example. For the device manufacturing step, as shown in
In accordance with Embodying Mode 7 as just described, utilizing a polycrystalline-GaN-layer-incorporating GaN epitaxial wafer to fabricate a semiconductor device 130 makes it possible to produce a semiconductor device (HEMT) 130 in which cracking is minimal and the yield rate is superior.
The semiconductor device 140 of the present embodying mode is fabricated by the following method for example. For the device manufacturing step, as shown in
In accordance with Embodying Mode 8 as just described, utilizing a polycrystalline-GaN-layer-incorporating GaN epitaxial wafer to fabricate a semiconductor device 140 makes it possible to produce a semiconductor device (Schottky diode) 140 in which cracking is minimal and the yield rate is superior.
The semiconductor device 150 of the present embodying mode is fabricated by the following method for example. For the device manufacturing step, as shown in
In accordance with Embodying Mode 9 as just described, utilizing a polycrystalline-GaN-layer-incorporating GaN epitaxial wafer to fabricate a semiconductor device 150 makes it possible to produce a semiconductor device (vertical MIS transistor) 150 in which cracking is minimal and the yield rate is superior.
Below, with GaN epitaxial wafers, and semiconductor devices fabricated based on semiconductor-device manufacturing methods, involving the present invention as embodiment examples, and with semiconductor devices fabricated employing conventional monocrystalline GaN wafers as comparative examples, a further detailed description of the present invention will be made, yet the present invention is not limited to the following embodiment examples.
The GaN epitaxial wafer utilized in the method of above-described Embodying Mode 4 was fabricated. To begin with, MOCVD was employed to grow a GaN crystal layer (corresponding to the first GaN layer) 3 μm onto 2.5-inch (Embodiments 1 to 50) as well as 3-inch (Embodiments A to E) (0001) c-plane sapphire wafers (corresponding to the first GaN layer formation step). Thereafter the sapphire wafers onto which the GaN crystal layer had been grown were taken out of the reactor, and an SiO2 film was layered onto GaN crystal layer and was patterned by a photolithographic process employing a lattice pattern with 5-μm sized windows and a 5 μm linewidth (the photographic negative of the mask pattern 60 depicted in
Subsequently, among the GaN epitaxial wafers, the portion with a layer consisting of GaN polycrystal were sliced from their sapphire substrates to yield polycrystalline GaN wafers.
The XRD patterns of the polycrystalline GaN wafers obtained by the method detailed above were recorded, and the number of sites with crystal-peak divisions and the number of peaks were determined.
The method whereby the XRD patterns were determined will be specifically set forth using
split peak mean count=(a1+ . . . +an)/n (1)
was taken as the split peak mean count.
The aforedescribed numerical value was found for a plurality of polycrystalline GaN wafers to distinguish wafers to be utilized in Embodiments 1 to 50. Utilizing these polycrystalline GaN wafers of Embodiments 1 to 50 (ten wafers for each embodiment, 500 wafers total), semiconductor devices were fabricated based on each of the following semiconductor-device manufacturing methods.
As the wafers utilized in the semiconductor devices of Embodiments A through E, fifty polycrystalline GaN wafers of 3-inch size, and whose peak-split occurrence sites were one site (n=1) and whose peak split count in the peak-split occurrence sites was 2 (making the split peak mean count 2) were readied. Utilizing these, semiconductor devices were fabricated based on each of the following semiconductor-device manufacturing methods.
Monocrystalline GaN wafers of 2.5-inch size and 400-μm thickness were used for Comparative Examples 1 through 5, and wafers of 3-inch size and 400-μm thickness for Comparative Examples A through E. These monocrystalline GaN wafers were x-ray analyzed to determine their diffraction patterns in the same manner as were the polycrystalline GaN wafers utilized in the embodiments, whereat peak-splitting did not arise in any of the analysis points.
The wafers divided into the respective embodiments/comparative examples were observed under a differential interference microscope to check for the presence of cracks. The observation zone was the entire surface of each wafer excluding a 5 mm periphery, and the observation magnification of the objective lens was set to be 20×. In instances where cracks were discovered, if there were thirty or more cracks of 100 μm or greater length, the wafer was considered to be “cracks present” and deemed a failure, and was not passed to the succeeding stage.
The crack test was conducted two times in the step of manufacturing each semiconductor device. The first time was after semiconductor layers were grown onto the wafer (in Tables I through X setting forth the results, entered as “cracking @ epi”), while the second time was after performing processes including forming an electrode on the back side of the wafer (entered as “cracking @ back lap” in Tables I through X). In Tables I through X presenting the results, the number of wafers deemed to be free of cracks (qualifying wafers) is given.
An evaluation concerning the device properties of each semiconductor device fabricated in the semiconductor device manufacturing step was as follows. To begin with, to characterize the device properties of the semiconductor devices, corresponding to the comparative examples of each semiconductor device, incorporating the monocrystalline GaN wafers, determined in each case were, with their mean values and σ being calculated: for LEDs, emission intensity; for LDs, lasing lifespan; for HEMTs, Schottky diodes, and vertical MIS transistors, “ON” resistance. On this basis the device properties of each of the semiconductor devices of the embodiments were characterized, and those having results over the value [mean—σ] for the device properties of the comparative examples were taken to be qualifying. With the devices incorporating the comparative examples, in the same way, those having results over the value [mean—σ] for the comparative-example device properties were taken to be qualifying.
Using, among the numerical values obtained from the above-described tests, the number of qualifying wafers in the two-times crack test (the number given at “cracking @ back lap” in Tables I through X) and the device-property test results (proportion of qualifying chips), the total yield rate was calculated employing the following general formula (2).
total yield=count of wafers qualifying in crack test×proportion of device-prperty-qualifying chips (%)÷10 (2)
Using the method described above, tests were conducted on the following semiconductor-device embodiments and comparative examples. Details of the method manufacturing, and the results of testing, the semiconductor-devices are presented below.
Embodiments 1 to 10 and Comparative Example 1 are LEDs being semiconductor device 110 involving Embodying Mode 5 of the present invention. The manufacturing method and testing method were as follows.
By MOCVD, a 5-μm thick n-type GaN layer, a 3-nm thick In0.2Ga0.8N layer, a 60-nm thick Al0.2Ga0.8N layer, and a 150-nm thick p-type GaN layer were epitaxially grown, in that order, as an at least single-lamina III-nitride semiconductor layer onto a 2.5-inch size, 400-μm thick polycrystalline GaN wafer (in Comparative Example 1, a monocrystalline GaN wafer was used).
Epi-wafer screening was conducted by observation under a differential interference microscope to test for the presence of cracks (first-time test).
Further, a p-electrode of 100 nm thickness was formed on the upper surface of the p-type GaN layer. Next, in order to facilitate singulating the wafers into chips, the surface of the p-type GaN layer was adhered to a polishing holder, and then a polishing process that employed a slurry containing an SiC abrasive of 30 μm mean particle diameter was carried out to bring the thickness of the polycrystalline GaN wafers (as well as monocrystalline GaN wafer) from 400 μm down to 100 μm.
Afterwards, n-electrodes of 80 μm diameter×100 nm thickness were formed in positions on the back side of the polycrystalline GaN wafers (as well as monocrystalline GaN wafer) that would become the central portions when the wafers were singulated into individual chips, and epi-wafer screening was conducted by observation under a differential interference microscope to test for the presence of cracks (second-time test). Following that, the semiconductors were singulated into individual 400 μm×400 μm chips. By the above, LEDs involving Embodiments 1 to 10 and Comparative Example 1 were fabricated, after which the device properties were tested. The results are set forth in Table I.
As is evident in Table I, the “cracking @ epi” and “cracking @ back lap” wafer counts (qualifying wafer counts) for the semiconductor devices fabricated utilizing polycrystalline GaN wafers (Embodiments 1 to 10) are augmented by comparison with the semiconductor device fabricated using a monocrystalline GaN wafer (Comparative Example 1), wherein it was understood that the occurrence of cracks was controlled to a minimum. The effectiveness in controlling cracking was greater with larger number n of peak-split sites in the polycrystalline GaN wafers, with the rejects due to cracking being few. Moreover, with regard to the semiconductor device yield rate also, in which the evaluation of the device properties was taken into consideration, the yield with every one of Embodiments 1 to 10 was higher than that with Comparative Example 1.
With the exception that, as a polycrystalline GaN wafer/a monocrystalline GaN wafer, crystals of 3-inch size were used, the LEDs that were Embodiment A and Comparative Example A were fabricated, and the device properties evaluated, by the same methods as for Embodiments 1 to 10 and Comparative Example 1. The results are set forth in Table II.
As is evident in Table II, the “cracking @ epi” and “cracking @ back lap” wafer counts (qualifying wafer counts) for the semiconductor devices fabricated utilizing a polycrystalline GaN wafer (Embodiment A) are augmented by comparison with the semiconductor device fabricated using a monocrystalline GaN wafer (Comparative Example A), wherein it was understood that the occurrence of cracks was controlled to a minimum. It was thereby confirmed that the crack-inhibiting effectiveness resulting from the polycrystalline GaN wafer does not depend on the wafer size.
Embodiments 11 to 20 and Comparative Example 2 are LDs being semiconductor device 120 involving Embodying Mode 6 of the present invention. The manufacturing method and testing method were as follows.
To begin with, by MOCVD, onto 2-inch size, 400-μm thick polycrystalline GaN wafers (in Comparative Example 2, a monocrystalline GaN wafer was used), as an at least single-lamina III-nitride semiconductor layer
an Si-doped, n-type GaN buffer layer of 0.05 μm thickness,
an Si-doped, n-type Al0.08Ga0.92N cladding layer of 1.0 μm thickness,
an active layer of a multiquantum-well structure in which
were repeated five times,
an undoped Al0.2Ga0.8N deterioration-preventing layer of 0.01 μm thickness,
a magnesium (Mg)-doped p-type Al0.2Ga0.8N gap layer of 10 nm thickness,
an Mg-doped p-type GaN optical waveguide layer of 0.1 μm thickness,
an Mg-doped p-type Al0.08Ga0.92N cladding layer of 0.3 μm thickness; and
an Mg-doped p-type GaN contact layer
were, in that order, grown epitaxially, after which the polycrystalline GaN wafers (as well as the monocrystalline GaN wafer) were taken out of the MOCVD reactor.
These epi-wafers were tested and screened for the presence of cracks by observation under a differential interference microscope (first-time test).
Subsequently, an SiO2 film of 0.1 μm thickness was formed by CVD across the entire p-type GaN contact layer, and then a pattern corresponding to the shape of a ridge section was lithographically formed onto the SiO2 film.
Next, with the SiO2 film as mask, a ridge extending in a <1-100> direction was formed by etching thickness-wise to a predetermined depth into the p-type AlGaN cladding layer, by the RIE method. The width of the ridge was 2 μm. A chlorine-based gas was employed as the RIE etchant gas.
Next, the SiO2 film employed as an etching mask was removed by being etched away, and then CVD was employed to deposit an SiO2 insulating film of 0.3 μm thickness across the entire wafer. Subsequently, by lithography a resist pattern was formed covering the surface of the insulating film in a region excluding the region for forming the p-electrode. Next, with the resist pattern as a mask, an opening was formed by etching the insulating film.
Following that, with the resist pattern left intact, a p-electrode was formed by vacuum deposition across the entire wafer, after which the resist was removed together with the p-electrode material where formed onto the resist pattern, to form a p-electrode on the p-type GaN contact layer alone. In order to facilitate singulating the wafers into chips, the surface of the p-type GaN layer was adhered to a polishing holder, and then a polishing process that employed a slurry containing an SiC abrasive of 30 μm mean particle diameter was carried out to bring the thickness of the GaN wafers from 400 μm down to 100 μm.
Next, an n-electrode was formed on the back side of the polycrystalline GaN wafers (as well as the monocrystalline GaN wafer). Thereafter, epi-wafer screening was conducted by observation under a differential interference microscope to test for the presence of cracks (second-time test).
Thereafter, along the contour lines of the electronic element regions, scribing on the polycrystalline GaN wafers (as well as the monocrystalline GaN wafer) onto which a laser structure had been formed as described above was carried out with cleaving, to process them into laser bars and form both cavity endfaces. Next, endface coating was implemented on the cavity endfaces, after which scribing, with cleavages, of the laser bars was again performed, rendering them into chips. By the above, LDs involving Embodiments 11 to 20 and Comparative Example 2 were fabricated, after which the device properties were tested. The results are set forth in Table III.
As is evident in Table III, the “cracking @ epi” and “cracking @ back lap” wafer counts (qualifying wafer counts) for the semiconductor devices fabricated utilizing polycrystalline GaN wafers (Embodiments 11 to 20) are augmented by comparison with the semiconductor device fabricated using a monocrystalline GaN wafer (Comparative Example 2), wherein it was understood that the occurrence of cracks was controlled to a minimum. The effectiveness in controlling cracking was greater with larger number n of peak-split sites in the polycrystalline GaN wafers, with the rejects due to cracking being few. Moreover, with regard to the semiconductor device yield rate also, in which the evaluation of the device properties was taken into consideration, the yield with every one of Embodiments 11 to 20 was higher than that with Comparative Example 2.
With the exception that, as a polycrystalline GaN wafer/a monocrystalline GaN wafer, crystals of 3-inch size were used, the LDs that were Embodiment B and Comparative Example B were fabricated, and the device properties evaluated, by the same methods as for Embodiments 11 to 20 and Comparative Example 1. The results are set forth in Table IV.
As is evident in Table IV, the “cracking @ epi” and “cracking @ back lap” wafer counts (qualifying wafer counts) for the semiconductor devices fabricated utilizing a polycrystalline GaN wafer (Embodiment B) are augmented by comparison with the semiconductor device fabricated using a monocrystalline GaN wafer (Comparative Example B), wherein it was understood that the occurrence of cracks was controlled to a minimum. It was thereby confirmed that the crack-inhibiting effectiveness resulting from the polycrystalline GaN wafer does not depend on the wafer size.
Embodiments 21 to 30 and Comparative Example 3 are HEMTs being semiconductor device 130 involving Embodying Mode 7 of the present invention. The manufacturing method and testing method were as follows.
By MOCVD, a 3-μm thick i-type GaN layer and a 30-nm thick i-type Al0.15Ga0.85N layer were grown as an at least single-lamina III-nitride semiconductor layer onto a 2-inch size, 400-μm thick polycrystalline GaN wafer (in Comparative Example 3, a monocrystalline GaN wafer was used).
Epi-wafer screening was conducted by observation under a differential interference microscope to test for the presence of cracks (first-time test).
Next, by photolithographic and lift-off processes, onto the i-type Al0.15Ga0.85N layer as a source electrode and a drain electrode, respective Ti layer (50 nm thickness)/Al layer (100 nm thickness)/Ti layer (20 nm thickness)/Au layer (200 nm thickness) laminar composites were formed by heating the layers at 800° C. for 30 seconds to alloy them. Further, an Au layer of 300 nm thickness was formed as a gate electrode. The gate length was 2 μm, and the gate width, 150 μm.
In order to facilitate singulating the wafers into chips, the surface of the p-type GaN layer was adhered to a polishing holder, and then a polishing process that employed a slurry containing an SiC abrasive of 30 μm mean particle diameter was carried out to bring the thickness of the polycrystalline GaN wafers (as well as the monocrystalline GaN wafer) from 400 μm down to 100 μm. Epi-wafer screening was conducted by observation under a differential interference microscope to test for the presence of cracks (second-time test).
Following that, the semiconductors constituted by the above-described polycrystalline GaN wafers (as well as the monocrystalline GaN wafer) and III-nitride semiconductor layers were singulated into individual 400 μm×400 μm chips. By the above, HEMTs involving Embodiments 21 to 30 and Comparative Example 3 were fabricated, after which the device properties were tested. The results are set forth in Table V.
As is evident in Table V, the “cracking @ epi” and “cracking @ back lap” wafer counts (qualifying wafer counts) for the semiconductor devices fabricated utilizing polycrystalline GaN wafers (Embodiments 21 to 30) are augmented by comparison with the semiconductor device fabricated using a monocrystalline GaN wafer (Comparative Example 3), wherein it was understood that the occurrence of cracks was controlled to a minimum. The effectiveness in controlling cracking was greater with larger number n of peak-split sites in the polycrystalline GaN wafers, with the rejects due to cracking being few. Moreover, with regard to the semiconductor device yield rate also, in which the evaluation of the device properties was taken into consideration, the yield with every one of Embodiments 21 to 30 was higher than that with Comparative Example 3.
With the exception that, as a polycrystalline GaN wafer/a monocrystalline GaN wafer, crystals of 3-inch size were used, the HEMTs that were Embodiment C and Comparative Example C were fabricated, and the device properties evaluated, by the same methods as for Embodiments 21 to 30 and Comparative Example 3. The results are set forth in Table VI.
As is evident in Table VI, the “cracking @ epi” and “cracking @ back lap” wafer counts (qualifying wafer counts) for the semiconductor device fabricated utilizing a polycrystalline GaN wafer (Embodiment C) are augmented by comparison with the semiconductor device fabricated using a monocrystalline GaN wafer (Comparative Example C), wherein it was understood that the occurrence of cracks was controlled to a minimum. It was thereby confirmed that the crack-inhibiting effectiveness resulting from the polycrystalline GaN wafer does not depend on the wafer size.
Embodiments 31 to 40 and Comparative Example 4 are Schottky diodes being semiconductor device 140 involving Embodying Mode 8 of the present invention. The manufacturing method and testing method were as follows.
By MOCVD, an n−-type GaN layer (whose electron density was 1×1016 cm−3) of 5 μm thickness was grown as an at least single-lamina III-nitride semiconductor layer onto a 2-inch size, 400-μm thick polycrystalline GaN wafer (in Comparative Example 4, a monocrystalline GaN wafer was used). Epi-wafer screening was conducted by observing the wafers under a differential interference microscope to test for the presence of cracks (first-time test).
Next, as an ohmic electrode across the entire back side of the polycrystallineline GaN wafers (as well as monocrystalline GaN wafer), a Ti layer (50 nm thickness)/Al layer (100 nm thickness)/Ti layer (20 nm thickness)/Au layer (200 nm thickness) laminar composite was formed by heating the layers at 800° C. for 30 seconds to alloy them. Furthermore, by photolithographic and lift-off processes, an Au layer of diameter 200 μm×thickness 300 nm was formed onto the n−-type GaN layer as a Schottky electrode.
In order to facilitate singulating the wafers into chips, the surface of the p-type GaN layer was adhered to a polishing holder, and then a polishing process that employed a slurry containing an SiC abrasive of 30 μm mean particle diameter was carried out to bring the thickness of the polycrystalline GaN wafers (as well as the monocrystalline GaN wafer) from 400 μm down to 100 μm. Thereafter epi-wafer screening was conducted by observation under a differential interference microscope to test for the presence of cracks (second-time test).
Following that, the semiconductors constituted by the above-described polycrystalline GaN wafers (as well as the monocrystalline GaN wafer) and III-nitride semiconductor layers were singulated into individual 400 μm×400 μm chips. By the above, Schottky diodes involving Embodiments 31 to 40 and Comparative Example 4 were fabricated, after which the device properties were tested. The results are set forth in Table VII.
As is evident in Table VII, the “cracking @ epi” and “cracking @ back lap” wafer counts (qualifying wafer counts) for the semiconductor devices fabricated utilizing polycrystalline GaN wafers (Embodiments 31 to 40) are augmented by comparison with the semiconductor device fabricated using a monocrystalline GaN wafer (Comparative Example 4), wherein it was understood that the occurrence of cracks was controlled to a minimum. The effectiveness in controlling cracking was greater with larger number n of peak-split sites in the polycrystalline GaN wafers, with the rejects due to cracking being few. Moreover, with regard to the semiconductor device yield rate also, in which the evaluation of the device properties was taken into consideration, the yield with every one of Embodiments 31 to 40 was higher than that with Comparative Example 4.
With the exception that, as a polycrystalline GaN wafer/a monocrystalline GaN wafer, crystals of 3-inch size were used, the Schottky diodes that were Embodiment D and Comparative Example D were fabricated, and the device properties evaluated, by the same methods as for Embodiments 31 to 40 and Comparative Example 4. The results are set forth in Table VIII.
As is evident in Table VIII, the “cracking @ epi” and “cracking @ back lap” wafer counts (qualifying wafer counts) for the semiconductor device fabricated utilizing a polycrystalline GaN wafer (Embodiment D) are augmented by comparison with the semiconductor device fabricated using a monocrystalline GaN wafer (Comparative Example D), wherein it was understood that the occurrence of cracks was controlled to a minimum. It was thereby confirmed that the crack-inhibiting effectiveness resulting from the polycrystalline GaN wafer does not depend on the wafer size.
Embodiments 41 to 50 and Comparative Example 5 are vertical MIS transistors being semiconductor device 150 involving Embodying Mode 9 of the present invention. The manufacturing method and testing method were as follows.
By MOCVD, an n−-type GaN layer (whose electron density was 1×1016 cm−3) of 5 μm thickness was grown as an at least single-lamina III-nitride semiconductor layer onto a 2-inch size, 400-μm thick polycrystalline GaN wafer (in Comparative Example 5, a monocrystalline GaN wafer was used). Epi-wafer screening was conducted by observing the wafers under a differential interference microscope to test for the presence of cracks (first-time test).
Next, by implantation of select ions, a p-type GaN layer and an n+-type GaN layer were formed. Herein, the p-type GaN layer was formed by Mg-ion implantation, while the n+-type GaN layer was formed by Si-ion implantation. Next, a 300-nm thick SiO2 film was formed as a protective film on the III-nitride semiconductor layer, which was then annealed at 1250° C. for 30 seconds to activate the implanted ions. Following that the aforedescribed protective film was stripped off with hydrofluoric acid, and then an SiO2 film of 50 nm thickness was formed by plasma-enhanced chemical vapor deposition (P-CVD) as an MIS insulating film.
Next, by a photolithographic process and a select etching process employing buffered hydrofluoric acid, a portion of the aforementioned MIS insulating film was etched, and by a lift-off process, onto the etched region as a source electrode a Ti layer (50 nm thickness)/Al layer (100 nm thickness)/Ti layer (20 nm thickness)/Au layer (200 nm thickness) laminar composite was formed by heating the layers at 800° C. for 30 seconds to alloy them. Following that, by photolithographic and lift-off processes an Al layer of 300 nm thickness was formed as a gate electrode onto the MIS insulating film, creating an MIS structure.
In order to facilitate singulating the wafers into chips, the surface of the p-type GaN layer was adhered to a polishing holder, and then a polishing process that employed a slurry containing an SiC abrasive of 30 μm mean particle diameter was carried out to bring the thickness of the polycrystalline GaN wafers (as well as the monocrystalline GaN wafer) from 400 μm down to 100 μm. Thereafter epi-wafer screening was conducted by observation under a differential interference microscope to test for the presence of cracks (second-time test).
Next, the semiconductors constituted by the above-described polycrystalline GaN wafers (as well as the monocrystalline GaN wafer) and III-nitride semiconductor layers were singulated into individual 400 μm×400 μm chips. Across the entire back side of each singulated chip's polycrystalline GaN wafer (monocrystalline GaN wafer), as a drain electrode a Ti layer (50 nm thickness)/Al layer (100 nm thickness)/Ti layer (20 nm thickness)/Au layer (200 nm thickness) laminar composite was formed by heating the layers at 800° C. for 30 seconds to alloy them. By the above, vertical MIS transistors involving Embodiments 41 to 50 and Comparative Example 5 were fabricated, after which the device properties were tested. The results are set forth in Table IX.
As is evident in Table IX, the “cracking @ epi” and “cracking @ back lap” wafer counts (qualifying wafer counts) for the semiconductor devices fabricated utilizing polycrystalline GaN wafers (Embodiments 41 to 50) are augmented by comparison with the semiconductor device fabricated using a monocrystalline GaN wafer (Comparative Example 5), wherein it was understood that the occurrence of cracks was controlled to a minimum. The effectiveness in controlling cracking was greater with larger number n of peak-split sites in the polycrystalline GaN wafers, with the rejects due to cracking being few. Moreover, with regard to the semiconductor device yield rate also, in which the evaluation of the device properties was taken into consideration, the yield with every one of Embodiments 41 to 50 was higher than that with Comparative Example 5.
With the exception that, as a polycrystalline GaN wafer/a monocrystalline GaN wafer, crystals of 3-inch size were used, the vertical MIS transistors that were Embodiment E and Comparative Example E were fabricated, and the device properties evaluated, by the same methods as for Embodiments 41 to 50 and Comparative Example 5. The results are set forth in Table X.
As is evident in Table X, the “cracking @ epi” and “cracking @ back lap” wafer counts (qualifying wafer counts) for the semiconductor device fabricated utilizing a polycrystalline GaN wafer (Embodiment E) are augmented by comparison with the semiconductor device fabricated using a monocrystalline GaN wafer (Comparative Example E), wherein it was understood that the occurrence of cracks was controlled to a minimum. It was thereby confirmed that the crack-inhibiting effectiveness resulting from the polycrystalline GaN wafer does not depend on the wafer size.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2007-261198 | Oct 2007 | JP | national |
| Filing Document | Filing Date | Country | Kind | 371c Date |
|---|---|---|---|---|
| PCT/JP2008/066945 | 9/19/2008 | WO | 00 | 6/12/2009 |
