Claims
- 1. A method comprising:placing a socket on a printed circuit board (PCB), the socket comprising an array of first contacts and a set of second contacts having a greater conductive cross-sectional area than the first contacts, wherein the greater conductive cross-sectional area of each contact of the set of second contacts is coplanar with each contact of the set of first contacts; aligning a plurality of solder balls attached to a bottom surface of each second contact with a set of solder pads on the PCB corresponding to the set of second contacts, each of the contacts of the set of second contacts formed to provide a pressure contact with respective corresponding solder pads of the set of solder pads solder pads on the PCB, the pressure contact of each of the contacts of the set of second contacts occurring on the greater conductive cross-sectional area to provide greater power delivery; and reflowing the plurality of solder balls to electrically couple the set of second contacts with the corresponding set of solder pads.
- 2. The method of claim 1, wherein the plurality of solder balls flow together upon reflow to form a single solder interconnection between each second contact and a corresponding solder pad.
- 3. The method of claim 1, wherein the plurality of solder balls are attached to a bottom surface of each second contact with a narrower pitch than the array of first contacts.
- 4. The method of claim 1, wherein the array of first contacts has a pitch of 0.040 inches or less and the solder balls are attached to a bottom surface of each second contact with a pitch of 0.030 inches or less.
- 5. The method of claim 1, further comprising mounting a land grid array (LGA) component in the socket.
- 6. The method of claim 5, wherein the LGA component is a processor and the array of first contacts engages a corresponding array of signal land pads on a bottom surface of the processor and the set of second contacts engages a set of power delivery land pads on the bottom surface of the processor.
Parent Case Info
This is a Divisional application of Ser. No.: 10/106,283 filed Mar. 26, 2002, which is presently pending.
US Referenced Citations (10)
Non-Patent Literature Citations (2)
Entry |
“Xilinx Fine-Pitch BGA and CSP Packages: The Technology Edge”, Tech Topics Virtex, Mar. 3, 2000, pp. 1-7. |
“System Design Considerations When Designing with Intel Flash”, Intel Application Note 751, Jan. 2002, pp. 1-9. |