Semiconductor devices are used in a variety of electronic applications, such as, for example, personal computers, cell phones, digital cameras, and other electronic equipment. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of material over a semiconductor substrate, and patterning the various material layers using lithography to form circuit components and elements thereon.
The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continual reductions in minimum feature size, which allow more components to be integrated into a given area.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 230 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. As used herein, “around,” “about,” “approximately,” or “substantially” may generally mean within 20 percent, or within 10 percent, or within 5 percent of a given value or range. Numerical quantities given herein are approximate, meaning that the term “around,” “about,” “approximately,” or “substantially” can be inferred if not expressly stated.
The present disclosure is generally related to integrated circuit (IC) structures and methods of forming the same, and more particularly to fabricating gate-all-around (GAA) transistors having fish-bone structures or fork-sheet structures. It is also noted that the present disclosure presents embodiments in the form of multi-gate transistors. Multi-gate transistors include those transistors whose gate structures are formed on at least two-sides of a channel region. These multi-gate devices may include a p-type metal-oxide-semiconductor device or an n-type metal-oxide-semiconductor device. Specific examples may be presented and referred to herein as fin field effect transistors (FinFET), on account of their fin-like structure. Also presented herein are embodiments of a type of multi-gate transistor referred to as a gate-all-around (GAA) device. A GAA device includes any device that has its gate structure, or portion thereof, formed on 4-sides of a channel region (e.g., surrounding a portion of a channel region). Devices presented herein also include embodiments that have channel regions disposed in nanosheet channel(s), nanowire channel(s), and/or other suitable channel configuration. Presented herein are embodiments of devices that may have one or more channel regions (e.g., nanosheets) associated with a single, contiguous gate structure. However, one of ordinary skill would recognize that the teaching can apply to a single channel (e.g., single nanosheet) or any number of channels. One of ordinary skill may recognize other examples of semiconductor devices that may benefit from aspects of the present disclosure.
The gate all around (GAA) transistor structures may be patterned by any suitable method. For example, the structures may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the GAA structure.
As scales of the fin width in fin field effect transistors (FinFET) decreases, channel width variations might cause mobility loss. GAA transistors, such as nanosheet transistors are being studied as an alternative to fin field effect transistors. In a nanosheet transistor, the gate of the transistor is made all around the channel (e.g., a nanosheet channel or a nanowire channel) such that the channel is surrounded or encapsulated by the gate. Such a transistor has the advantage of improving the electrostatic control of the channel by the gate, which also mitigates leakage currents.
The present disclosure provides a GAA transistor including a fork-sheet structure to allow n-type devices and p-type devices to be formed close to one another. One aspect of embodiments of the present disclosure provides an improved thickness design flexibility for the p-type work function metal. A threshold voltage shift or a localized threshold voltage mismatch issue caused by merging of the p-type work function metal along the x-axis can be prevented. An enlarged process window along the x-axis during formation of the n-type work function layer can thus be provided.
Some embodiments discussed herein are discussed in the context of GAA-FETs formed using a gate-last process. In other embodiments, a gate-first process may be used. Also, some embodiments contemplate aspects used in planar devices, such as planar FETs or in fin field-effect transistors (FinFETs).
In
The substrate 100 has n-type regions 1001 and a p-type region 1002. The n-type regions 1001 are regions in which n-channel metal-oxide-semiconductor (NMOS) transistors, e.g., n-type GAA-FETs will reside, and the p-type region 1002 is a region in which p-type devices, such as p-channel metal-oxide-semiconductor (PMOS) transistors, e.g., p-type GAA-FETs will reside. In some embodiments, the first transistors are different from the second transistors at least in threshold voltage. For example, first transistors in the n-type regions 1001 may be High Voltage (HV) devices (e.g., I/O devices), and second transistors in the p-type region 1002 may be Low Voltage (LV) devices (e.g., logic devices).
The n-type regions 1001 may be separated from the p-type region 1002, and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) may be disposed between the n-type regions 1001 and the p-type region 1002. Although two n-type regions 1001 and one p-type region 1002 are illustrated, any number of the n-type regions 1001 and the p-type region 1002 may be provided.
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The first semiconductor layers 104 and the second semiconductor layers 106 may include one or more layers of Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb or InP. In some embodiments, the first semiconductor layers 104 and the second semiconductor layers 106 are made of Si, a Si compound, SiGe, Ge or a Ge compound. The first semiconductor layers 104 include a first composition and the second semiconductor layers 106 include a second composition different from the first composition. The first and second compositions have different oxidation rates and/or etch selectivity. For example, the first semiconductor layers 104 may include SiGe and the second semiconductor layers 106 may include Si.
The multi-layer stack 102 is illustrated as including four layers of the first semiconductor layers 104 and three layers of the second semiconductor layers 106 for illustrative purposes. In some embodiments, the multi-layer stack 102 may include any number of the first semiconductor layers 104 and the second semiconductor layers 106. Each of the layers of the multi-layer stack 102 may be epitaxially grown using a process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam cpitaxy (MBE), or the like. In various embodiments, the second semiconductor layers 106 may be formed of a semiconductor material suitable for serving as channel regions of GAA-FETs, such as silicon, silicon carbon, silicon germanium, or the like.
The first semiconductor materials and the second semiconductor materials may be materials having a high-etch selectivity to one another. As such, the first semiconductor layers 104 of the first semiconductor material may be removed without significantly removing the second semiconductor layers 106 of the second semiconductor material, thereby allowing the second semiconductor layers 106 to serve as channel regions of GAA-FETs. The topmost first semiconductor layer 104a is thicker than other first semiconductor layers 104. For example, the topmost first semiconductor layer 104a has a thickness T2 greater than a thickness T1 of a bottommost first semiconductor layers 104b. By the topmost first semiconductor layer 104a being thicker than other first semiconductor layers 104, a subsequent dielectric fin can have an increased thickness.
A Pad layer 108a and a mask layer 108b may be formed on the multi-layer stack 102. The pad layer 108a may be a thin film comprising silicon oxide formed, for example, using a thermal oxidation process. The pad layer 108a may act as an adhesion layer between multi-layer stack 102 and the mask layer 108b. The pad layer 108a may also act as an etch stop layer for etching the mask layer 108b. In an embodiment, the mask layer 108b is formed of silicon nitride, for example, using low-pressure chemical vapor deposition (LPCVD). In other embodiments, the mask layer 108b is formed by thermal nitridation of silicon, plasma enhanced chemical vapor deposition (PECVD), or plasma anodic nitridation. The mask layer 108b is used as a hard mask during subsequent photolithography processes. A photo resist 110 is formed on the mask layer 108b and is then patterned, forming openings 112 in the photo resist 110.
The mask layer 108b and the pad layer 108a are etched through the openings 112 to expose the underlying multi-layer stack 102. The photo resist 110 is removed. The exposed multi-layer stack 102 and the underlying substrate 100 are then etched to form trenches 118a, 118b, 118c, 118d in the multi-layer stack 102 and the substrate 100 using the mask layer 108b and the pad layer 108a as an etch mask. Fin structures 114 are formed in the substrate 100 and nanostructures 116 are formed in the multi-layer stack 102, in accordance with some embodiments, as shown in
The fin structures 114 and the nanostructures 116 may be patterned by any suitable method. For example, the fin structures 114 and the nanostructures 116 may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fin structures 114 and the nanostructures 116.
The process described above with respect to
Additionally, the first semiconductor layers (and resulting nanostructures 122) and the second semiconductor layers (and resulting nanostructures 124) are illustrated and discussed herein as comprising the same materials in the p-type region 1002 and the n-type region 1001 for illustrative purposes only. As such, in some embodiments one or both of the first semiconductor layers and the second semiconductor layers may be different materials or formed in a different order in the n-type and p-type regions 1001 and 1002.
In some embodiments, the fin 120N in the n-type region 1001 and the fin 120P in the p-type region 1002 have a first spacing S1, and the two neighboring fins 120P in the p-type region 1002 have a second spacing S2. The second spacing S2 is greater than the first spacing S1. In other words, the trench 118c is wider than the trenches 118b and 118d.
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In an embodiment, the insulation material 134 is formed such that excess insulation material 134 covers the fins 120. In some embodiments, a liner (not shown) is first formed along surfaces of the substrate 100 and the fins 120, and a fill material, such as those discussed above is formed over the liner. In some embodiments, the liner is omitted. Next, a removal process is applied to the insulation material 134 to remove excess insulation material 134 over the fins 120. The mask layer 108b and the pad layer 108a are removed by the removal process. In some embodiments, a planarization process such as a chemical mechanical polish (CMP), an etch back process, combinations thereof, or the like may be utilized. The planarization process exposes the nanostructures 116 such that top surfaces of the nanostructures 116 and the insulation material 134 are level after the planarization process is complete.
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The gate structure 140 is formed by deposition processes, lithography processes, etching processes, other suitable processes, or combinations thereof. For example, a deposition process is performed to form a dummy gate electrode layer over the substrate 100, particularly over the fins 120 and the STI regions 134a. In some implementations, a deposition process is performed to form a dummy gate dielectric layer over the fins 120 before forming the dummy gate electrode layer, where the dummy gate electrode layer is formed over the dummy gate dielectric layer. The deposition process includes CVD, physical vapor deposition (PVD), atomic layer deposition (ALD), high density plasma CVD (HDPCVD), metal organic CVD (MOCVD), remote plasma CVD (RPCVD), plasma enhanced CVD (PECVD), low-pressure CVD (LPCVD), atomic layer CVD (ALCVD), atmospheric pressure CVD (APCVD), plating, other suitable methods, or combinations thereof. A lithography patterning and etching process is then performed to pattern the dummy gate electrode layer (and, in some implementations, the dummy gate dielectric layer) to form the dummy gate stack 145, such that the dummy gate stack 145 (including the dummy gate electrode 144, the dummy gate dielectric 142, and/or other suitable layers) wraps a portion of channel region. The lithography patterning processes include resist coating (for example, spin-on coating), soft baking, mask aligning, exposure, post-exposure baking, developing the resist, rinsing, drying (for example, hard baking), other suitable processes, or combinations thereof. Alternatively, the lithography exposing process is assisted, implemented, or replaced by other methods, such as maskless lithography, electron-beam writing, or ion-beam writing. In yet another alternative, the lithography patterning process implements nanoimprint technology. The etching processes include dry etching processes, wet etching processes, other etching methods, or combinations thereof.
Gate spacers 148 are formed adjacent to the dummy gate stack 145 of the gate structure 140. Fin spacers 150 are formed on tops of the STI regions 134a. For example, the gate spacers 148 are disposed adjacent to (for example, along sidewalls of) the dummy gate electrode 144. The gate spacers 148 and the fin spacers 150 are formed by any suitable process and include a dielectric material. The dielectric material can include silicon, oxygen, carbon, nitrogen, other suitable material, or combinations thereof (for example, silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide). For example, in the depicted embodiment, a dielectric layer including silicon and nitrogen, such as a silicon nitride layer, can be deposited over the fins 120 and the STI regions 134a and subsequently anisotropically etched to form the gate spacers 148 and the fin spacers 150. In some implementations, the fin spacers 150 and the gate spacers 148 include a multi-layer structure, such as a first dielectric layer that includes silicon nitride and a second dielectric layer that includes silicon oxide. In some implementations, more than one set of spacers, such as seal spacers, offset spacers, sacrificial spacers, dummy spacers, and/or main spacers, are formed adjacent to the dummy gate stack 145. In such implementations, the various sets of spacers can include materials having different etch rates. For example, a first dielectric layer including silicon and oxygen (for example, silicon oxide) can be deposited over the fins 120 and the STI regions 134a and subsequently anisotropically etched to form a first spacer set adjacent to the dummy gate stack 145 and on the STI regions 134a, and a second dielectric layer including silicon and nitrogen (for example, silicon nitride) can be deposited over the fins 120 and the STI regions 134a and subsequently anisotropically etched to form a second spacer set adjacent to the first spacer set.
Source/drain recesses 152 are formed in the nanostructures 116 and the substrate 100, in accordance with some embodiments. Epitaxial source/drain regions will be subsequently formed in the source/drain recesses 152. The source/drain recesses 152 may extend through the first nanostructures 122 and the second nanostructures 124, and into the substrate 100. Bottom surfaces of the source/drain recesses 152 are lower than top surfaces of the STI regions 134a, as an example. In some other embodiments, the fin structures 114 may be etched such that bottom surfaces of the source/drain recesses 152 are level with the top surfaces of the STI regions 134a. The source/drain recesses 152 may be formed by etching the nanostructures 116 and the substrate 100 using anisotropic etching processes, such as RIE, NBE, or the like. The gate spacers 148 and the mask layer 146b protect portions of the fin structures 114, the nanostructures 116, and the substrate 100 during the etching processes used to form the source/drain recesses 152. A single etch process or multiple etch processes may be used to etch each layer of the nanostructures 116 and/or the fin structures 114. Timed etch processes may be used to stop the etching of the source/drain recesses 152 after the source/drain recesses 152 reach a target depth.
A recessing process (e.g., etch back process) is performed to remove a portion of the dielectric fin 132 so that the dielectric fin 132 has a reduced height H1. A vertical distance between a top surface of the fin spacers 150 and a top surface of the recessed fin structure 114 is substantially the same as a distance between a top surface of the recessed dielectric fin 132 and the top surface of the recessed fin structure 114. In other words, the top surfaces of the dielectric fin 132 and the fin spacers 150 are at the same level heights.
Portions of sidewalls of the layers of the nanostructures 116 formed of the first semiconductor materials (e.g., the first nanostructures 122) exposed by the source/drain recesses 152 are etched to form sidewall recesses between corresponding second nanostructures 124. Although sidewalls of the first nanostructures 122 in recesses are illustrated as being straight in
Inner spacers 154 are formed in the sidewall recess, as shown in
The inner spacers 154 may be formed by depositing an inner spacer layer using conformal deposition process, such as CVD, ALD, or the like. The inner spacer layer may include a material such as silicon nitride or silicon oxynitride, although any suitable material, such as low-dielectric constant (low-k) materials having a k-value less than about 3.5, may be utilized. The inner spacer layer may then be anisotropically etched to form the inner spacers 154. Although outer sidewalls of the inner spacers 154 are illustrated as being flush with sidewalls of the second nanostructures 124, the outer sidewalls of the inner spacers 154 may extend beyond or be recessed from sidewalls of the second nanostructures 124.
Moreover, although the outer sidewalls of the inner spacers 154 are illustrated as being straight in
In some embodiments, the epitaxial source/drain regions 158 may include any acceptable material appropriate for n-type GAA-FETs. For example, if the second nanostructures 124 are silicon, the epitaxial source/drain regions 232 may include materials exerting a tensile strain on the second nanostructures 204, such as silicon carbide, phosphorous doped silicon carbide, silicon phosphide, or the like. In some embodiments, the epitaxial source/drain regions 158 may include any acceptable material appropriate for p-type GAA-FETs. For example, if the second nanostructures 124 are silicon, the epitaxial source/drain regions 158 may include materials exerting a compressive strain on the second nanostructures 124, such as silicon germanium, boron doped silicon germanium, germanium, germanium tin, or the like. The epitaxial source/drain regions 158 may have surfaces raised from respective upper surfaces of the nanostructures 116 and may have facets.
The epitaxial source/drain regions 158 may be implanted with dopants to form source/drain regions, followed by an anneal. The n-type and/or p-type impurities for source/drain regions 158 may be any of the impurities previously discussed. In some embodiments, the epitaxial source/drain regions 158 may be in situ doped during growth.
As a result of the epitaxy processes used to form the epitaxial source/drain regions 158, upper surfaces of the epitaxial source/drain regions 158 have facets which expand laterally outward beyond sidewalls of the nanostructures 116. In some other embodiments, adjacent epitaxial source/drain regions 158 remain separated after the epitaxy process is completed as illustrated by
In
A planarization process, such as a CMP, may be performed to remove the hard mask including the pad layer 146a and the mask layer 146b on the dummy gate electrode 144. The planarization process levels the top surface of the ILD layer 160 with the top surfaces of dummy gate electrode 144 (see
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The gate spacers 148 are separated in the x-axis.
The first nanostructures 122 in the gate trenches 164 are then removed by an isotropic etching process such as wet etching or the like using etchants which are selective to the materials of the first nanostructures 122. Stated differently, the first nanostructures 122 are removed by using a selective etching process that etches the first nanostructures 122 at a faster etch rate than it etches the second nanostructures 124, thus forming spaces between the second nanostructures 124 (also referred to as sheet-sheet spaces if the nanostructures 124 are nanosheets). This step can be referred to as a channel release process. As illustrated in
In embodiments in which the first nanostructures 122 include, e.g., SiGe, and the second nanostructures 124 include, e.g., Si or SiC, tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH) or the like may be used to remove the first nanostructures 122. In some embodiments, both the channel release step and the previous step of laterally recessing first nanostructures 122 (i.e., the step as illustrated in
The first dielectric film 126 exposed by the gaps 166 are removed such that the second dielectric film 128 is exposed by the gaps 166. The first dielectric film 126 can be removed by an isotropic etching process such as wet etching or the like using etchants which are selective to the materials of the first dielectric film 126. Stated differently, the first dielectric film 126 are removed by using a selective etching process that etches the first dielectric film 126 at a faster etch rate than it etches the second dielectric film 128.
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In an alternative embodiment, an interfacial layer 170 is deposited between the gate dielectric layer 172 and the second nanostructures 124 and is formed of silicon oxide or silicon oxynitride grown by a thermal oxidation process. For example, the interfacial layer 170 can be grown by a rapid thermal oxidation (RTO) process or by an annealing process using oxygen.
In
In some embodiments, before the formation of the first p-type work function layer 174, a growth control layer 173 is formed on side surfaces of the gate trench 164 but not on a bottom surface of the gate trench 164. In some embodiments, a patterned photoresist layer (not shown) is formed on the substrate 100, exposing the gate trench 164, and then the growth control layer 173 is formed on the gate trench 164. The growth control layer 173 extends to the bottom surface of the gate trench 164 while the growth control layer 173 may cover only a topmost portion (see
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The reduced thickness T4 is small enough such that the second p-type work function layer 180 would not merge in the gate trench 164, allowing for a subsequent n-type work function layer formed into the gate trench 164. Therefore, a process window along the x-axis is enlarged during formation of the subsequent n-type work function layer. Therefore, a threshold voltage shift or a localized threshold voltage mismatch issue caused by merging of the second p-type work function layer 180 along the x-axis can be prevented, which is beneficial for controlling a uniformity of a local threshold voltage. The p-type work function metal thus has an improved thickness design flexibility. The second p-type work function layer 180 has the thickness T4 less than the vertical distance between the second nanostructures 124. For example, the thickness T4 can be less than the sheet-to-sheet spacing Z1 (see
In some embodiments, the second p-type work function layer 180 includes a p-type work function metal (P-metal). The p-type work function metal may exemplarily include, but are not limited to, titanium nitride (TiN), tungsten nitride (WN), tungsten (W), ruthenium (Ru), palladium (Pd), platinum (Pt), cobalt (Co), nickel (Ni), conductive metal oxides, and/or other suitable materials.
Depending on a desired threshold voltage for the high-k/metal gate structure in the p-type region 1002, the first p-type work function layer 174 can have a material same as or different from a material of the second p-type work function layer 180. In some embodiments, the second p-type work function layer 180 includes the material same as the material of the first p-type work function layer 174. In some other embodiments, the second p-type work function layer 180 includes the material different from the material of the first p-type work function layer 174. As discussed previously, the first p-type work function layer 174 (see
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After the patterned photoresist layer 182 is formed, the exposed second p-type work function layer 180 in the n-type region 1001 and the underlying first p-type work function layer 174 are removed by using the patterned photoresist layer 182 as an etch mask, so that the gate dielectric layer 172 is exposed in the n-type region 1001. In some embodiments, the second p-type work function layer 180 and the first p-type work function layer 174 are removed by a plasma dry etching using fluorine-based and/or chlorine-based etchants. For example, the second p-type work function layer 180 and the first p-type work function layer 174 may be removed by a wet etching process using an etchant that is selective to the material of the gate dielectric layer 172. Stated differently, the etchant used in removing the second p-type work function layer 180 and the first p-type work function layer 174 etches the material of the second p-type work function layer and the first p-type work function layer 174 at a faster etch rate than etching the material of the gate dielectric layer 172. The resulting structure is shown in
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In
In some embodiments, the fill metal 186 may exemplarily include, but are not limited to, tungsten, aluminum, copper, nickel, cobalt, titanium, tantalum, titanium nitride, tantalum nitride, nickel silicide, cobalt silicide, TaC, TaSiN, TaCN, TiAl, TiAlN, or other suitable materials. Additional processing may be performed to finish fabrication of the device, as one of ordinary skill readily appreciates, thus details may not be repeated here. For example, another inter-layer dielectric (ILD) may be deposited over the ILD layer 160. Further, gate contacts and source/drain contacts may be formed extending through the additional ILD and/or the ILD layer 160 to electrically couple to the gate stacks 188a, 188b and the epitaxial source/drain regions 158 (see
Based on the above discussions, it can be seen that the present disclosure in various embodiments offers advantages. It is understood, however, that other embodiments may offer additional advantages, and not all advantages are necessarily disclosed herein, and that no particular advantage is required for all embodiments. One advantage is that by forming the bottom anti-reflective coating on the fork-sheet structure followed by the anisotropic etch process and the isotropic etch process, the portion of the first p-type work function layer in the gate trench can be removed while the portion of the p-type work function layer in the sheet-to-sheet spacing remains. Another advantage is that a threshold voltage shift or a localized threshold voltage mismatch issue caused by merging of the second p-type work function layer along the x-axis can be prevented, which is beneficial for controlling a uniformity of a local threshold voltage. Yet another advantage is that the process window along the x-axis is enlarged during formation of the n-type work function layer.
In some embodiments, a semiconductor device includes a plurality of nanostructures over a substrate arranged in a z-axis and a gate stack wrapping around the plurality of nanostructures. Thea gate stack comprises a gate dielectric layer and a p-type work function material on the gate dielectric layer. The gate dielectric layer wraps around the plurality of nanostructures. The p-type work function material has a first thickness along the z-axis above a topmost one of the plurality of nanostructures and a second thickness along the z-axis between neighboring two of the plurality of nanostructures, and the first thickness is less than the second thickness. In some embodiments, the semiconductor device further comprises gate spacers on opposite sides of the gate stack. The gate spacers are separated in an x-axis perpendicular to the z-axis, the p-type work function material has a portion between the gate spacers with a third thickness along the z-axis, and the third thickness is less than the second thickness. In some embodiments, the p-type work function material between the neighboring two of the plurality of nanostructure comprises a first p-type work function layer and a second p-type work function layer on the first p-type work function layer. In some embodiments, the p-type work function material above the topmost one of the plurality of nanostructures is free of the first p-type work function layer. In some embodiments, in a y-axis perpendicular to the x-axis, the plurality of nanostructures each have a width greater than a width of the first p-type work function layer. In some embodiments, the second p-type work function layer has a material different from a material of the first p-type work function layer.
In some embodiments, a method of forming a semiconductor device includes the following steps. Fins are formed protruding from a substrate. Each of the fins has alternating stacked first nanostructures and second nanostructures. A dielectric fin is formed on a first side of one of the fins. An insulation material is formed on a second side of the one of the fins opposite to the first side. The first nanostructures are removed to form gaps each between adjacent two of the second nanostructures. A first p-type work function layer is formed continuously extending across the gaps. The first p-type work function layer is etched to break the first p-type work function layer into separate first p-type work function sublayers respectively confined within the gaps. A second p-type work function layer is formed across the first p-type work function sublayers. In some embodiments, the method further includes forming a bottom anti-reflection coating (BARC) layer on the first p-type work function layer and etching back the BARC layer to expose the first p-type work function layer, while leaving portions of the BARC layer within the gaps. In some embodiments, etching the first p-type work function layer is performed using an isotropic etch process after etching back the BARC layer. In some embodiments, the method further comprises after performing the isotropic etch process, removing the BARC layer. In some embodiments, the isotropic etch process removes portions of the first p-type work function layer from sidewalls of the second nanostructures. In some embodiments, the isotropic etch process removes a portion of the first p-type work function layer from a top surface of the insulation material. In some embodiments, the isotropic etch process removes a portion of the first p-type work function layer from a top surface of the dielectric fin. In some embodiments, the method further comprises forming one or more n-type work function layers over the second p-type work function layer.
In some embodiments, a method of forming a semiconductor device comprises the following steps. A fin structure is formed extruding from a substrate. The fin structure comprises first semiconductor layers and second semiconductor layers alternately stacked. A dummy gate structure is formed over the fin structure. The dummy gate structure is removed to form a gate trench. The first semiconductor layers are etched in the gate trench. A gate dielectric layer is deposited in the gate trench. The gate dielectric layer wraps around the second semiconductor layers. A deposition process is performed to form a first p-type work function layer in the gate trench. The first p-type work function layer is removed in the gate trench. After removing the first p-type work function layer, a second p-type work function layer is formed in the gate trench. A n-type work function layer is formed in the gate trench. In some embodiments, the first p-type work function layer has a thickness less than a half of a vertical distance between the second semiconductor layers. In some embodiments, the second p-type work function layer has a thickness less than a half of a vertical distance between the second semiconductor layers. In some embodiments, the method further comprises the following steps. Prior to removing the first p-type work function layer, an organic material is formed filling the gate trench and between the two neighboring second semiconductor layers. An etch process is performed to remove the organic material in the gate trench. In some embodiments, the method further comprises after performing the etch process, ashing the organic material between the two neighboring second semiconductor layers. In some embodiments, after performing the etch process, the first p-type work function layer in the gate trench remains intact.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.