TREA

High voltage III-nitride semiconductor devices

Follow

Information

  • Patent Grant
  • 9293561
  • Patent Number
    9,293,561
  • Date Filed
    Friday, April 25, 2014
    11 years ago
  • Date Issued
    Tuesday, March 22, 2016
    9 years ago
Information
Abstract
A III-N device is described has a buffer layer, a first III-N material layer on the buffer layer, a second III-N material layer on the first III-N material layer on an opposite side from the buffer layer and a dispersion blocking layer between the buffer layer and the channel layer. The first III-N material layer is a channel layer and a compositional difference between the first III-N material layer and the second III-N material layer induces a 2DEG channel in the first III-N material layer. A sheet or a distribution of negative charge at an interface of the channel layer and the dispersion blocking layer confines electrons away from the buffer layer.
Description
TECHNICAL FIELD

This invention relates to semiconductor devices fabricated on group III-nitride semiconductors.


BACKGROUND

Group III-nitride based devices have many potential material advantages over silicon based devices for high power electronics applications. Amongst others, the advantages can include a larger band gap and breakdown field, high electron mobility in a two dimensional electron gas (2DEG) and low thermal generation current. However, large native substrates for group III-nitride semiconductors are not yet widely available. Currently, III-nitride films are grown by heteroepitaxy on suitable non-III-nitride substrates.


Substrates commonly used to support III-nitride films are silicon carbide, sapphire or silicon. Heteroepitaxy can be done with molecular beam epitaxy (MBE) or metal oxide chemical vapor deposition (MOCVD), and lately with hydride vapor phase epitaxy (HYPE). It can be difficult to grow high quality thick gallium nitride layers by heteroepitaxy; therefore, high voltage devices in gallium nitride are typically lateral devices with gallium nitride layers that are only a few microns thick. It can be difficult to accommodate a large voltage in a lateral device without spacing out the electrodes a relatively large distance. For a large blocking voltage across the source/gate and drain in a FET or across the anode and cathode in a diode, the spacing between the electrodes needed to sustain the voltage can be large. For example, a 1 kV device may have gate-drain electrode spacing of 10 μm or larger. This can cause high voltage lateral devices to have a larger area than an equivalent vertical device. Thus, substrate cost becomes an important issue commercially.


To reduce cost, silicon is the most desirable substrate for III-nitride layers. However, due to the large lattice and thermal mismatch between silicon and gallium nitride, it can be necessary to include nucleation and stress management layers in the device structures. These layers, often called the buffer layer and comprised of layers of AlxGa1-xN that can include superlattices, can have a high density of threading dislocations and other extended defects, along with a multitude of point defects that act as deep traps or dopants. An appropriate buffer layer, even for a lattice mismatched substrate, can result in films of acceptable quality above the buffer layer. However, the layers within the buffer layer can have a high concentration of defect levels in the bandgap. The bandgap defect levels can cause dispersion or current collapse due to electron trapping in these layers, leakage at high drain biases due to carrier generation in these layers, and reduce the breakdown voltage of the device.



FIGS. 1(a) and 1(b) show an approach used to confine electrons to the channel. The III-nitride stack of FIG. 1(a) is for n-channel devices on the cation face, the preeminent form of III-nitride structure currently being used for fabricating HEMTs. The stack can be used to form a lateral device in which external biases modulate field and current in the active layer. The device structure includes a substrate 101 on which a buffer layer 102, which may include nucleation and stress management layers, is grown by heteroepitaxy. The active layer, which includes a channel layer 103 that has a 2DEG 104, is on the buffer layer 102. A barrier layer 105 whose dipole charge enables the formation of the 2DEG and confines the electrons to the channel layer is on an opposite side of the channel layer 103 from the buffer layer 102. Insulation and metallization layers are deposited and patterned to form the device (not shown).


Referring to FIG. 1(b), there can be a step in the conduction band edge (ΔEC) going from the channel layer to the buffer layer. As shown in the band diagram along the plane YY1, a higher conduction band edge in the buffer layer can prevent carrier injection and trapping in the buffer layer as long as the barrier height is larger than the energy of the electrons impinging on it. Electron e1 with energy less than the barrier height gets reflected back at the barrier (schematic trajectories r1 and r′1) while electron e2 with energy greater than the barrier gets injected into the barrier where it could get trapped (schematic trajectory r′2) or get collected by the substrate contact on the other side of the barrier (schematic trajectory r″2). FIG. 1(b) only shows trapping processes in the buffer layer. However, the defects that form deep levels in the buffer layer also diffuse into the channel layer where they can readily trap electrons and cause current collapse.


SUMMARY

In one aspect, a III-N device is described that has a buffer layer, a first III-N material layer on the buffer layer, a second III-N material layer on the first III-N material layer on an opposite side from the buffer layer and a dispersion blocking layer between the buffer layer and the channel layer. The first III-N material layer is a channel layer and a compositional difference between the first III-N material layer and the second III-N material layer induces a 2DEG channel in the first III-N material layer. A sheet or a distribution of negative charge at an interface of the channel layer and the dispersion blocking layer confines electrons away from the buffer layer.


In another aspect, an integrate circuit is described. The circuit includes a III-N device, where the III-N device is an enhancement mode transistor or a depletion mode transistor and is electrically connected to one of a diode, resistor or capacitor.


Embodiments of the device may include one or more of the following features. The lowest conduction band minimum in the dispersion blocking layer can be higher than the highest occupied conduction band minimum in the channel layer. The dispersion blocking layer can be configured to confine electrons to the channel layer during device operation. The device can include a spacer layer between the dispersion blocking layer and the buffer layer. The dispersion blocking layer can have a greater concentration of aluminum than the spacer layer. The channel layer can consist of a first III-nitride alloy and the spacer layer consists of a second III-nitride alloy, wherein the first III-nitride alloy and the second III-nitride alloy have aluminum mole fractions within 10% of one another. The material of the channel layer can be unintentionally doped and the spacer layer can be compensated or over compensated.


The spacer layer can consist of a III-nitride ternary alloy. The spacer layer can consist of AlxGa1-xN, 0≦x≦0.3. The dispersion blocking layer can be a ternary III-nitride alloy layer with a sheet or layer of negative polarization charge adjacent to the channel layer. The dispersion blocking layer can comprise AlxInyGa1-x-yN, y<x and 0<(x+y)<1. A portion of the dispersion blocking layer that is closer to the channel layer than the buffer layer can have a higher aluminum composition than a portion of the dispersion blocking layer that is closer to the buffer layer. The dispersion blocking layer can have a graded aluminum concentration. The dispersion blocking layer can have a stepped aluminum concentration. The composition of the ternary III-nitride alloy layer can be graded and the ternary III-nitride alloy layer can be intentionally compensated. Fe, C, Mg, Zn or Be or any combination of acceptor or amphoteric dopants can compensate the III-nitride layer. The device can include a spacer layer that is doped with Fe, C, Mg, Zn or Be or any combination of acceptor or amphoteric dopants. The device can include a source contact, a drain contact and a gate, wherein the gate is adjacent to the second III-N material layer, the source contact and drain contact are in electrical contact with the 2DEG and the device is an enhancement mode FET. The device can include a source contact, a drain contact and a gate, wherein the gate is in contact with the second III-N material layer, the source contact and drain contact are in electrical contact with the 2DEG and the device is a depletion mode FET. The device can include an anode that forms a Schottky barrier with the III-nitride stack and a cathode in electrical contact with the 2DEG, wherein the device is a diode. When in operation, the device can have an on-resistance increase under switching operation at voltages above 300V that is less than 10%. In operation the device can have an on-resistance increase that is less than 5%. In operation the device can have operation has an on-resistance increase that is less than 2%. In operation the device can have an on-resistance increase under switching operation at voltages above 1200V that is less than 5%. The channel layer can have a thickness less than 1 micron, such as less than 0.5 micron or less than 0.05 micron. A combined thickness of all III-N layers can be about 2 micron or less and the device can exhibit less than 20% dispersion when used in an application where the device blocks at least 300V. A combined thickness of all III-N layers can be about 2.5 microns or less and the device can exhibit less than 20% dispersion when used in an application where the device blocks at least 600V. A combined thickness of all III-N layers can be about 3 microns or less and the device can exhibit less than 20% dispersion when used in an application where the device blocks at least 1200V. The device can include a substrate on an opposite side of the buffer layer from the dispersion blocking layer, wherein the substrate comprises either silicon carbide, sapphire or substantially pure silicon.


One or more of the embodiments described herein may provide one of the following advantages. One solution to prevent current collapse caused by traps in the buffer layer is to grow a thick (>2 um) GaN channel layer to separate the electrons in the 2DEG from the defects in the buffer. However, while this solution can be a suitable approach for transistors grown on silicon carbide or sapphire substrates, it can be difficult to grow thick uninterrupted gallium nitride layers on silicon substrates. Therefore, the devices and methods described herein do not require a thick channel layer. Rather, channel layers with a thickness of less than 0.5 microns, such as less than 0.2 micron can be utilized. In addition to trapping and current collapse, another major challenge in the fabrication of GaN devices is the creation of insulating buffer layers. One or more types of an intentional impurity such as iron (Fe), carbon (C), or magnesium (Mg) may be added to the buffer to compensate unintentional impurities in order to render the buffer semi-insulating. However, the use of intentional impurities must be managed carefully and balanced with the need to reduce current collapse. For example, a standard AlGaN/GaN transistor can be grown in which the entire GaN layer is doped, for example with Fe, except for a thin portion near the AlGaN/GaN interface where the 2-DEG forms. This structure can result in excellent off-state leakage behavior, but can suffer from current collapse as a result of channel charge being trapped by deep levels associated with Fe during device operation. On the other end of the spectrum, an AlGaN/GaN structure can be grown where no intentional Fe doping is used. This structure will have little current collapse behavior, but has high off-state leakage at high voltages.


The solutions provided herein avoid problems occurring in other III-nitride devices, such as problems that occur in devices that offer other solutions, such as merely forming back barriers in cation faced III-nitride devices to confine carriers to the vicinity of the 2DEG. Some back barriers can result in devices exhibiting high dispersion, because the GaN channel layer next to the AlN/AlGaN buffer layer is not of a very high quality and can therefore trap channel charge during device operation. To prevent defects from forming near the device channel, the buffer layer has to be made thick (>0.5 μm). However, a thick high bandgap buffer layer can act as a poor thermal conductor to the substrate, which is undesirable for power devices. Furthermore, a thick AlN/AlGaN buffer layer with the large Al mole fraction (>20%), required to form the barrier to prevent electron entry into the buffer layer, is more difficult to grow. Even if one grows a thick AlGaN layer with Al mole fraction greater that 20%, it is very defected and causes a defected channel layer to be subsequently formed on it. Indium based quaternary III-nitrides produce a small conduction band discontinuity that acts as a back barrier. These schemes can be used in low-voltage applications to improve channel carrier confinement and thence transconductance and output resistance. However, they have limited applicability for high voltage devices, where operating voltages are greater than 100V, and carrier heating causes electrons to cross these small barriers.


The devices and methods described herein allow for fabrication of III-N devices on various substrates in which dispersion due to buffer layer traps is mitigated. By preventing the trapping of channel electrons in the bulk of the buffer layer, the background doping in the buffer layer can be much higher than would otherwise be practical, leading to a more manufacturable structure. Furthermore, if the channel layer is thin enough, the dopant levels can remain high in the channel layer without significant effect on electrical performance. This allows for the use of dopants (such as Fe in MOCVD) which may “ride” the surface during growth and result in long tails after the dopant source is shut off. The buffer layer is sufficiently insulating. The entire III-N material structure is also sufficiently thin to prevent defects resulting from thermal mismatch between the substrate and the III-N materials from forming. The devices described herein can be used in high voltage applications because they exhibit low trapping and low leakage. They can also be used for high frequency HEMTs to reduce dispersion. By separating the channel from the buffer, the design of optimum buffer layers can be decoupled from the design of the channel structure, resulting in higher performance and a more controllable, repeatable manufacturing process.





BRIEF DESCRIPTION OF DRAWINGS


FIG. 1(a) shows a III-nitride stack.



FIG. 1(b) is a schematic of a back barrier in GaN based devices showing how a conduction band back barrier can prevent carriers from the channel from getting trapped in the buffer layer.



FIG. 2 shows the general structure of a semiconductor stack with a dispersion blocking layer included.



FIG. 3 shows a cross-section of the semiconductor stack, wherein a dispersion blocking layer is added using a graded AlGaN layer.



FIG. 4 shows a simulated band diagram for a semiconductor stack with a dispersion blocking layer.



FIGS. 5(a) and 5(b) show band diagrams that show how the dispersion blocking layer prevents carrier trapping.



FIGS. 6(a) and 6(b) show the CV and carrier profiles for two semiconductor devices with different compensating schemes below the dispersion blocking layer.



FIGS. 7(a) and 7(b) have graphs showing drain leakage current vs. drain bias when the HEMTs are biased OFF for devices with and without the dispersion blocking layer.



FIGS. 8(a) and 8(b) have graphs of the ON resistance and drain current as a function of the drain voltage for devices with and without the dispersion blocking layer.



FIG. 9 shows the schematic cross-section of a semiconductor stack with a dispersion blocking layer on a silicon substrate with a HEMT fabricated on that.





DETAILED DESCRIPTION

Device structures in which a dispersion blocking layer is included between the channel layer and the buffer layer of a III-N semiconductor device confine carriers to the channel layer so that dispersion or current collapse due to trapping in the buffer layer is minimized. The term dispersion blocking layer describes a layered structure in a III-N device that reduces electron trapping in the buffer layer and thence reduces drain current dispersion or drain current collapse and output resistance increase. The terms dispersion and current collapse are used synonymously herein for drain current reduction due to electron trapping. Additionally, the buffer layer can be made sufficiently insulating, such as by intentional doping, to prevent buffer leakage. Dispersion blocking layers can alleviate the need to grow thick channel or buffer layer(s) in order to reduce trapping and current collapse. The blocking layer can further eliminate the need to optimize the trade-off between reducing current collapse and having a low leakage buffer. By inserting a polarization engineered dispersion blocking layer close to the electron channel, electrons are prevented from entering the defective buffer layer, permitting the insulating nature of the buffer layer to be improved. A dispersion blocking layer can be used with GaN devices formed on silicon.


GaN-based materials and foreign substrate materials such as silicon have different lattice constants and different coefficients of thermal expansion. These differences can be addressed in part by using AlGaInN materials in the buffer layer, which may comprise one or more layers for nucleation, stress management and defect reduction, to offset the effect of the lattice mismatch and the effect of the differences in the coefficient of thermal expansion. In addition, for high voltage devices (VDS>300V, 600V or 1200V, depending on the application) GaN-based epitaxial material grown on a silicon substrate often has a thickness large enough to prevent breakdown of the device fabricated from the GaN epitaxial material. That is, it is desirable to prevent breakdown along the path from the drain to the silicon to the source. This path is possible because the Si substrate has a higher conductivity and lower breakdown strength than the GaN grown thereon.


The various III-N alloys used to form nucleation and buffer layers to manage the effects of lattice mismatch and the coefficient of thermal expansion are typically very defective because of the lattice mismatch and buffer layer's requirements to accommodate strain due to thermal coefficient mismatch. The channel material grown above the nucleation and buffer layer on which the active high power device is fabricated can be grown as pure and thick as possible to attempt to separate the active channel region in the channel layer from the buffer layer. A thick channel layer can reduce the problems of dispersion and current collapse due to electron trapping in defects. However, the maximum thickness of the high purity III-N channel is limited because of the lattice mismatch and coefficient of thermal expansion problem. Further, a thick channel can lead to excessive bowing of the wafer and can potentially cause the wafer to crack. The use of the III-N dispersion blocking layer can mitigate the need for a thick channel, because the III-N dispersion blocking layer prevents electrons from the channel from interacting with the defects in the buffer layer during device operation. This allows the buffer layer to be designed independent of the channel layer, breaking a design trade-off that can exist. The blocking layer can also allow reduced dispersion operation of high power GaN-based devices fabricated on Si substrates.


Referring to FIG. 2, a substrate 1 is an appropriate substrate, such as silicon carbide, sapphire, silicon, a III-nitride or any other material, for the growth of III-nitride semiconducting layers, including cation-face III-nitride layers, by hetero- or homo-epitaxy. A channel layer 4 and a barrier layer 5 form the active portion of the device, with the bandgap of the barrier layer 5 being larger than that of the channel layer 4. Buffer layer 2 is between the substrate 1 and the channel layer 4. In general, the active portion of the device can include any combination of III-N layers that can be used to form a III-N electronic device, such as a diode, HEMT, HFET, MISHFET, POLFET, or other III-N device. Examples of III-N diode and transistor devices, along with III-N layers which comprise these devices, can be found in U.S. Pat. No. 7,915,643, U.S. Pat. No. 7,795,642, U.S. Pat. No. 7,851,825, U.S. Pat. No. 8,519,438, U.S. Pat. No. 7,898,004, U.S. Pat. No. 7,884,394, and U.S. Patent Publication No. 2009/0072269, filed Sep. 17, 2007, all of which are hereby incorporated by reference.


Buffer layer 2 enables the formation of overlying III-nitride layers. The buffer layer 2 can be a simple layer of a single material or can be formed of multiple layers, such as any combination of AlxGa1-xN/GaN layers. The buffer layer 2 can be lattice mismatched to the substrate. Ideally, the average lattice constant of the lower face of the buffer layer 2 is matched to the substrate 1 and the average lattice constant of the upper face of the buffer layer 2 is matched to the lattice constant of the channel layer. However, this type of lattice matching is difficult to achieve in a defect-free buffer layer 2. Rather, the lattice constant mismatching that realistically occurs between buffer layer 2 and substrate 1 and between buffer layer 2 and channel layer 4 can result in the formation of dislocations and other extended defects which have deep levels. The buffer layer 2 can be intentionally doped, such as with iron (Fe), carbon (C), or magnesium (Mg), to compensate for unintentional n-type dopants, which can cause buffer leakage. The density of deep levels, which can trap channel charge during device operation, can be further increased by the intentional doping to compensate the unintentional dopants in the buffer layer to make it semi-insulating.


Dispersion blocking layer 3 is inserted between the buffer layer 2 and the channel layer 4. The dispersion blocking layer 3 is a thin, such as, less than 500 nm thick, for example, less than 200 nm thick, and if need be compensated, that is, intentionally doped with p-type dopants, layer of a III-nitride material. The dispersion blocking layer 3 is strained such that it is polarized with respect to the channel material. A sheet of negative polarization charge on its upper face creates a field to confine electrons to the upper regions of the channel layer 4 and prevents the electrons from getting trapped in the buffer layer 2. A band-edge discontinuity at the interface of the channel layer 4 and the dispersion blocking layer 3 such that the conduction band minimum is higher in the dispersion blocking layer 3 further helps to reduce electron injection and trapping.


The dispersion blocker layer 3 is essentially a layer, or a combination of layers, which creates a large field and barrier to isolate electrons from traps in the defective buffer layer 2. One way of isolating electrons is to create a large field perpendicular to the plane of the 2DEG that confines electrons to the part of the channel layer 4 that is substantially trap-free so that trapping is, for example less than 10% of the channel charge, during device operation. The field is created by a sheet or layer of negative charge using polarization or delta doping. The field therefore confines electrons to the top of the channel layer. Electrons are isolated by growing a compensated semi-insulating pseudomorphically strained dispersion blocking layer 3, so that polarization creates a sheet of negative charge just below the channel layer. In some cases, a compensated spacer layer is required between the pseudomorphically strained dispersion blocking layer 3 and the buffer layer.


The dispersion blocking layer 3 can be formed of a III-nitride layer of alloys such as a binary alloy AN, or a ternary alloy such as AxGa1-xN with 0≦x<1, or a quaternary alloy ZyAxGa1-x-yN with 0≦(x+y)<1, where A and Z are cationic elements. In some embodiments, these layers are graded from one alloy to the next or the alloys can be stepped within the layer. Two simple examples are: an AlN layer or an AlxGa1-xN layer, where the latter is graded or stepped in Al composition. The dispersion blocking layer can be an AlGaN/GaN superlattice. The dispersion blocking layer 3 can be intentionally compensated with Fe, Mg, Be, C or Zn or any other suitable dopant or combination of dopants that are able to prevent the formation of a 2DEG or a less confined electron distribution in or below the dispersion blocking layer. The extent of the compensation can be from 0 to 100% depending on the device requirement, the tradeoff being between the advantages of little mobile electrons in or below the dispersion blocking layer 3 and the disadvantage of deep defects due to the intentional compensation doping. The charge due to polarization creates the field that raises the conduction band edge in the portion of the channel layer 4 adjacent to the dispersion blocking layer 3. Furthermore, a III-N spacer layer can be included between the buffer layer 2 and dispersion blocking layer 3 and could be considered part of the dispersion blocking layer 3. In some embodiments, the spacer layer is a III-nitride ternary alloy such as AlxGa1-xN, where 0≦x<0.3. The spacer layer can be compensated, that is, the right amount of the opposite type of dopant is added to make the semiconductor near intrinsic, or overcompensated, that is, the type of material is changed, such as from an n-type material to a p-type material.


An exemplary device having a dispersion blocking layer is shown in schematic in FIG. 3. Substrate 1 is silicon carbide. Buffer layer 2 includes a thin AlN nucleation layer 21 grown on the SiC substrate 1 and an iron doped GaN layer 22 on the nucleation layer. The iron doped GaN layer can be between about 1 and 10 microns thick, such as about 2.5 microns thick. The dispersion blocking layer 3 has a moderately Fe doped GaN spacer layer 31 with a graded AlxGa1-xN (x going from 0 to 0.23) layer 32 on the spacer layer. The graded AlxGa1-xN layer is about 27 nm thick. The channel layer 4 is formed of GaN and has a thickness of less than 500 nm, such as about 50 nm. The barrier layer 5 includes a 0.6 nm AlN layer 51 with a 27 nm Al0.28Ga0.72N layer 52 thereon.


A simulated band diagram for the device shown in FIG. 3 is shown in FIG. 4. The addition of the dispersion blocking layer 3 creates a large field E, which raises the conduction band edge 201 at the bottom face of the channel layer 4. Furthermore, the iron doping can prevent the formation of a 2DEG below the graded AlGaN sublayer of the blocking layer 3. Alternatively, an additional 2DEG or other charge distribution can be present in or below the dispersion blocking layer 3, where the concentration of additional charge can be controlled by adjusting the concentration of iron doping. The band diagrams in FIGS. 5(a) and 5(b) show the difference in the barrier for situations where a device has (FIG. 5(a)) and does not have (FIG. 5(b)) an AlGaN dispersion blocking layer 3. As shown in the band diagrams, adding a graded AlGaN blocking layer prevents electrons from being scattered into the buffer layer 2 where the electrons can be trapped.



FIGS. 6(a)-8(b) show the effects of introducing an AlGaN dispersion blocking layer. As shown by the graphs, doping the spacer layer such as by Fe doping, can prevent or reduce the formation of a 2DEG below the dispersion blocking layer 3. The elimination of a 2-DEG below the dispersion blocking layer 3 can reduce device leakage or early breakdown for some device structures. Further, the dispersion blocking layer 3 can improve device switching performance.



FIGS. 6(a) and 6(b) show capacitance-voltage (CV) plots and carrier profiles of two devices with AlGaN dispersion blocking layers. Each carrier profile has two peaks, the peaks P1 and P3 closer to the surface are due to the channel 2DEG and the peaks P2 and P4 are deeper in the semiconductor indicate the electron concentration below the dispersion blocking AlGaN layer. The plots in FIG. 6(a) are for a device that has been Fe doped right up to the graded AlGaN layer and the plots in FIG. 6(b) are for a device with Fe doping only in the buffer layer. In the latter case a 2DEG layer is formed below the AlGaN dispersion blocking layer, which is shown by P4 being sharper and higher than P2. A 2DEG below the AlGaN dispersion blocking layer can be problematic at large device biases for some device structures.



FIGS. 7(a), 7(b), 8(a), and 8(b) are performance plots of performance parameters of HEMTs with and without a graded AlGaN dispersion blocking layer. In FIG. 7(a), current voltage (IV) plots for devices without dispersion blocking layers are shown and in FIG. 7(b) the IV plots for devices with dispersion blocking layers are shown. The plots (each plot is for a different device) show the drain leakage current as a function of drain bias with the devices biased OFF. Devices with a dispersion blocking layer (FIG. 7(b)) have on the average smaller leakage currents compared to devices without the dispersion blocking layer (FIG. 7(a)).


In FIGS. 8(a) and 8(b), plots of the on resistance (RON), when the FET is switched ON after being turned OFF and kept at a certain drain bias, is shown as a function of the drain voltage when the device is kept OFF. Also plotted is the drain current (IDS) used for measuring each RON and as can be seen the drain currents are around the nominal 1 A value set for these measurements. The RON after the drain is kept at a certain reverse bias is a measure of trapping that modulates the channel. There is little evidence of trapping in the device with the graded AlGaN dispersion blocking layer (FIG. 8(b)). However, the device without the dispersion blocking layer (FIG. 8(a)) shows a steady increase of trapping effects, exemplified by the increase of RON, as the drain voltage is increased.



FIG. 9 shows a cross-section of a GaN-on-Si depletion mode (D-mode) HEMT that has a dispersion blocking layer. On a silicon substrate 1, a III-nitride buffer layer 2 is grown heteroepitaxially. Next, a dispersion blocking layer 3 either with or without a GaN spacer layer is grown on the buffer layer 2. The channel layer 4 and the barrier layer 5 are grown on the blocking layer 3. A D-mode HEMT is fabricated by patterning and forming ohmic source 6 and drain 9 contacts, depositing a suitable dielectric 8 and appropriately micro-machining the dielectric 8 before depositing the gate 7 and the slant field plate on the dielectric 8. The device is optionally coated with a passivation layer (not shown) that is patterned to open contact holes for wire bonding or flip-chip bonding to bond pads. This D-mode HEMT is illustrated as an example of how a dispersion blocking layer could be used in a planar GaN device. E-mode HEMTs, diodes or even GaN integrated circuits can benefit from such dispersion blocking layers.


A number of embodiments of the invention have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the invention. For example, the dispersion blocking layer could have different types of buffer and active layers on either side, the buffer layer optimized for the substrate and the III-nitride active layer so that the latter have the requisite strain profile and low defect density, and the active layers themselves optimized for the FET, diode or high voltage integrated circuit fabricated in them. The specific HEMT structure and measurements on it that are presented are meant only to show the efficacy of the dispersion blocking layer. The structures described herein can be grown by epitaxy, such as by MBE or HYPE. Although the term “on” is used in the claims to indicate the relative locations of some of the components, such as layers, there may be one or more intervening layers. When the term “directly on” is used, there is no intervening layer. Accordingly, other embodiments are within the scope of the following claims.

Claims
  • 1. A method of forming a III-N device, comprising: forming a first III-N material layer on a buffer layer;forming a second III-N material layer on an opposite side of the first III-N material layer from the buffer layer, wherein the first III-N material layer is a channel layer and a compositional difference between the first III-N material layer and the second III-N material layer induces a 2DEG channel in the first III-N material layer; andforming a dispersion blocking layer between the buffer layer and the channel layer, the dispersion blocking layer being doped with Fe, Mg, Be, C, or Zn; whereina sheet or a distribution of negative charge at an interface of the channel layer and the dispersion blocking layer confines electrons away from the buffer layer;a band-edge discontinuity at the interface of the channel layer and the dispersion blocking layer results in a conduction band edge directly adjacent to the interface being higher in the dispersion blocking layer than in the channel layer; anda conduction band minimum of the dispersion blocking layer is within the dispersion blocking layer and away from the interface.
  • 2. The method of claim 1, wherein the dispersion blocking layer is configured to confine electrons to the channel layer during device operation.
  • 3. A method of forming a III-N device, comprising: forming a first III-N material layer on a buffer layer;forming a second III-N material layer on an opposite side of the first III-N material layer from the buffer layer, wherein the first III-N material layer is a channel layer and a compositional difference between the first III-N material layer and the second III-N material layer induces a 2DEG channel in the first III-N material layer;forming a dispersion blocking layer between the buffer layer and the channel layer; andforming a spacer layer between the dispersion blocking layer and the buffer layer; whereina sheet or a distribution of negative charge at an interface of the channel layer and the dispersion blocking layer confines electrons away from the buffer layer;a band-edge discontinuity at the interface of the channel layer and the dispersion blocking layer results in a conduction band edge directly adjacent to the interface being higher in the dispersion blocking layer than in the channel layer; anda conduction band minimum of the dispersion blocking layer is within the dispersion blocking layer and away from the interface.
  • 4. The method of claim 3, wherein the dispersion blocking layer has a greater concentration of aluminum than the spacer layer.
  • 5. The method of claim 3, wherein the channel layer consists of a first III-nitride alloy and the spacer layer consists of a second III-nitride alloy, wherein the first III-nitride alloy and the second III-nitride alloy have aluminum mole fractions within 10% of one another.
  • 6. The method of claim 3, wherein the spacer layer consists of AlxGa1-xN, 0≦x<0.3.
  • 7. The method of claim 3, further comprising forming a source contact, a drain contact, and a gate, wherein the gate is adjacent to the second III-N material layer, the source contact and drain contact are in electrical contact with the 2DEG channel, and the III-N device is an enhancement mode FET.
  • 8. The method of claim 3, further comprising forming a source contact, a drain contact, and a gate, wherein the source contact and drain contact are in electrical contact with the 2DEG and the device is a depletion mode FET.
  • 9. The method of claim 3, wherein the first and second III-N material layers are part of a III-nitride stack, the device further comprises an anode that forms a Schottky barrier with the III-nitride stack and a cathode in electrical contact with the 2DEG, and the device is a diode.
  • 10. The method of claim 3, wherein the device in operation has an on-resistance increase under switching operation at voltages above 300V that is less than 10%.
  • 11. The method of claim 10, wherein the device in operation has an on-resistance increase under switching operation at voltages above 1200V that is less than 5%.
  • 12. The method of claim 3, wherein the channel layer is formed having a thickness less than 1 micron.
  • 13. The method of claim 12, wherein the channel layer is formed having a thickness less than 0.5 micron.
  • 14. The method of claim 13, wherein the channel layer is formed having a thickness less than 0.05 micron.
  • 15. The method of claim 3, wherein a combined thickness of all III-N layers in the device is about 2 μm or less and the device exhibits less than 20% dispersion when used in an application where the device blocks at least 300V.
  • 16. The method of claim 3, wherein a combined thickness of all III-N layers in the device is about 2.5 μm or less and the device exhibits less than 20% dispersion when used in an application where the device blocks at least 600V.
  • 17. The method of claim 3, wherein a combined thickness of all III-N layers in the device is about 3 μm or less and the device exhibits less than 20% dispersion when used in an application where the device blocks at least 1200V.
  • 18. The method of claim 3, wherein the buffer layer is formed on a substrate, the substrate comprising silicon carbide, sapphire, or silicon.
  • 19. A method of forming a III-N device, comprising: forming a first III-N material layer on a buffer layer;forming a second III-N material layer on an opposite side of the first III-N material layer from the buffer layer, wherein the first III-N material layer is a channel layer and a compositional difference between the first III-N material layer and the second III-N material layer induces a 2DEG channel in the first III-N material layer; andforming a dispersion blocking layer between the buffer layer and the channel layer; whereina sheet or a distribution of negative charge at an interface of the channel layer and the dispersion blocking layer confines electrons away from the buffer layer;a band-edge discontinuity at the interface of the channel layer and the dispersion blocking layer results in a conduction band edge directly adjacent to the interface being higher in the dispersion blocking layer than in the channel layer;a conduction band minimum of the dispersion blocking layer is within the dispersion blocking layer and away from the interface; andthe dispersion blocking layer comprises AlxInyGa1-x-yN, y<x and 0<(x+y)<1.
  • 20. The method of claim 19, wherein a portion of the dispersion blocking layer that is closer to the channel layer than the buffer layer has a higher aluminum composition than a portion of the dispersion blocking layer that is closer to the buffer layer.
  • 21. The method of claim 20, wherein the dispersion blocking layer has a graded aluminum concentration.
  • 22. The method of claim 20, wherein the dispersion blocking layer has a stepped aluminum concentration.
  • 23. A method of forming a III-N device, comprising: forming a first III-N material layer on a buffer layer;forming a second III-N material layer on an opposite side of the first III-N material layer from the buffer layer, wherein the first III-N material layer is a channel layer and a compositional difference between the first III-N material layer and the second III-N material layer induces a 2DEG channel in the first III-N material layer; andforming a dispersion blocking layer between the buffer layer and the channel layer; whereina sheet or a distribution of negative charge at an interface of the channel layer and the dispersion blocking layer confines electrons away from the buffer layer;a band-edge discontinuity at the interface of the channel layer and the dispersion blocking layer results in a conduction band edge directly adjacent to the interface being higher in the dispersion blocking layer than in the channel layer;a conduction band minimum of the dispersion blocking layer is within the dispersion blocking layer and away from the interface;the dispersion blocking layer is a ternary III-nitride alloy layer with a sheet or layer of negative polarization charge adjacent to the channel layer; andthe composition of the ternary III-nitride alloy layer is graded and the ternary III-nitride alloy layer is doped with Fe, C, Mg, Zn or Be.
  • 24. A method of forming a III-N device, comprising: forming a first III-N material layer on a buffer layer;forming a second III-N material layer on an opposite side of the first III-N material layer from the buffer layer, wherein the first III-N material layer is a channel layer and a compositional difference between the first III-N material layer and the second III-N material layer induces a 2DEG channel in the first III-N material layer; andforming a dispersion blocking layer between the buffer layer and the channel layer; whereina sheet or a distribution of negative charge at an interface of the channel layer and the dispersion blocking layer confines electrons away from the buffer layer;a band-edge discontinuity at the interface of the channel layer and the dispersion blocking layer results in a conduction band edge directly adjacent to the interface being higher in the dispersion blocking layer than in the channel layer;a conduction band minimum of the dispersion blocking layer is within the dispersion blocking layer and away from the interface; andthe dispersion blocking layer is doped with Fe, C, Mg, Zn or Be or any combination of acceptor or amphoteric dopants.
  • 25. A method of forming a III-N device, comprising: forming a first III-N material layer on a buffer layer;forming a second III-N material layer on an opposite side of the first III-N material layer from the buffer layer, wherein the first III-N material layer is a channel layer and a compositional difference between the first III-N material layer and the second III-N material layer induces a 2DEG channel in the first III-N material layer;forming a dispersion blocking layer between the buffer layer and the channel layer; andforming a spacer layer that is doped with Fe, C, Mg, Zn or Be or any combination of acceptor or amphoteric dopants; whereina sheet or a distribution of negative charge at an interface of the channel layer and the dispersion blocking layer confines electrons away from the buffer layer;a band-edge discontinuity at the interface of the channel layer and the dispersion blocking layer results in a conduction band edge directly adjacent to the interface being higher in the dispersion blocking layer than in the channel layer;a conduction band minimum of the dispersion blocking layer is within the dispersion blocking layer and away from the interface;the dispersion blocking layer is a ternary III-nitride alloy layer with a sheet or layer of negative polarization charge adjacent to the channel layer.
  • 26. A method of forming a III-N device, comprising: forming a first III-N material layer on a buffer layer;forming a second III-N material layer on an opposite side of the first III-N material layer from the buffer layer, wherein the first III-N material layer is a channel layer and a compositional difference between the first III-N material layer and the second III-N material layer induces a 2DEG channel in the first III-N material layer; andforming a dispersion blocking layer between the buffer layer and the channel layer; whereina sheet or a distribution of negative charge at an interface of the channel layer and the dispersion blocking layer confines electrons away from the buffer layer;the dispersion blocking layer has a wider bandgap than the channel layer;a conduction band minimum of the dispersion blocking layer is within the dispersion blocking layer and away from the interface; andthe dispersion blocking layer is doped with Fe, C, Mg, Zn, or Be.
  • 27. The method of claim 26, wherein the dispersion blocking layer comprises AlxGa1-xN.
  • 28. The method of claim 27, wherein the dispersion blocking layer has a graded Al composition.
  • 29. The method of claim 26, further comprising a spacer layer between the dispersion blocking layer and the buffer layer.
  • 30. The method of claim 29, wherein the spacer layer is doped with Fe, C, Mg, Zn, or Be.
  • 31. A method of forming nitride-based device, comprising: forming a first nitride-based material layer on a buffer layer;forming a second nitride-based material layer on an opposite side of the first nitride-based material layer from the buffer layer, wherein the first nitride-based material layer is a channel layer and a compositional difference between the first nitride-based material layer and the second nitride-based material layer induces a 2DEG channel in the first nitride-based material layer; andforming a dispersion blocking layer between the buffer layer and the channel layer; whereinthe dispersion blocking layer is strained to induce a sheet or a distribution of negative charge at an interface of the channel layer and the dispersion blocking layer; anda conduction band minimum of the dispersion blocking layer is within the dispersion blocking layer and away from the interface.
  • 32. The method of claim 31, further comprising forming a source contact, a drain contact, and a gate, wherein the gate is adjacent to the second nitride-based material layer, the source contact and drain contact are in electrical contact with the 2DEG channel, and the III-N device is a FET.
  • 33. The method of claim 31, wherein the dispersion blocking layer comprises AlxGa1-xN.
  • 34. The method of claim 33, wherein the dispersion blocking layer has a graded Al composition.
  • 35. The method of claim 31, further comprising forming a spacer layer between the dispersion blocking layer and the buffer layer.
  • 36. The method of claim 35, wherein the spacer layer is doped with Fe, C, Mg, Zn, or Be.
  • 37. The method of claim 31, wherein the dispersion blocking layer is doped with Fe, C, Mg, Zn, or Be.
CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation application of U.S. patent application Ser. No. 12/465,968, filed May 14, 2009, the disclosure of which is hereby incorporated by reference in its entirety.

US Referenced Citations (210)
Number Name Date Kind
4300091 Schade, Jr. Nov 1981 A
4645562 Liao et al. Feb 1987 A
4728826 Einzinger et al. Mar 1988 A
4821093 Iafrate et al. Apr 1989 A
4914489 Awano Apr 1990 A
5051618 Lou Sep 1991 A
5329147 Vo et al. Jul 1994 A
5618384 Chan et al. Apr 1997 A
5646069 Jelloian et al. Jul 1997 A
5663091 Yen et al. Sep 1997 A
5705847 Kashiwa et al. Jan 1998 A
5714393 Wild et al. Feb 1998 A
5909103 Williams Jun 1999 A
5998810 Hatano et al. Dec 1999 A
6008684 Ker et al. Dec 1999 A
6097046 Plumton Aug 2000 A
6100571 Mizuta et al. Aug 2000 A
6316793 Sheppard et al. Nov 2001 B1
6373082 Ohno et al. Apr 2002 B1
6475889 Ring Nov 2002 B1
6486502 Sheppard et al. Nov 2002 B1
6504235 Schmitz et al. Jan 2003 B2
6515303 Ring Feb 2003 B2
6548333 Smith Apr 2003 B2
6583454 Sheppard et al. Jun 2003 B2
6586781 Wu et al. Jul 2003 B2
6649497 Ring Nov 2003 B2
6727531 Redwing et al. Apr 2004 B1
6777278 Smith Aug 2004 B2
6849882 Chavarkar et al. Feb 2005 B2
6867078 Green et al. Mar 2005 B1
6946739 Ring Sep 2005 B2
6979863 Ryu Dec 2005 B2
6982204 Saxler et al. Jan 2006 B2
7030428 Saxler Apr 2006 B2
7045404 Sheppard et al. May 2006 B2
7071498 Johnson et al. Jul 2006 B2
7084475 Shelton et al. Aug 2006 B2
7125786 Ring et al. Oct 2006 B2
7126212 Enquist et al. Oct 2006 B2
7161194 Parikh et al. Jan 2007 B2
7170111 Saxler Jan 2007 B2
7230284 Parikh et al. Jun 2007 B2
7238560 Sheppard et al. Jul 2007 B2
7253454 Saxler Aug 2007 B2
7265399 Sriram et al. Sep 2007 B2
7268375 Shur et al. Sep 2007 B2
7304331 Saito et al. Dec 2007 B2
7321132 Robinson et al. Jan 2008 B2
7326971 Harris et al. Feb 2008 B2
7332795 Smith et al. Feb 2008 B2
7364988 Harris et al. Apr 2008 B2
7388236 Wu et al. Jun 2008 B2
7419892 Sheppard et al. Sep 2008 B2
7432142 Saxler et al. Oct 2008 B2
7456443 Saxler et al. Nov 2008 B2
7465967 Smith et al. Dec 2008 B2
7501669 Parikh et al. Mar 2009 B2
7544963 Saxler Jun 2009 B2
7547925 Wong et al. Jun 2009 B2
7548112 Sheppard Jun 2009 B2
7550783 Wu et al. Jun 2009 B2
7550784 Saxler et al. Jun 2009 B2
7566918 Wu et al. Jul 2009 B2
7573078 Wu et al. Aug 2009 B2
7592211 Sheppard et al. Sep 2009 B2
7598108 Li et al. Oct 2009 B2
7612390 Saxler et al. Nov 2009 B2
7615774 Saxler Nov 2009 B2
7638818 Wu et al. Dec 2009 B2
7678628 Sheppard et al. Mar 2010 B2
7692263 Wu et al. Apr 2010 B2
7709269 Smith et al. May 2010 B2
7709859 Smith et al. May 2010 B2
7745851 Harris Jun 2010 B2
7755108 Kuraguchi Jul 2010 B2
7759700 Ueno et al. Jul 2010 B2
7777252 Sugimoto et al. Aug 2010 B2
7777254 Sato Aug 2010 B2
7795642 Suh et al. Sep 2010 B2
7812369 Chini et al. Oct 2010 B2
7851825 Suh et al. Dec 2010 B2
7855401 Sheppard et al. Dec 2010 B2
7875537 Suvorov et al. Jan 2011 B2
7875914 Sheppard Jan 2011 B2
7884394 Wu et al. Feb 2011 B2
7884395 Saito Feb 2011 B2
7892974 Ring et al. Feb 2011 B2
7893500 Wu et al. Feb 2011 B2
7898004 Wu et al. Mar 2011 B2
7901994 Saxler et al. Mar 2011 B2
7906799 Sheppard et al. Mar 2011 B2
7915643 Suh et al. Mar 2011 B2
7915644 Wu et al. Mar 2011 B2
7919791 Flynn et al. Apr 2011 B2
7928475 Parikh et al. Apr 2011 B2
7948011 Rajan et al. May 2011 B2
7955918 Wu et al. Jun 2011 B2
7960756 Sheppard et al. Jun 2011 B2
7985986 Heikman et al. Jul 2011 B2
8049252 Smith et al. Nov 2011 B2
8519438 Mishra et al. Aug 2013 B2
20010032999 Yoshida Oct 2001 A1
20010040247 Ando et al. Nov 2001 A1
20020036287 Yu et al. Mar 2002 A1
20020121648 Hsu et al. Sep 2002 A1
20020167023 Chavarkar et al. Nov 2002 A1
20030003724 Uchiyama et al. Jan 2003 A1
20030006437 Mizuta et al. Jan 2003 A1
20030020092 Parikh et al. Jan 2003 A1
20040041169 Ren et al. Mar 2004 A1
20040061129 Saxler et al. Apr 2004 A1
20040164347 Zhao et al. Aug 2004 A1
20050001235 Murata et al. Jan 2005 A1
20050077541 Shen et al. Apr 2005 A1
20050133816 Fan et al. Jun 2005 A1
20050189561 Kinzer et al. Sep 2005 A1
20050189562 Kinzer et al. Sep 2005 A1
20050194612 Beach Sep 2005 A1
20050253168 Wu et al. Nov 2005 A1
20050274977 Saito et al. Dec 2005 A1
20060011915 Saito et al. Jan 2006 A1
20060043499 De Cremoux et al. Mar 2006 A1
20060060871 Beach Mar 2006 A1
20060076677 Daubenspeck et al. Apr 2006 A1
20060102929 Okamoto et al. May 2006 A1
20060108602 Tanimoto May 2006 A1
20060108605 Yanagihara et al. May 2006 A1
20060121682 Saxler Jun 2006 A1
20060124962 Ueda et al. Jun 2006 A1
20060157729 Ueno et al. Jul 2006 A1
20060186422 Gaska et al. Aug 2006 A1
20060189109 Fitzgerald Aug 2006 A1
20060202272 Wu et al. Sep 2006 A1
20060220063 Kurachi et al. Oct 2006 A1
20060226442 Zhang et al. Oct 2006 A1
20060255364 Saxler et al. Nov 2006 A1
20060289901 Sheppard et al. Dec 2006 A1
20070007547 Beach Jan 2007 A1
20070018187 Lee et al. Jan 2007 A1
20070018199 Sheppard et al. Jan 2007 A1
20070018210 Sheppard Jan 2007 A1
20070045670 Kuraguchi Mar 2007 A1
20070080672 Yang Apr 2007 A1
20070128743 Huang et al. Jun 2007 A1
20070131968 Morita et al. Jun 2007 A1
20070132037 Hoshi et al. Jun 2007 A1
20070134834 Lee et al. Jun 2007 A1
20070145390 Kuraguchi Jun 2007 A1
20070145417 Brar et al. Jun 2007 A1
20070158692 Nakayama et al. Jul 2007 A1
20070164315 Smith et al. Jul 2007 A1
20070164322 Smith et al. Jul 2007 A1
20070194354 Wu et al. Aug 2007 A1
20070205433 Parikh et al. Sep 2007 A1
20070210329 Goto Sep 2007 A1
20070215899 Herman Sep 2007 A1
20070224710 Palacios et al. Sep 2007 A1
20070228477 Suzuki et al. Oct 2007 A1
20070241368 Mil'shtein et al. Oct 2007 A1
20070278518 Chen et al. Dec 2007 A1
20070295985 Weeks, Jr. et al. Dec 2007 A1
20080073670 Yang et al. Mar 2008 A1
20080093626 Kuraguchi Apr 2008 A1
20080121876 Otsuka et al. May 2008 A1
20080157121 Ohki Jul 2008 A1
20080203430 Simin et al. Aug 2008 A1
20080230784 Murphy Sep 2008 A1
20080237606 Kikkawa et al. Oct 2008 A1
20080237640 Mishra et al. Oct 2008 A1
20080274574 Yun Nov 2008 A1
20080283844 Hoshi et al. Nov 2008 A1
20080296618 Suh et al. Dec 2008 A1
20080308813 Suh et al. Dec 2008 A1
20090001409 Takano et al. Jan 2009 A1
20090032820 Chen Feb 2009 A1
20090032879 Kuraguchi Feb 2009 A1
20090045438 Inoue et al. Feb 2009 A1
20090050936 Oka Feb 2009 A1
20090065810 Honea et al. Mar 2009 A1
20090072240 Suh et al. Mar 2009 A1
20090072269 Suh et al. Mar 2009 A1
20090075455 Mishra Mar 2009 A1
20090085065 Mishra et al. Apr 2009 A1
20090121775 Ueda et al. May 2009 A1
20090140262 Ohki et al. Jun 2009 A1
20090146185 Suh et al. Jun 2009 A1
20090201072 Honea et al. Aug 2009 A1
20090218598 Goto Sep 2009 A1
20090267078 Mishra et al. Oct 2009 A1
20100019225 Lee Jan 2010 A1
20100019279 Chen et al. Jan 2010 A1
20100065923 Charles et al. Mar 2010 A1
20100067275 Wang et al. Mar 2010 A1
20100133506 Nakanishi et al. Jun 2010 A1
20100140660 Wu et al. Jun 2010 A1
20100201439 Wu et al. Aug 2010 A1
20100203234 Anderson et al. Aug 2010 A1
20100219445 Yokoyama et al. Sep 2010 A1
20100244087 Horie et al. Sep 2010 A1
20100288998 Kikuchi et al. Nov 2010 A1
20100289067 Mishra et al. Nov 2010 A1
20110006346 Ando et al. Jan 2011 A1
20110012110 Sazawa et al. Jan 2011 A1
20110249359 Mochizuki et al. Oct 2011 A1
20120168822 Matsushita Jul 2012 A1
20120193638 Keller et al. Aug 2012 A1
20120211800 Boutros Aug 2012 A1
20120217512 Renaud Aug 2012 A1
20120315445 Mizuhara et al. Dec 2012 A1
Foreign Referenced Citations (48)
Number Date Country
1599960 Mar 2005 CN
1748320 Mar 2006 CN
101107713 Jan 2008 CN
101312207 Nov 2008 CN
101897029 Nov 2010 CN
102017160 Apr 2011 CN
1 998 376 Dec 2008 EP
2 188 842 May 2010 EP
11-224950 Aug 1999 JP
2000-058871 Feb 2000 JP
2003-229566 Aug 2003 JP
2003-244943 Aug 2003 JP
2004-260114 Sep 2004 JP
2006-032749 Feb 2006 JP
2006-033723 Feb 2006 JP
2006-253559 Sep 2006 JP
2007-036218 Feb 2007 JP
2007-215331 Aug 2007 JP
2008-199771 Aug 2008 JP
2010-087076 Apr 2010 JP
2010-539712 Dec 2010 JP
200924068 Jun 2009 TW
200924201 Jun 2009 TW
200947703 Nov 2009 TW
201010076 Mar 2010 TW
201027759 Jul 2010 TW
201027912 Jul 2010 TW
201036155 Oct 2010 TW
WO 2004070791 Aug 2004 WO
WO 2004098060 Nov 2004 WO
WO 2005070007 Aug 2005 WO
WO 2005070009 Aug 2005 WO
WO 2006114883 Nov 2006 WO
WO 2007077666 Jul 2007 WO
WO 2007108404 Sep 2007 WO
WO 2008120094 Oct 2008 WO
WO 2009036181 Mar 2009 WO
WO 2009036266 Mar 2009 WO
WO 2009039028 Mar 2009 WO
WO 2009039041 Mar 2009 WO
WO 2009076076 Jun 2009 WO
WO 2009132039 Oct 2009 WO
WO 2010039463 Apr 2010 WO
WO 2010068554 Jun 2010 WO
WO 2010090885 Aug 2010 WO
WO 2010132587 Nov 2010 WO
WO 2011031431 Mar 2011 WO
WO 2011072027 Jun 2011 WO
Non-Patent Literature Citations (98)
Entry
Authorized officer Chung Keun Lee, International Search Report and Written Opinion in PCT/US2008/076030, mailed Mar. 23, 2009, 10 pages.
Authorized officer Yolaine Cussac, International Preliminary Report on Patentability in PCT/US2008/076030, Mar. 25, 2010, 5 pages.
Authorized officer Chung Keun Lee, International Search Report and Written Opinion in PCT/US2008/076079, mailed Mar. 20, 2009, 11 pages.
Authorized officer Nora Lindner, International Preliminary Report on Patentability in PCT/US2008/076079, mailed Apr. 1, 2010, 6 pages.
Authorized officer Keon Hyeong Kim, International Search Report and Written Opinion in PCT/US2008/076160 mailed Mar. 18, 2009, 11 pages.
Authorized officer Chung Keun Lee, International Search Report and Written Opinion in PCT/US2008/076199, mailed Mar. 24, 2009, 11 pages.
Authorized officer Dorothée Mülhausen, International Preliminary Report on Patentability in PCT/US2008/076199, mailed Apr. 1, 2010, 6 pages.
Authorized officer Keon Hyeong Kim, International Search Report and Written Opinion in PCT/US2008/085031, mailed Jun. 24, 2009, 11 pages.
Authorized officer Yolaine Cussac, International Preliminary Report on Patentability in PCT/US2008/085031, mailed Jun. 24, 2010, 6 pages.
Authorized officer Tae Hoon Kim, International Search Report and Written Opinion in PCT/US2009/041304, mailed Dec. 18, 2009, 13 pages.
Authorized officer Dorothée Mülhausen, International Preliminary Report on Patentability, in PCT/US2009/041304, mailed Nov. 4, 2010, 8 pages.
Authorized officer Sung Hee Kim, International Search Report and the Written Opinion in PCT/US2009/057554, mailed May 10, 2010, 13 pages.
Authorized Officer Gijsbertus Beijer, International Preliminary Report on Patentability in PCT/US2009/057554, mailed Mar. 29, 2011, 7 pages.
Authorized officer Cheon Whan Cho, International Search Report and Written Opinion in PCT/US2009/066647, mailed Jul. 1, 2010, 16 pages.
Authorized officer Athina Nikitas-Etienne, International Preliminary Report on Patentability in PCT/US2009/066647, mailed Jun. 23, 2011, 12 pages.
Authorized officer Sung Chan Chung, International Search Report and Written Opinion for PCT/US2010/021824, mailed Aug. 23, 2010, 9 pages.
Authorized officer Sang Ho Lee, International Search Report and Written Opinion in PCT/US2010/034579, mailed Dec. 24, 2010, 9 pages.
Authorized officer Nora Lindner, International Preliminary Report on Patentability in PCT/US2010/034579, mailed Nov. 24, 2011, 7 pages.
Authorized officer Jeongmin Choi, International Search Report and Written Opinion in PCT/US2010/046193, mailed Apr. 26, 2011, 13 pages.
Authorized officer Philippe Bécamel, International Preliminary Report on Patentability in PCT/US2010/046193, mailed Mar. 8, 2012, 10 pages.
Authorized officer Sang Ho Lee, International Search Report and Written Opinion in PCT/US2010/059486, mailed Jul. 26, 2011, 9 pages.
Authorized officer Nora Lindner, International Preliminary Report on Patentability in PCT/US2010/059486, mailed Jun. 21, 2012, 6 pages.
Authorized officer Kwan Sik Sul, International Search Report and Written Opinion in PCT/US2011/063975, mailed May 18, 2012, 8 pages.
Authorized officer Sang-Taek Kim, International Search Report and Written Opinion in PCT/US2011/061407, mailed May 22, 2012, 10 pages.
Authorized officer Kwan Sik Sul, International Search Report and Written Opinion in PCT/US2012/023160, mailed May 24, 2012, 9 pages.
Authorized officer Jeongmin Choi, International Search Report and Written Opinion in PCT/US2012/027146, mailed Sep. 24, 2012, 12 pages.
Authorized officer Athina Nickitas-Etienne, International Preliminary Report on Patentability in PCT/US2012/027146, mailed Sep. 19, 2013, 9 pages.
Authorized officer Tae Hoon Kim, International Search Report and Written Opinion in PCT/US2013/035837, mailed Jul. 30, 2013, 9 pages.
European Search Report in Application No. 10 81 5813.0, mailed Mar. 13, 2012, 9 pages.
Search Report and Action in TW Application No. 098132132, issued Dec. 6, 2012, 8 pages.
Chinese First Office Action for Application No. 200880120050.6, Aug. 2, 2011, 8 pages.
Chinese First Office Action for Application No. 200980114639.X, May 14, 2012, 13 pages.
Chinese First Office Action for Application No. 201080030524.5, Oct. 28, 2013, 11 pages.
Ando et al., “10-W/mm AlGaN—GaN HFET with a Field Modulating Plate,” IEEE Electron Device Letters, 2003, 24(5):289-291.
Arulkumaran et al., “Enhancement of Breakdown Voltage by AlN Buffer Layer Thickness in AlGaN/GaN High-electron-mobility Transistors on 4 in. Diameter Silicon,” Applied Physics Letters, 2005, 86:123503-1-3.
Arulkumaran et al. “Surface Passivation Effects on AlGaN/GaN High-Electron-Mobility Transistors with SiO2, Si3N4, and Silicon Oxynitride,” Applied Physics Letters, 2004, 84(4):613-615.
Barnett and Shinn, “Plastic and Elastic Properties of Compositionally Modulated Thin Films,” Annu. Rev. Mater. Sci., 1994, 24:481-511.
Chen et al., “High-performance AlGaN/GaN Lateral Field-effect Rectifiers Compatible with High Electron Mobility Transistors,” Applied Physics Letters, 2008, 92, 253501-1-3.
Cheng et al., “Flat GaN Epitaxial Layers Grown on Si(111) by Metalorganic Vapor Phase Epitaxy Using Step-graded AlGaN Intermediate Layers,” Journal of Electronic Materials, 2006, 35(4):592-598.
Coffie, “Characterizing and Suppressing DC-to-RF Dispersion in AlGaN/GaN High Electron Mobility Transistors,” 2003, PhD Thesis, University of California, Santa Barbara, 169 pages.
Coffie et al., “Unpassivated p-GaN/AlGaN/GaN HEMTs with 7.1 W/mm at 10 GhZ,” Electronic Letters, 2003, 39(19):1419-1420.
Chu et al., “1200-V Normally Off GaN-on-Si Field-effect Transistors with Low Dynamic On-Resistance,” IEEE Electron Device Letters, 2011, 32(5):632-634.
Dora et al., “High Breakdown Voltage Achieved on AlGaN/GaN HEMTs with Integrated Slant Field Plates,” IEEE Electron Device Letters, 2006, 27(9):713-715.
Dora et al., “ZrO2 Gate Dielectrics Produced by Ultraviolet Ozone Oxidation for GaN and AlGaN/GaN Transistors,” J. Vac. Sci. Technol. B, 2006, 24(2)575-581.
Dora, “Understanding Material and Process Limits for High Breakdown Voltage AlGaN/GaN HEMTs,” PhD Thesis, University of California, Santa Barbara, Mar. 2006, 157 pages.
Fanciulli et al., “Structural and Electrical Properties of HfO2 Films Grown by Atomic Layer Deposition on Si, Ge, GaAs and GaN,” Mat. Res. Soc. Symp. Proc., 2004, vol. 786, 6 pages.
Green et al., “The Effect of Surface Passivation on the Microwave Characteristics of Undoped AlGaN/GaN HEMT's,” IEEE Electron Device Letters, 2000, 21(6):268 270.
Gu et al., “AlGaN/GaN MOS Transistors using Crystalline ZrO2 as Gate Dielectric,” Proceedings of SPIE, 2007, vol. 6473, 64730S-1-8.
Higashiwaki et al. “AlGaN/GaN Heterostructure Field-Effect Transistors on 4H-SiC Substrates with Current-Gain Cutoff Frequency of 190 GHz,” Applied Physics Express, 2008, 021103-1-3.
Hwang et al., “Effects of a Molecular Beam Epitaxy Grown AlN Passivation Layer on AlGaN/GaN Heterojunction Field Effect Transistors,” Solid-State Electronics, 2004, 48:363-366.
Im et al., “Normally Off GaN MOSFET Based on AlGaN/GaN Heterostructure with Extremely High 2DEG Density Grown on Silicon Substrate,” IEEE Electron Device Letters, 2010, 31(3):192-194.
Karmalkar and Mishra, “Enhancement of Breakdown Voltage in AlGaN/GaN High Electron Mobility Transistors Using a Field Plate,” IEEE Transactions on Electron Devices, 2001, 48(8):1515-1521.
Karmalkar and Mishra, “Very High Voltage AlGaN/GaN High Electron Mobility Transistors Using a Field Plate Deposited on a Stepped Insulator,” Solid-State Electronics, 2001, 45:1645-1652.
Keller et al., “GaN-GaN Junctions with Ultrathin AlN Interlayers: Expanding Heterojunction Design.” Applied Physics Letters, 2002, 80(23):4387-4389.
Keller et al., “Method for Heteroepitaxial Growth of High Quality N-Face GaN, InN and AlN and their Alloys by Metal Organic Chemical Vapor Deposition,” U.S. Appl. No. 60/866,035, filed Nov. 15, 2006, 31 pages.
Khan et al., “AlGaN/GaN Metal Oxide Semiconductor Heterostructure Field Effect Transistor,” IEEE Electron Device Letters, 2000, 21(2):63-65.
Kim, “Process Development and Device Characteristics of AlGaN/GaN HEMTs for High Frequency Applications,” PhD Thesis, University of Illinois at Urbana-Champaign, 2007, 120 pages.
Kumar et al., “High Transconductance Enhancement-mode AlGaN/GaN HEMTs on SiC Substrate,” Electronics Letters, 2003, 39(24):1758-1760.
Kuraguchi et al., “Normally-off GaN-MISFET with Well-controlled Threshold Voltage,” Phys. Stats. Sol., 2007, 204(6):2010-2013.
Lanford et al., “Recessed-gate Enhancement-mode GaN HEMT with High Threshold Voltage,” Electronic Letters, 2005, 41(7):449-450.
Lee et al., “Self-aligned Process for Emitter- and Base-regrowth GaN HBTs and BJTs,” Solid-State Electronics, 2001, 45:243-247.
Marchand et al., “Metalorganic Chemical Vapor Deposition on GaN on Si(111): Stress Control and Application to Filed-effect Transistors,” Journal of Applied Physics, 2001, 89(12):7846-7851.
Mishra et al., “N-face High Electron Mobility Transistors with Low Buffer Leakage and Low Parasitic Resistance,” U.S. Appl. No. 60/908,914, filed Mar. 29, 2007, 21 pages.
Mishra et al., “Polarization-induced Barriers for N-face Nitride-based Electronics,” U.S . Appl. No. 60/940,052, filed May 24, 2007, 29 pages.
Mishra et al., “Growing N-polar III-nitride structures,” U.S. Appl. No. 60/972,467, filed Sep. 14, 2007, 7 pages.
Mishra et al., “AlGaN/GaN HEMTs—An Overview of Device Operation and Applications,” Proceedings of the IEEE, 2002, 90(6):1022-1031.
Nanjo et al., “Remarkable Breakdown Voltage Enhancement in AlGaN Channel High Electron Mobility Transistors,” Applied Physics Letters 92 (2008), 3 pages.
Napierala et al., “Selective GaN Epitaxy on Si(111) Substrates Using Porous Aluminum Oxide Buffer Layers,” Journal of the Electrochemical Society, 2006. 153(2):G125-G127, 4 pages.
Ota and Nozawa, “AlGaN/GaN Recessed MIS-gate HFET with High-threshold-voltage Normally-off Operation for Power Electronics Applications,” IEEE Electron Device Letters, 2008, 29(7):668-670.
Palacios et al., “AlGaN/GaN HEMTs with an InGaN-based Back-barrier,” Device Research Conference Digest, 2005, DRC '05 63rd, pp. 181-182.
Palacios et al., “AlGaN/GaN High Electron Mobility Transistors with InGaN Back-Barriers,” IEEE Electron Device Letters, 2006, 27(1):13-15.
Palacios et al., “Fluorine Treatment to Shape the Electric Field in Electron Devices, Passivate Dislocations and Point Defects, and Enhance the Luminescence Efficiency of Optical Devices,” U.S. Appl. No. 60/736,628, filed Nov. 15, 2005, 21 pages.
Palacios et al., “Nitride-based High Electron Mobility Transistors with a GaN Spacer,” Applied Physics Letters, 2006, 89:073508-1-3.
Pei et al., “Effect of Dielectric Thickness on Power Performance of AlGaN/GaN HEMTs,” IEEE Electron Device Letters, 2009, 30(4):313-315.
“Planar, Low Switching Loss, Gallium Nitride Devices for Power Conversion Applications,” SBIR N121-090 (Navy), 3 pages.
Rajan et al., “Advanced Transistor Structures Based on N-face GaN,” 32M International Symposium on Compound Semiconductors (ISCS), Sep. 18-22, 2005, Europa-Park Rust, Germany, 2 pages.
Reiher et al., “Efficient Stress Relief in GaN Heteroepitaxy on Si(111) Using Low-temperature AlN Interlayers,” Journal of Crystal Growth, 2003, 248:563-567.
Saito et al., “Recessed-gate Structure Approach Toward Normally Off High-voltage AlGaN/GaN HEMT for Power Electronics Applications,” IEEE Transactions on Electron Device, 2006, 53(2):356-362.
Shelton et al., “Selective Area Growth and Characterization of AlGaN/GaN Heterojunction Bipolar Transistors by Metalorganic Chemical Vapor Deposition,” IEEE Transactions on Electron Devices, 2001, 48(3):490-494.
Shen, “Advanced Polarization-based Design of AlGaN/GaN HEMTs,” Jun. 2004, PhD Thesis, University of California, Santa Barbara, 192 pages.
Sugiura et al., “Enhancement-mode n-channel GaN MOSFETs Fabricated on p-GaN Using HfO2 as Gate Oxide,” Electronics Letters, 2007, vol. 43, No. 17, 2 pages.
Suh et al., “High Breakdown Enhancement Mode GaN-based HEMTs with Integrated Slant Field Plate,” U.S. Appl. No. 60/822,886, filed Aug. 18, 2006, 16 pages.
Suh et al. “High-Breakdown Enhancement-mode AlGaN/GaN HEMTs with Integrated Slant Field-Plate,” Electron Devices Meeting, 2006, IEDM '06 International, 3 pages.
Suh et al., “III-Nitride Devices with Recessed Gates,” U.S. Appl. No. 60/972,481, filed Sep. 14, 2007, 18 pages.
Tipirneni et al. “Silicon Dioxide-encapsulated High-Voltage AlGaN/GaN HFETs for Power-Switching Applications,” IEEE Electron Device Letters, 2007, 28(9):784-786.
Vetury et al., “Direct Measurement of Gate Depletion in High Breakdown (405V) Al/GaN/GaN Heterostructure Field Effect Transistors,” IEDM 98, 1998, pp. 55-58.
Wang et al., “Comparison of the Effect of Gate Dielectric Layer on 2DEG Carrier Concentration in Strained AlGaN/GaN Heterostructure,” Mater. Res. Soc. Symp. Proc., 2007, vol. 831, 6 pages.
Wang et al., “Enhancement-mode Si3N4/AlGaN/GaN MISHFETs,” IEEE Electron Device Letters, 2006, 27(10):793-795.
Wu, “AlGaN/GaN Microwave Power High-Mobility Transistors,” PhD Thesis, University of California, Santa Barbara, Jul. 1997, 134 pages.
Wu et al., “A 97.8% Efficient GaN HEMT Boost Converter with 300-W Output Power at 1MHz,”Electronic Device Letters, 2008, IEEE, 29(8):824-826.
Yoshida, “AlGan/GaN Power FET,” Furukawa Review, 2002, 21:7-11.
Zhang, “High Voltage GaN HEMTs with Low On-resistance for Switching Applications,” PhD Thesis, University of California, Santa Barbara, Sep. 2002, 166 pages.
Zhanghong Content, Shanghai Institute of Metallurgy, Chinese Academy of Sciences, “Two-Dimensional Electron Gas and High Electron Mobility Transistor (HEMT),” Dec. 31, 1984, 17 pages.
Authorized officer Simin Baharlou, International Preliminary Report on Patentability in PCT/US2008/076160, mailed Mar. 25 2010, 6 pages.
Authorized officer Beate Giffo-Schmitt, International Preliminary Report on Patentability in PCT/US2010/021824, mailed Aug. 18, 2011, 6 pages.
Authorized officer Lingfei Bai, International Preliminary Report on Patentability in PCT/US2011/061407, mailed Jun. 6, 2013, 7 pages.
Authorized officer Simin Baharlou, International Preliminary Report on Patentability in PCT/US2011/063975, mailed Jun. 27, 2013, 5 pages.
Authorized officer Simin Baharlou, International Preliminary Report on Patentability in PCT/US2012/023160, mailed Aug. 15, 2013, 6 pages.
Related Publications (1)
Number Date Country
20140342512 A1 Nov 2014 US
Continuations (1)
Number Date Country
Parent 12465968 May 2009 US
Child 14262649 US