Patent Application
20170330827
Various surface mount module form factors are commercially available. These form factors are typically based on either castellated edge pad patterns, or land grid array pad patterns. In such cases where both pad patterns are present, these are simply offering the different pads for mixed signal use, without pad subset mapping to the land grid array pads.
In one aspect, this disclosure is directed to addressing the problem of providing a unified surface mount (SMT) module platform decision for: a more complex but more versatile land grid array based module, vs. an easy-to-use but more limited castellated edge module.
A surface mount module form factor comprises a substrate having a bottom surface, a top surface, and an outer periphery, with at least one electronic component mounted on the substrate, and a plurality of land grid array pads mounted on the bottom surface of the substrate. At least some of the land grid array pads are coupled to the at least one electronic component. A plurality of castellated edge pads are mounted around the outer periphery of the substrate, with at least some of the castellated edge pads coupled to the at least one electronic component. At least some of the land grid array pads are mapped to at least some of the castellated edge pads.
Features of the present invention will become apparent to those skilled in the art from the following description with reference to the drawings. Understanding that the drawings depict only typical embodiments and are not therefore to be considered limiting in scope, the invention will be described with additional specificity and detail through the use of the accompanying drawings, in which:
In the following detailed description, embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. It is to be understood that other embodiments may be utilized without departing from the scope of the invention. The following detailed description is, therefore, not to be taken in a limiting sense.
A hybrid embedded surface mount module form factor is disclosed, in which same signal source subset mapping is provided. The surface mount module form factor combines two distinct integration techniques, utilizing shared pinouts, to provide a low-profile and cost-effective platform for mounting various electronic components.
In one embodiment, the surface mount module form factor comprises one or more electronic components mounted on a substrate, a plurality of land grid array pads on the substrate, and a plurality of castellated edge pads around a periphery of the substrate. At least some of the land grid array pads are coupled to the electronic components, and at least some of the castellated edge pads are also coupled to the electronic components. In addition, at least some of the outer land grid array pads are directly mapped to at least some of the castellated edge pads.
The direct mapping of the outer land grid array pads to the castellated edge pads allows sharing of a common subset of signals from the same source, greatly simplifying implementation of the surface mount module form factor and common software platform support. This technique also delivers a universal form factor platform, without compromising time-to-market, design flexibility, optimized assembly cost, and overall cost of goods.
The present approach provides two distinct methods of integrating various electronic components, including single function, multi-function, or system-on-module components, in a common surface mount (SMT) module form factor. By providing both high density land grid array pads and castellated edge pads, the present form factor allows for direct attachment to a carrier printed circuit board (PCB) without any connectors, as well as selecting for the most cost-effective and fastest design and assembly method. In addition, the same module form factor platform can be used in a wide variety of designs and applications.
Embodiments using the present approach may offer a number of advantages, including: simplified manufacturing or assembly options across low and high volume builds; designs for fully automated component pick-and-place manufacturing; more cost-effective and lower carrier PCB layer count using castellated edge pads; and castellated edge pads allowing for manual placement (prototyping, etc.). In addition, the land grid array pads offer complete pinout for complex designs; the castellated edge pads offer exact same-source subset of pinout for simplified design integration; and the castellated edge pads are directly mapped to outer land grid array pads to deliver a subset of functionality.
Other benefits of the present approach include no board connector cost, and no board connector supply dependency; highly reliable low-profile surface mount assembly; one form factor platform suitable for a wide array of designs; an optional cavity for bottom module components that eliminate the need for a carrier PCB routing pattern; and unified software platform support regardless of the integration method used.
Further details of the various embodiments are described hereafter with reference to the drawings.
As shown in
The form factor 100 supports the optional placement of electronic components 140 in cavity 116, providing a flat configuration for bottom surface 112. This flat configuration eliminates the need for a routing pattern in a mating carrier PCB for form factor 100.
As shown in the bottom view of
As depicted in
The form factor 200 supports the placement of various electronic components 240, 242, 244 in cavity 216, providing a flat configuration for bottom surface 212. The electronic components can include memory devices, processors, communication devices, or the like.
As shown in the top view of
The form factor 200 also supports the placement of various electronic components 250, 252, 254 on top surface 252. The electronic components can include processors, memory devices, communication devices, or the like.
As depicted in the top view of
The techniques described herein can be implemented in an embedded system-on-module product, which employs the present surface mount module form factor. One example of such a product is illustrated in
The communication platform 300 can include a plurality of system control components 320, such as for secure JTAG, a phase lock loop (PLL), an oscillator, a real-time clock (RTC) and reset, smart direct memory access (DMA), IOMUX, timer, and pulse width modulation (PWM) circuit; power management components 324, such as low drop out (LDO) regulator, and a temperature monitor; a CPU platform 328 for a microprocessor and various processing components; multimedia components 332, such as CSC, combine, rotate, programmable, processing engine, parallel CSI, and parallel LCD; external memory components 336, such as NOR flash, dual-channel quad serial peripheral interface (SPI), and SDRAM; internal memory components 340, such as ROM and RAM; security components 348, such as ciphers, a random number generator (RNG), and eFuse; and address conflict detection (ACD) software 350. Additional components on communications platform 300 can include connectivity components 352, such as for a universal asynchronous receiver/transmitter (UART), general purpose input/output (GPIO), S/PDIF transmitter/receiver, USB, Ethernet, keypad, and the like; a security and authentication controller 356; a microcontroller 358; wireless communication components 360 such as for WiFi (802.11), Bluetooth, or the like; a power management integrated circuit (PMIC) 364; and additional memory components 368 such as NAND flash and SDRAM.
Example 1 includes a surface mount module form factor, comprising: a substrate having a bottom surface, a top surface, and an outer periphery; at least one electronic component mounted on the substrate; a plurality of land grid array pads mounted on the bottom surface of the substrate, wherein at least some of the land grid array pads are coupled to the at least one electronic component; and a plurality of castellated edge pads mounted around the outer periphery of the substrate, wherein at least some of the castellated edge pads are coupled to the at least one electronic component; wherein at least some of the land grid array pads are mapped to at least some of the castellated edge pads.
Example 2 includes the surface mount module form factor of Example 1, wherein the at least one electronic component comprises at least one single function component.
Example 3 includes the surface mount module form factor of any of Examples 1-2, wherein the at least one electronic component comprises at least one multi-function component.
Example 4 includes the surface mount module form factor of any of Examples 1-3, wherein the at least one electronic component comprises at least one system-on-module component.
Example 5 includes the surface mount module form factor of any of Examples 1-4, wherein the at least one electronic component is mounted on the top surface of the substrate.
Example 6 includes the surface mount module form factor of any of Examples 1-5, further comprising a cavity in the bottom surface of the substrate, wherein the at least one electronic component is mounted inside of the cavity.
Example 7 includes the surface mount module form factor of Example 6, further comprising one or more additional electronic components mounted on the top surface of the substrate.
Example 8 includes the surface mount module form factor of any of Examples 1-7, further comprising a top shield plate mounted over the top surface of the substrate.
Example 9 includes the surface mount module form factor of any of Examples 1-8, wherein the land grid array pads are mapped to the castellated edge pads to provide a same-source subset of the land grid array pads.
Example 10 includes the surface mount module form factor of any of Examples 1- 9, wherein outer land grid array pads are mapped to the castellated edge pads with respective common pins.
Example 11 includes the surface mount module form factor of any of Examples 1-10, wherein the at least one electronic component comprises one or more of a processor, a memory device, or a communication device.
Example 12 includes a communication platform, comprising: a surface mount module form factor comprising: a substrate having a bottom surface, a top surface, and an outer periphery; a plurality of land grid array pads mounted on the bottom surface of the substrate; and a plurality of castellated edge pads mounted around the outer periphery of the substrate; wherein at least some of the land grid array pads are mapped to at least some of the castellated edge pads; and a plurality of electronic components mounted on the substrate; wherein the land grid array pads mapped to the castellated edge pads are coupled to the electronic components.
Example 13 includes the communication platform of Example 12, wherein one or more of the electronic components are mounted on the top surface of the substrate.
Example 14 includes the communication platform of any of Examples 12-13, further comprising a cavity in the bottom surface of the substrate, wherein one or more of the electronic components are mounted inside of the cavity.
Example 15 includes the communication platform of any of Examples 12-14, further comprising a top shield plate mounted over the top surface of the substrate.
Example 16 includes the communication platform of any of Examples 12-15, wherein the land grid array pads are mapped to the castellated edge pads to provide a same-source subset of the land grid array pads.
Example 17 includes the communication platform of any of Examples 12-16, wherein outer land grid array pads are mapped to the castellated edge pads with respective common pins.
Example 18 includes the communication platform of any of Examples 12-17, wherein the electronic components comprise a processor, a memory device, and a communication device.
A number of embodiments of the invention defined by the following claims have been described. Nevertheless, it will be understood that various modifications to the described embodiments may be made without departing from the scope of the claimed invention. Accordingly, other embodiments are within the scope of the following claims.
This application claims the benefit of priority to U.S. Provisional Application No. 62/335,494, filed on May 12, 2016, the disclosure of which is incorporated by reference.
| Number | Date | Country | |
|---|---|---|---|
| 62335494 | May 2016 | US |
