Patent Application
20210257299
The present application relates to back-end-of-the-line (BEOL) technology, and more particularly to a BEOL interconnect structure that includes a hybrid metal-containing electrically conductive structure of a first critical dimension and a copper-containing electrically conductive structure of a second critical dimension greater than the first critical dimension, both of which are embedded in a same interconnect dielectric material layer.
Generally, semiconductor devices include a plurality of circuits which form an integrated circuit fabricated on a semiconductor substrate. A complex network of signal paths will normally be routed to connect the circuit elements distributed on the surface of the substrate. Efficient routing of these signals across the device requires formation of multilevel or multilayered schemes, such as, for example, single or dual damascene wiring, i.e., interconnect, structures.
Within typical interconnect structures, electrically conductive metal vias run perpendicular to the semiconductor substrate and electrically conductive metal lines run parallel to the semiconductor substrate. In conventional interconnect structures, copper or a copper containing alloy has been used as the material of the electrically conductive metal structure.
As the feature size gets smaller and smaller, the interconnect resistance increases and becomes an issue. For example, small feature sizes can lead to a decreased conducting cross sectional area, a decreased copper volume fraction and/or an increased copper resistivity induced by electron scatterings. When a small feature size electrically conductive structure and a wide feature size electrically conductive structure are to be integrated in a same interconnect dielectric material layer, a comprehensive solution of materials, integration and layouts is needed to address the resistance tradeoffs between the narrow features and the wide features.
In one aspect of the present application, a back-end-of-the-line (BEOL) interconnect structure is provided. In one embodiment of the present application, the BEOL interconnect structure includes a hybrid metal-containing electrically conductive structure and a copper-containing electrically conductive structure embedded in an interconnect dielectric material layer. The hybrid metal-containing electrically conductive structure has a first critical dimension and includes a diffusion barrier liner and a hybrid metal-containing region. The copper-containing electrically conductive structure has a second critical dimension that is greater than the first critical dimension and includes a first diffusion barrier liner, a hybrid metal-containing liner, a second diffusion barrier liner and a copper-containing region. In accordance with the present application, the hybrid metal-containing region and the hybrid metal-containing liner are compositionally the same and include a metal or metal alloy that has a higher bulk resistivity than copper. Bulk resistivity (or volume resistivity) is a constant value for a certain material at a certain environment (typically measured at 21° C.). The bulk resistivity is a measure of the resistivity across a defined thickness of the material.
In some embodiments, the diffusion barrier liner is omitted from the hybrid metal-containing electrically conductive structure, and the first diffusion barrier liner is omitted from the copper-containing electrically conductive structure. In such an embodiment, the entirety of the hybrid metal-containing electrically conductive structure is composed of the hybrid metal-containing region, and the copper-containing electrically conductive structure is composed of the hybrid metal-containing liner, the second diffusion barrier liner and the copper-containing region.
In another aspect of the present application, a method of forming a back-end-of-the-line (BEOL) interconnect structure is provided. In one embodiment of the present application, the method includes forming an interconnect dielectric material layer that contains at least one first opening having a first critical dimension and at least one second opening having a second critical dimension that is greater than the first critical dimension. A first diffusion barrier layer is then formed on the interconnect dielectric material layer and within both the at least one first opening and the at least one second opening. Next, a hybrid metal-containing layer is formed on the first diffusion barrier layer, wherein the hybrid metal-containing layer completely fills in the at least one first opening, while partially filling the at least one second opening. A second diffusion barrier layer is then formed on the hybrid metal-containing layer, and thereafter a copper-containing layer is formed on the second diffusion barrier layer. A planarization process is then performed to remove the copper-containing layer, the second diffusion barrier layer, the hybrid metal-containing layer, and the first diffusion barrier layer that are present on the interconnect dielectric material layer, while maintaining the hybrid metal-containing layer and the first diffusion barrier layer in the at least one first opening and maintaining the copper-containing layer, the second diffusion barrier layer, the hybrid metal-containing layer and the first diffusion barrier layer in the at least one second opening. In some embodiments, the forming of the first diffusion barrier layer can be omitted.
The present application will now be described in greater detail by referring to the following discussion and drawings that accompany the present application. It is noted that the drawings of the present application are provided for illustrative purposes only and, as such, the drawings are not drawn to scale. It is also noted that like and corresponding elements are referred to by like reference numerals.
In the following description, numerous specific details are set forth, such as particular structures, components, materials, dimensions, processing steps and techniques, in order to provide an understanding of the various embodiments of the present application. However, it will be appreciated by one of ordinary skill in the art that the various embodiments of the present application may be practiced without these specific details. In other instances, well-known structures or processing steps have not been described in detail in order to avoid obscuring the present application.
It will be understood that when an element as a layer, region or substrate is referred to as being “on” or “over” another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “beneath” or “under” another element, it can be directly beneath or under the other element, or intervening elements may be present. In contrast, when an element is referred to as being “directly beneath” or “directly under” another element, there are no intervening elements present.
Referring first to
The exemplary structure shown in
The interconnect dielectric material layer 10 can be composed of an inorganic dielectric material and/or an organic dielectric material. In some embodiments, the interconnect dielectric material layer 10 can be porous. In other embodiments, the interconnect dielectric material layer 10 can be non-porous. Examples of suitable dielectric materials that can be employed as the interconnect dielectric material layer 10 include, but are not limited to, silicon dioxide, undoped or doped silicate glass, silsesquioxanes, C doped oxides (i.e., organosilicates) that include atoms of Si, C, O and H, theremosetting polyarylene ethers or any multilayered combination thereof. The term “polyarylene” is used in this present application to denote aryl moieties or inertly substituted aryl moieties which are linked together by bonds, fused rings, or inert linking groups such as, for example, oxygen, sulfur, sulfone, sulfoxide, or carbonyl.
The interconnect dielectric material layer 10 can have a dielectric constant (all dielectric constants mentioned herein are measured relative to a vacuum, unless otherwise stated) that is about 4.0 or less. In one embodiment, the interconnect dielectric material layer 10 has a dielectric constant of 2.8 or less. These dielectrics generally having a lower parasitic cross talk as compared to dielectric materials whose dielectric constant is greater than 4.0.
The interconnect dielectric material layer 10 can be formed by a deposition process such as, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD) or spin-on coating. The interconnect dielectric material layer 10 can have a thickness from 50 nm to 250 nm. Other thicknesses that are lesser than 50 nm, and greater than 250 nm can also be employed in the present application as the thickness of the interconnect dielectric material layer 10.
After providing the interconnect dielectric material layer 10, the at least one first opening 12 having the first critical dimension (CD-1) and the at least one second opening 14 having the second critical dimension (CD-2) that is greater than the first critical dimension (CD-1) are formed into the interconnect dielectric material layer 10. The at least one first opening 12 and the at least one second opening 14 can be formed utilizing one or more patterning processes. The one or more patterning processes can include lithography and etching, sidewall image transfer (SIT), or a direct self-assembly (DSA) process. In some embodiments, the at least one first opening 12 and the at least one second opening 14 are formed at the same time using a same patterning process. In another embodiment, the at least one first opening 12 can be formed prior to, or after, forming the at least one second opening 14. In the present application, each first opening 12 is spaced apart from a neighboring first opening 12 and each second opening 14 is spaced apart from a neighboring second opening 14. Also, and in the present application, the first and second openings are spaced apart from each other.
In one embodiment of the present application and as is shown in
As mentioned above, the at least one first opening 12 has a first critical dimension (CD-1) and the at least one second opening 14 has a second critical dimension (CD-2) that is greater than the first critical dimension (CD-1). In one embodiment of the present application, the second critical dimension (CD-2) of each second opening 14 is two times greater than the first critical dimension (CD-1) of each first opening 12. In one example, the first critical dimension (CD-1) is from 5 nm to 80 nm, and the second critical dimension (CD-2) is two times greater than the first critical dimension (CD-1). In the at least one first opening 12 having the first critical dimension (CD-1) copper fill needs to be avoided so as to circumvent increased resistivity in the small size openings.
Thus, and in the present application, each first opening 12 will house a hybrid metal-containing-containing electrically conductive structure having the first critical dimension (CD-1), and each second opening 14 will house a copper-containing electrically conductive structure having the second critical dimension (CD-2).
Referring now to
The first diffusion barrier layer 16 is composed of a diffusion barrier material (e.g., metal, metal alloy or metal nitride) that prevents a conductive material from diffusing there through. Exemplary diffusion barrier materials include tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), ruthenium (Ru), ruthenium nitride (RuN), an alloy of Ru—Ta, RuTaN, tungsten (W), or tungsten nitride (WN). The thickness of the first diffusion barrier layer 16 can vary depending on the deposition process used as well as the material employed. In some embodiments, the first diffusion barrier layer 16 can have a thickness from 0.3 nm to 50 nm; although other thicknesses for the first diffusion barrier layer 16 are contemplated and can be employed in the present application as long as the first diffusion barrier layer 16 does not entirely fill the at least one first opening 12 and the at least one second opening 14 that are formed into the interconnect dielectric material layer 10. The first diffusion barrier layer 16 can be formed by a deposition process including, for example, CVD, PECVD, atomic layer deposition (ALD), physical vapor deposition (PVD), sputtering, chemical solution deposition or plating.
Referring now to
In one embodiment, the hybrid metal-containing layer 18 can be formed by a deposition process including, for example, CVD, PECVD, PVD or ALD. In another embodiment, the hybrid metal-containing layer 18 can be formed by a reflow process. A reflow process is a process in which a material is first deposited and then the deposited material is subjected to a reflow anneal that melts the material. The melted material flows into openings present in another material by capillary force/surface tension.
Because of the narrow dimension of the at least one first opening 12, the hybrid metal-containing layer 18 completely fills in the at least one first opening 12. Because of the wide dimension of the at least one second opening 14, the hybrid metal-containing layer 18 only partially fills the at least one second opening 14. In the at least one second opening 14, the deposited hybrid metal-containing layer 18 can have a thickness from 6 nm to 120 nm.
Referring now to
The second diffusion barrier layer 20 is composed of a diffusion barrier material (e.g., metal, metal alloy or metal nitride) that prevents a conductive material from diffusing there through. The diffusion barrier material that provides the second diffusion barrier layer 20 can be compositionally the same as, or compositionally different from, the diffusion barrier material that provided the first diffusion barrier layer 16. Exemplary diffusion barrier materials that can be used as the second diffusion barrier layer 20 include tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), ruthenium (Ru), ruthenium nitride (RuN), an alloy of Ru—Ta, RuTaN, tungsten (W), or tungsten nitride (WN). The thickness of the second diffusion barrier layer 20 can vary depending on the deposition process used as well as the material employed. In some embodiments, the second diffusion barrier layer 20 can have a thickness from 2 nm to 25 nm; although other thicknesses for the second diffusion barrier layer 20 are contemplated and can be employed in the present application as long as the second diffusion barrier layer 20 does not entirely fill the at least one second opening 14 that is formed into the interconnect dielectric material layer 10; the at least one first opening 12 is entirely filled with the first diffusion barrier layer 16 and the hybrid metal-containing layer 18 at this point of the present application. The second diffusion barrier layer 20 can be formed utilizing one of the deposition processes mentioned above in forming the first diffusion barrier layer 16.
Referring now to
Referring now to
The hybrid metal-containing layer 18 that is maintained in the at least one first opening 12 can be referred to herein as a hybrid metal-containing region 18S, while the first diffusion barrier layer 16 that is maintained in the at least one first opening 12 can be referred to herein as a diffusion barrier liner 16L. Collectively, the diffusion barrier liner 16L and the hybrid metal-containing region 18S that are present in the at least one first opening 12 provide a hybrid metal-containing electrically conductive structure that has the first critical dimension (CD-1) mentioned above. The hybrid metal-containing electrically conductive structure excludes a copper-containing region as well as another diffusion barrier liner.
As is shown in
The copper-containing layer 22 that is maintained in the at least one second opening 14 can be referred to a copper-containing region 22S, the second diffusion barrier layer 20 that is maintained in the at least one second opening 14 can be referred to as a second diffusion barrier liner 20L, the hybrid metal-containing layer 18 that is maintained in the at least one second opening 14 can be referred as a hybrid metal-containing liner 18L, while the first diffusion barrier layer 16 that is maintained in the at least one second opening 14 can be referred to as a first diffusion barrier liner 17L. Collectively, the first diffusion barrier liner 17L, the hybrid metal-containing liner 18L, the second diffusion barrier liner 20L, and the copper-containing region 22S that are present in the at least one second opening 14 provide a copper-containing electrically conductive structure that has the second critical dimension (CD-2) mentioned above. The second diffusion barrier liner 20L is needed to preserve the reliability of the copper-containing electrically conductive structure.
The first diffusion barrier liner 17L of the copper-containing electrically conductive structure is compositionally the same as the diffusion barrier liner 16L of the hybrid metal-containing electrically conductive structure since both liners are derived from the first diffusion barrier layer 16. The diffusion barrier liner 16L of the hybrid metal-containing electrically conductive structure lines the interconnect dielectric material layer 10 exposed by the at least one first opening 12, while the first diffusion barrier liner 17L of the copper-containing electrically conductive structure lines the interconnect dielectric material layer 10 exposed by the at least one second opening 14. The hybrid metal-containing region 18S of the hybrid metal-containing electrically conductive structure and the hybrid metal-containing liner 18L of the copper-containing electrically conductive structure are composed of a compositionally same hybrid metal or metal alloy.
As is shown in
The hybrid metal-containing electrically conductive structure (16L/18S) and the copper-containing electrically conductive structure (17L/18L/20L/22S) are located in the same interconnect level and are embedded in a same interconnect dielectric material, i.e., interconnect dielectric material layer 10. The hybrid metal-containing electrically conductive structure (16L/18S) has a topmost surface that is coplanar with a topmost surface of both the copper-containing electrically conductive structure (17L/18L/20L/22S) and the interconnect dielectric material layer 10. In some embodiments, both the hybrid metal-containing electrically conductive structure 16L/18S) and the copper-containing electrically conductive structure (17L/18L/20L/22S) are partially embedded in the interconnect dielectric material layer 10.
The hybrid metal-containing electrically conductive structure (16L/18S) has a higher bulk resistivity than the copper-containing electrically conductive structure (17L/18L/20L/22S). In some embodiments, the hybrid metal-containing electrically conductive structure (16L/18S) can be used for signal distributions within the interconnect structure, while the copper-containing electrically conductive structure (17L/18L/20L/22S) can be used for power lines. Collectively, the BEOL interconnect structure containing the hybrid metal-containing electrically conductive structure (16L/18S) and the copper-containing electrically conductive structure (17L/18L/20L/22S) can be referred to as a hybrid interconnect structure.
In some embodiments of the present application (not shown), a metal cap can be selectively deposited on the topmost surface of both the hybrid metal-containing region 18S and the hybrid metal-containing region 18S.
While the present application has been particularly shown and described with respect to preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in forms and details may be made without departing from the spirit and scope of the present application. It is therefore intended that the present application not be limited to the exact forms and details described and illustrated, but fall within the scope of the appended claims.
