Patent Application
20050236684
The present invention relates to flip chip packaging of semiconductor integrated circuits. More particularly, the present invention relates to a flip-chip packaging structure and method which reduces space particularly in the packaging of image sensors.
One of the last processes in the production of semiconductor integrated circuits (IC) is multi-leveled packaging, which includes expanding the electrode pitch of the IC chips containing the circuits for subsequent levels of packaging; protecting the chip from package internal and external stress; providing proper thermal paths for channeling heat dissipated by the chip; and forming electronic interconnections. The manner in which the IC chips are packaged dictates the overall cost, performance, and reliability of the packaged chips, as well as of the system in which the package is applied.
Package types for IC chips can be broadly classified into two groups: hermetic packages and non-hermetic packages. A chip packaged in a hermetic package is isolated from the ambient environment by a vacuum-tight or special atmosphere enclosure. The package is typically ceramic and is utilized in high-performance applications. A chip packaged in a non-hermetic package, on the other hand, is not completely isolated from the ambient environment Of course, a hermetic package's manufacturing cost is higher than a non-hermetic package's, the hermetic package still have to be used for the special application, such like image sensor or pressure sensor. Recent advances in hermetic package used by plastic, however, has expanded their application and performance capability. Plastic packages are cost-effective due to the fact that the production process is typically facilitated by automated batch-handling.
A recent development in the packaging of IC chips is the ball grid array (BGA) package, which may be utilized with either ceramic packages or plastic packages and involves different types of internal package structures. The BGA package uses multiple solder balls or bumps for electrical, mechanical and thermal interconnection of IC chips to other microelectronic devices. The solder bumps serve to both secure the IC chip to a circuit board and electrically interconnect the chip circuitry to a conductor pattern formed on the circuit board. The BGA technique is included under a broader connection technology known as “Controlled Collapse Chip Connection-C4” or “flip-chip” technology.
Flip chip technology can be used in conjunction with a variety of circuit board types, including ceramic substrates, printed wiring boards, flexible circuits, and silicon substrates. The solder bumps are typically located at the area array of the flip chip on electrically conductive bond pads that are electrically interconnected with the circuitry on the flip chip. Because of the numerous functions typically performed by the microcircuitry of a flip chip, a relatively large number of solder bumps are often required. The size of a flip chip is typically on the order of about thirteen millimeters per side, resulting in crowding of the solder bumps along the perimeter of the flip chip. Consequently, flip chip conductor patterns are typically composed of numerous individual conductors that are often spaced apart about 0.1 millimeter or less.
A section of a typical conventional flip chip 26 is shown schematically in
As further shown in
After the solder bumps 10 are formed on the flip chip 26, the chip 26 is inverted (thus the term, “flip chip”) and the solder bumps 10 are bonded to electrical terminals in a substrate 28 such as a printed circuit board (PCB). As shown in
After the solder bumps 10 are bonded to the PCB substrate 28, the flip chip 26 is subjected to a variety of tests such as, for example, bump shear tests and die shear tests, in which shear stress is applied to the flip chip 26 to determine the mechanical integrity of the electrical connections between the flip chip 26 and the bonded PCB substrate 28. The flip chip 26 may also be subjected to temperature tests, in which the flip chip 26 is subjected to temperatures of up to typically about 150 degrees C. However, leadless chip carrier packaging is commonly used to package an image sensor such as a CCD (Charge Coupled Device) or or CMOS (Complementary Metal Oxide Semiconductor) image sensor, for example.
A charge coupled device (CCD) image sensor is an electronic device that is capable of transforming a light pattern or image into an electric charge pattern or electronic image. The CCD includes several photosensitive elements that have the capacity to collect, store and transport electrical charge from one photosensitive element to another. The photosensitive properties of silicon make silicon the material of choice in the design of image sensors. Each photosensitive element represents a picture element, or pixel. With semiconductor technologies and design rules, structures are made that form lines, or matrices, of pixels. One or more output amplifiers at the edge of the chip collect the signals from the CCD. An electronic image can be obtained by applying a series of pulses that transfer the charge of one pixel after another to the output amplifier, line after line. The output amplifier converts the charge into a voltage. External electronics transform the output signal into a form suitable for monitors or frame grabbers.
CMOS (complementary metal oxide semiconductor) image sensors operate at a lower voltage than CCD image sensors, reducing power consumption for portable applications. Each CMOS active pixel sensor cell has its own buffer amplifier and can be addressed and read individually. A commonly used cell has four transistors and a photo-sensing element. The cell has a transfer gate separating the photo sensor from a capacitive “floating diffusion”, a reset gate between the floating diffusion and power supply, a source-follower transistor to buffer the floating diffusion from readout-line capacitance, and a row-select gate to connect the cell to the readout line. All pixels on a column connect to a common sense amplifier.
In addition to their lower power consumption when compared with CCDs, CMOS image sensors are generally of a much simpler design, often having a crystal and decoupling. For this reason, they are easier to design with, generally smaller, and require less support circuitry than CCD image sensors.
A conventional leadless chip carrier package 30 is shown in
The leadless chip carrier package 30 has a thickness 46 of typically about 2 mm. One of the limitations inherent in using the leadless chip carrier package 30 to package image sensors is the relatively large space consumed by the package 30. This contributes in many cases to the excessive size of the image sensor device. Accordingly, a new and improved packaging structure and method is needed for the packaging of an image sensor.
An object of the present invention is to provide a novel packaging structure for an image sensor.
Another object of the present invention is to provide a novel image sensor packaging structure which is characterized by economy of space.
Still another object of the present invention is to provide a novel BGA (ball grid array) image sensor packaging structure.
Still another object of the present invention is to provide a novel packaging method for the packaging of image sensors.
Another object of the present invention is to provide a novel packaging structure and method which is suitable for the packaging of CCD or CMOS image sensors.
Yet another object of the present invention is to provide a BGA method for the packaging of image sensors.
A still further object of the present invention is to provide an image sensor packaging structure which is characterized by significantly reduced thickness.
The present invention is generally directed to a new and improved image sensor packaging structure. The image sensor packaging structure includes a glass substrate. A bond pad film, on which is provided multiple, interior flip-chip bond pads and exterior BGA (ball grid array) bond pads, is provided on the glass substrate. An inverted image sensor chip is bonded to the flip-chip bond pads on the glass substrate, with the image sensor chip facing the glass substrate through a window provided in the bond pad film. Solder bumps (Actually the connecting solder from chip to substrate is call “bump”, and the connecting solder from substrate to mother board is call “ball”) are provided on the BGA bond pads on the bond pad film, and bond pads on a PCB (printed circuit board) are bonded to the respective solder balls.
The image sensor packaging structure of the present invention is characterized by high space efficiency as compared to conventional, leadless chip carrier packages typically used in the packaging of image sensors. The entire thickness of the image sensor packaging structure of the present invention is typically about 800˜1400 _m, as compared to a total thickness of typically about 2 mm for a leadless chip carrier package. Consequently, the image sensor device can be constructed in much smaller sizes than is possible using conventional packaging structures for CCD or CMOS image sensors.
The present invention is further directed to a method for packgaging an image sensor. The method includes providing a glass substrate; providing a bond pad film on which is provided multiple, interior flip-chip bond pads and exterior BGA (ball grid array) bond pads; providing the bond pad film on the glass substrate; providing solder bumps on the respective image sensor chip bond pads; bonding an inverted image sensor chip to flip-chip bond pads on the film; providing BGA solder balls on the BGA bond pads; and bonding a PCB (printed circuit board) to the BGA solder balls.
The invention will now be described, by way of example, with reference to the accompanying drawings, in which:
The present invention contemplates a structure and method for the packaging of an image sensor IC (integrated circuit) chip. The structure is a flip-chip BGA (ball grid array) packaging structure which is characterized by a high space efficiency as compared to conventional packaging structures for image sensors. Consequently, the image sensor device can be constructed in much smaller sizes than is possible using conventional packaging structures. The packaging structure may be adapted to either CCD image sensors or CMOS image sensors.
Referring initially to
An inverted CCD (charge-coupled device) or CMOS (complementary metal oxide semiconductor) image sensor IC chip 60 is bonded to the interior solder bumps 62. As shown in
Referring next to
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Referring again to
A flow diagram which summarizes typical process steps in the fabrication of the image sensor packaging structure is shown in
While the preferred embodiments of the invention have been described above, it will be recognized and understood that various modifications can be made in the invention and the appended claims are intended to cover all such modifications which may fall within the spirit and scope of the invention.
