Patent Application
20100052087
This invention relates to image sensors.
An image sensor is an electronic device that receives an optical image and converts it into an electronic signal. Conventional image sensors include, among others, charge-coupled devices (CCDs) and complementary metal oxide semiconductor (CMOS) devices. A variety of image sensor technologies have been proposed, presenting various (and sometimes competing) performance characteristics, and presenting particular technical challenges, particularly for example as relate to manufacturability. Performance improvements and lower cost of manufacture of CMOS image sensors have resulted in gains over conventional CCD image sensors, especially in consumer and hand-held applications such as cell phones, PDAs, digital music players, digital cameras, GPS devices, and the like.
Significant efforts have been directed to merging as much as possible of the required functionality for the various functions and features that might be merged into such devices in a single semiconductor (silicon) chip, but these efforts have not proven to be practical or cost effective.
Separate chips can be employed to carry out these various functions, and each die can be subjected to the best silicon processes for construction of particular circuits to carry out the functions. Where, for example, it is advantageous to include large amounts of memory storage in the product, it is often more cost effective to accomplish this in a system having multiple chips, including memory chips.
As the industry matures there is a drive to improve overall functionality as well as form factor and cost. Significant effort has been directed to thinning devices, reducing device footprints, and increasing density by stacking chips. To improve throughput and manufacturing reliability, there has been a tendency toward wafer level processing.
Factors intrinsic to image sensing and processing, and to manufacture of devices intended to provide suitable image sensing and processing, present particular technical challenges, in terms both of cost and of performance. Particular challenges may be presented by demands to decrease device footprint and thickness without compromising performance.
Image sensor packaging requirements present unique challenges. Particularly, for example, the sensor must remain unobscured by other features of the package, and must be protected from damage during manufacturing operations and throughout the in-service life of the product into which it will be incorporated. As the electrical interconnection pads are at the image sensor (active) side of the die, means must be provided to route the signals from the front surface of the die to the back for connection to underlying circuitry, such as a circuit board.
In conventional image sensor cavity packages, the image sensor die is mounted on a package substrate, and is electrically connected to the substrate using wire bonds. Wire bonds increase both the footprint and the thickness of the package, because the wire span and wire loop height must be accommodated. Additionally, to protect the sensing array and to permit optical access, a cover glass may be provided over the cavity, further increasing the thickness of the assembly.
In some approaches to improving footprint and package thickness, cover glass protection may be formed at the wafer level before die singulation. More recently, attention has been directed to so-called through silicon via (TSV) techniques to route electrical signals from the front (active) side of the sensor die to the backside. TSV is essentially a front-end approach requiring expensive equipment, and much process development remains before it can be considered ready for reliable, low cost manufacture. Capital equipment costs and lack of process maturity pose obstacles to widespread adoption of TSV.
Color filters may be provided on the surface of the sensor array, and micro-lenses may be incorporated on the surface of the chip for improving light sensitivity. These features are usually formed of polymers that cure at relatively low temperatures, and they can be deformed or damaged by elevated processing temperatures during packaging operations. To avoid damage to these parts of the image sensor, process temperatures during packaging of the image sensor chips must be kept low.
In one general aspect the invention features an image sensor die. The image sensor die has a front side (the “active side”), a back side, and sidewalls; the active side has an active surface including a sensor array area, and interconnect pads arranged adjacent at least one die edge (an “interconnect edge”); and the image sensor die has a conformal dielectric coating over the interconnect edge and over an adjacent die sidewall (an “interconnect sidewall”). In some embodiments the active surface of the image sensor die further includes a peripheral circuitry area.
In some embodiments the image sensor die further includes an optically transparent conformal dielectric coating over at the sensor array area, and in some embodiments additionally over the peripheral circuitry area.
In some embodiments the conformal dielectric coating may additionally cover the back side of the image sensor die. In some embodiments the image sensor die includes a die attach film at the back side. In some embodiments the image sensor die includes both a die attach film and a conformal dielectric coating at the back side and, in some such embodiments either the die attach film or the conformal dielectric coating may be applied onto the die back side surface.
In some embodiments the optically transparent conformal dielectric coating and the conformal dielectric coating over the die edges and die sidewalls are formed of the same material or of similar materials. Suitable materials at least for the optically transparent coating include organic polymers formed by vapor deposition, and a particularly useful conformal coating may be a polymer of p-xylene or a derivative thereof, such as a polyxylylene polymer, e.g., a parylene C or a parylene N, or a parylene A. In some embodiments the optically transparent conformal dielectric coating and the conformal dielectric coating over the die edges are formed as a continuous coating, and openings in the coating expose die pads for subsequent electrical connection to other circuitry.
In another general aspect the invention features an image sensor package, including an image sensor die mounted over a support. The image sensor die has interconnect pads arranged adjacent at least one die edge (an “interconnect edge”), and has a conformal dielectric coating over the interconnect edge and over an adjacent die sidewall (a “interconnect sidewall”). The image sensor die is electrically connected to interconnect sites at a first surface (the “interconnect surface”) of the support by traces of an electrically conductive material that is applied to or adjacent to the coated interconnect edge and sidewall; the trace makes contact with an exposed pad on the image sensor die and with a site on the support. In some embodiments the image sensor die additionally has an optically transparent dielectric conformal coating over at least the sensor array area of the active side, and in some embodiments additionally over a peripheral circuitry area of the active side.
In some embodiments two or more image sensor die are mounted over and electrically connected to the support.
Suitable electrically conductive materials include materials that can be applied in a flowable form and then cured or allowed to cure to form the electrically conductive traces. Such materials include, for example, electrically conductive polymers, including electrically conductive particulates (e.g., conductive metal particles) contained in a curable organic polymer matrix (for example, conductive (e.g., filled) epoxies, or electrically conductive inks); and include, for example, electrically conductive particulates delivered in a liquid carrier. In particular embodiments the interconnect material is a conductive polymer such as a curable conductive polymer, or a conductive ink.
In some embodiments the support to which the image sensor die is electrically connected is a circuit board, or a package substrate, or a leadframe. Suitable package substrates include, for example, ball grid array (“BGA”) or land grid array (“LGA”) substrate, or a flex tape substrate.
In some such embodiments the image sensor die may be mounted onto a surface of the package substrate (such as the interconnect surface) or the leadframe (such as a die mount surface, which may be a die paddle, for example); in other such embodiments an additional electrical device (such as an additional die) is interposed between the image sensor die and the support to which the image sensor die is electrically connected. Where the interposed electrical device includes circuitry (such as circuitry on an interposed additional die) the image sensor die may additionally be electrically connected to circuitry on the interposed electrical device. Where the interposed electrical device is an additional die, the additional die may be, for example, a memory die, or a processor (such as a graphics processing unit), or a wireless communication chip, or a network access chip.
In some embodiments the support to which the image sensor die is electrically connected is an additional die; and in some such embodiments the interconnect sites on the additional die include die pads. That is, in such embodiments the interconnect traces make contact with an exposed pad on the image sensor die and with an exposed pad on the additional die. In some such embodiments the additional die is mounted onto a package support such as a package substrate or leadframe; the additional die may be electrically connected to the support, and the image sensor die may be electrically connected to interconnect sites on the die and additionally to interconnect sites on the support. The additional die may have any of a variety of functionalities, including for example processing (e.g., graphics processing) functionalities and memory functionalities; and the additional die may have a combination of functionalities.
In some embodiments having an additional electrical device interposed between the image sensor die and the support to which the image sensor die is electrically connected, the interconnect edge (or a portion thereof) of the image sensor die may be set back from, or may be vertically aligned with, or may extend beyond, an edge of the interposed electrical device. In embodiments where the interconnect edge (or a portion thereof) extends beyond an edge of the interposed electrical device, the image sensor die may be electrically connected to interconnect sites at the interconnect surface of the underlying support by pedestals of electrically conductive material at the sites on the support and traces of an electrically conductive material that is applied to or adjacent to the coated interconnect edge and sidewall and that make contact with the pedestals.
In some embodiments the support to which the image sensor die is electrically connected is a stack of additional die; and in some such embodiments the interconnect sites on the additional die include die pads. That is, in such embodiments the interconnect traces make contact with an exposed pad on the image sensor die and with an exposed pad on at least one of the additional die. In some embodiments two or more of the additional die may be interconnected in the stack. In some such embodiments the stack of additional die is mounted onto a package support such as a package substrate or leadframe; the stack of additional die may be electrically connected to the support, and the image sensor die may be electrically connected to interconnect sites on at least one of the additional die and additionally to interconnect sites on the support. The additional die in the stack may have any of a variety of functionalities, including for example processing (e.g., graphics processing) functionalities and memory functionalities; the die in the stack may have the same functionalities, or, various die in the stack may have different functionalities; one or more of the additional die in the stack may have a combination of functionalities. In particular embodiments, for example, a memory die (or a stack of memory die) may be stacked on a processor die such as a graphics processor unit (“GPU”), and these die may be interposed between the image sensor die and the support.
In some embodiments an additional electrical device is mounted on and electrically connected to interconnect sites at a second surface of the support. The second surface of the support may be an area on the same side of the support as the interconnect surface; or the second surface may be an area on the opposite side of the support. The additional electrical device mounted on the second surface of the support may include, for example, an additional die or stack of additional die or a semiconductor package.
In some embodiments an additional electrical device is interposed between the image sensor die and a first surface of the support, and a further additional electrical device is mounted on and electrically connected to interconnect sites at a second surface of the support.
In some such embodiments the support comprises a package substrate, such as a ball grid array (“BGA”) or land grid array (“LGA”) substrate, or a flex tape substrate.
In another general aspect the invention features an image sensor assembly, including an image sensor die mounted on and electrically connected to a first surface of a support as described above, and additionally including at least one die having another functionality mounted on and connected to circuitry at the opposite side of the support. In particular embodiments of such an assembly, for example, the image sensor die is mounted on and electrically connected to sites on a first surface of a package substrate, and a stack of electrically interconnected memory die is mounted on and electrically connected to sites at the opposite side of the substrate.
In another general aspect the invention features a wafer level or die array level method for making an image sensor package, including providing a wafer having image sensor circuitry formed on an active side thereof, cutting the wafer to form die edges and die sidewalls (including interconnect edges along which die pads are arranged and interconnect sidewalls adjacent the interconnect edges), and depositing a conformal dielectric coating over the front side of the cut wafer, including the interconnect edges and die sidewalls. In particular embodiments the conformal coating is a parylene, formed by vapor deposition.
In some embodiments the wafer level method or die array level method includes thinning the wafer by removal of material from the wafer backside (“backgrinding”). In some such embodiments the wafer is cut at least in part after backgrinding; in some embodiments the wafer is cut at least in part before backgrinding; in some embodiments the wafer is cut by two or more cutting procedures, and the backgrind is carried out between the cutting procedures.
In another general aspect the invention features a method for making an image sensor package, including providing a die having a front side and a back side and image sensor circuitry formed on the active side, the die having die sidewalls defining die edges (including interconnect edges along which die pads are arranged and interconnect sidewalls adjacent the interconnect edges); applying a conformal dielectric coating over at least the interconnect edges and the interconnect sidewalls; providing a support having connection sites at a first surface thereof; mounting the die over the first surface and electrically connecting the die to circuitry in the support, by applying traces of an electrically conductive material to or adjacent to the coated interconnect edge and sidewall in contact with an exposed pad on the die and with a connection site on the support.
In some embodiments the method includes applying a conformal dielectric coating over the front side of the image sensor die; in some embodiments the method includes applying a conformal dielectric coating over the back side of the die; and in some embodiments the method includes applying a conformal dielectric coating over the front side and the back side of the die. In particular embodiments the method includes applying a conformal dielectric coating over all sides of the image sensor die. In some such embodiments applying a conformal dielectric coating over the front side of the die, and/or over the back side of the die, can be carried out concurrently with applying conformal coating over the interconnect edges and the interconnect sidewalls. In some embodiments applying the conformal dielectric coating further includes selectively removing areas of the coating to expose features (such as interconnect pads). In particular embodiments applying the conformal coating includes coating die surfaces with a parylene, and selectively removing areas of the coating includes directing laser energy at the areas.
In some embodiments mounting the image sensor die over the first surface of the support includes mounting an additional electrical device on the first surface of the support, and affixing the image sensor die on a surface of the additional electrical device. In some embodiments affixing the image sensor die includes applying a die attach film or a die attach adhesive to the back side of the image sensor die or to the surface to which the die is mounted. In some embodiments, where the die has a suitable conformal dielectric coating (such as a parylene film) over the back side, it may be unnecessary to employ a die attach film or die attach adhesive between the back side of the image sensor die and the surface to which it is affixed, as the conformal dielectric coating may serve to affix the die to the support surface.
The die, packages, and assemblies according to the invention can be used in computers, telecommunications equipment, and consumer and industrial electronics devices.
The invention will now be described in further detail by reference to the drawings, which illustrate alternative embodiments of the invention. The drawings are diagrammatic, showing features of the invention and their relation to other features and structures, and are not made to scale. For improved clarity of presentation, in the FIGs. illustrating embodiments of the invention, elements corresponding to elements shown in other drawings are not all particularly renumbered, although they are all readily identifiable in all the FIGs. Also for clarity of presentation certain features are not shown in the FIGs., where not necessary for an understanding of the invention.
Turning now to
As
The sensor array 126 may include an array of any of a variety of photosensors, including any of a variety of solid state imaging devices, such as, for example, photodiodes, phototransistors.
According to the invention, the optical sensor die 122 is electrically connected to the support by interconnect traces 114, 114′ of electrically conductive material that contacts and provides electrical continuity between interconnect die pads (e.g., pad 124′) and corresponding sites in the support (e.g., bond pad 112′). Suitable electrically conductive materials include materials that can be applied in a flowable form and then cured or allowed to cure to form the electrically conductive traces. Such materials include, for example, electrically conductive polymers, including electrically conductive particulates (e.g., conductive metal particles) contained in a curable organic polymer matrix (for example, conductive (e.g., filled) epoxies, or electrically conductive inks); and include, for example, electrically conductive particulates delivered in a liquid carrier. The material may be applied by dispensing, or printing, or spraying, for example. Examples of suitable interconnect materials, and techniques for applying them, are described for example in T. Caskey et al. U.S. patent application Ser. No. 12/124,097, titled “Electrical interconnect formed by pulsed dispense”, which was filed May 20, 2008, and which is incorporated herein by reference. Conductive inks may be applied by aerosol spray, for example, and may following application be sintered or cured, according to the constitution of the particular ink. Particles in a carrier may be dispensed or applied by aerosol spray, for example, and may following application be sintered to form the electrically conductive traces.
The interconnection in an example as in
In an example as illustrated in
The conformal coating transmits light to the optical sensor. Accordingly, the conformal coating may be substantially optically clear at least to wavelengths at which the optical sensor is intended to operate. Where for example the optical sensor die is intended to operate at wavelengths over the entire visible spectrum, the conformal coating transmits wavelengths at least in the visible region. The optical sensor may be intended to operate in UV, deep UV, or IR; and the conformal coating in such instances transmits wavelengths at least in the corresponding parts of the spectrum. The conformal coating also provides mechanical and chemical protection to the underlying structures. A preferred coating material does not require temperature elevation, does not shrink during coating formation, and protects the underlying surfaces during wafer processing.
Useful conformal coatings include organic polymers formed by vapor deposition, and a particularly useful conformal coating may be a polymer of p-xylene or a derivative thereof, such as a polyxylylene polymer, e.g., a parylene C or a parylene N, or a parylene A. Openings in the coating may be formed, where required, by selective laser ablation, for example.
The conformal parylene coating is formed by vapor deposition, and the coatings can be formed at the wafer level or at the die array level of processing. Stages in an example of a wafer process are as follows, for example. The wafer is provided, with image sensor (e.g., CMOS sensor) circuitry formed thereon.
In a cut-before-thinning procedure, the wafer is cut at the active side, for example by sawing using a dicing saw, to a depth in the wafer material slightly greater than the final die thickness, so that the die sidewalls are formed, but the die are not fully singulated. The cut wafers are then placed in a parylene deposition chamber, and deposition is carried out to form a thin coating on the exposed surfaces, that is, on the front side of the die and on the exposed die sidewalls.
The coating is formed to a thickness sufficient to provide a continuous coating (free of pinholes), and sufficient to provide electrical insulation with a dielectric strength that meets or exceeds the requirements of the underlying circuitry. Parylene coating thicknesses in a range about 1 um to about 5 um may be suitable, for example. After the coating is complete, the wafer is removed from the parylene chamber and a laser ablation system is used to remove the coating from the interconnect die pads on the front surface of the die. As may be appreciated, the laser must be operated at a wavelength at which there is appreciable energy absorption in the coating layer, considering that parylene is substantially transparent in the visible range between 300 and 800 nanometers. Optionally, the removal of coating material from the pads may be carried out at a later stage, at any time up to the time electrical connection of the die is to be carried out.
The wafer is then thinned to a specified die thickness (typically, for example, 50 um or less) by, for example, backgrinding, Because the wafer had previously been cut to a depth exceeding the die thickness, the backgrinding results in singulation of the die.
In a cut-after-thinning procedure, the wafer as provided is thinned, for example by backgrinding, to a desired die thickness; and then the wafer is cut through either from the wafer front side or from the wafer backside to yield singulated die in a die array. Then the die array is supported with the active side and die edges and sidewalls exposed, and treated as described above to form the conformal coating over the exposed surfaces. Then laser ablation is used to expose interconnect pads on the die.
A hybrid cut-and-thin die separation process may be used, particularly where interconnect die pads are arranged in the die margin along one or two die edges. Hybrid cut-and-thin processes are described in R. Co et al. U.S. application Ser. No. 12/323,288, titled “Semiconductor die separation method”, which was filed Nov. 25, 2008, and which is incorporated herein by reference. Briefly, the wafer is cut in two stages. The first cutting procedure may be carried out prior to wafer thinning to the desired die thickness, or wafer thinning may be carried out prior to the first cutting procedure. In the first cutting procedure the wafer is cut from the front side along streets fronting the interconnect edges to a depth less than the die thickness, to form interconnect die edges and at least partial interconnect sidewalls; and the wafer is cut along the other streets to a depth at least about the die thickness. Thereafter the wafer array is treated as described above to form the conformal coating over the front side and die edges and interconnect sidewalls. Thereafter the wafer is cut in a second cutting procedure along the streets fronting the interconnect sidewalls to singulate the die and complete the die sidewalls.
A die attach film can optionally be applied to the backside of the thinned wafer (in a cut after thinning procedure, or in a hybrid cut-and-thin procedure) or to the back sides of the singulated die while they are in a die array, and then a pick-and-place operation is employed to affix the singulated die to an appropriate support such as a package substrate, or a circuit board, or another die. Where a suitable conformal dielectric coating (such as a parylene film) is formed over the back side, it may be unnecessary to employ a die attach film or die attach adhesive between the back side of the image sensor die and the surface to which it is affixed, as the conformal dielectric coating may serve to affix the die to the support surface. Where a die attach film is employed, it may be advantageous to apply the film to the thinned wafer backside or to the die back sides at the die array level; and, particularly, it may be advantageous in a cut after thinning procedure or in a hybrid cut-and-thin procedure to apply the die attach film prior to completing wafer cutting, to help avoid die shift or die tilt during subsequent processing steps.
In other embodiments the conformal coating may be removed from or may be omitted from the area of the active side of the die overlying the image array area. The advantages of protecting the image array surface during subsequent processing are lost in such embodiments, however.
Suitable electrically conductive materials for the electrical interconnect are applied in a flowable form, subsequently cured or permitted to harden. The interconnect material may be an electrically conductive polymer; or a conductive ink. The interconnect material may be a curable conductive polymer, for example, such as a curable epoxy; and the interconnect process may include forming traces of the uncured material in a prescribed pattern and thereafter curing the polymer to secure the electrical contacts with the lead ends and the interconnect sites and the mechanical integrity of the traces between them. The interconnect material may be applied using an application tool such as, for example, a syringe or a nozzle or a needle; more usually the tool is a deposition head, configured to automatically (for example, robotically) and accurately deposit the material. The material is applied by the tool in a deposition direction generally toward the lead ends at the sidewall surface, and the tool is moved over the presented die sidewall of die stack face in a work direction. The material may be extruded from the tool in a continuous flow, or, the material may exit the tool dropwise. In some embodiments the material exits the tool as a jet of droplets, and is deposited as dots which coalesce upon contact, or following contact, with the electrically insulated die sidewall surface. In some embodiments the material is applied in an aerosol spray. In some embodiments the deposition direction is generally perpendicular to the die sidewall surface, and in other embodiments the deposition direction is at an angle off perpendicular to the stack face surface. The tool may be moved in a generally linear work direction, or in a zig-zag work direction, depending upon the location on the die and on the substrate of the various pads to be connected.
Prior to application of the interconnect material the surface of the die pad and/or the connection site on the support may optionally be provided with an element (or elements) which, under the cure conditions, can together with an element (or elements) in the interconnect material, form an intermetallic at the interface of the interconnect material and the pad or site surface.
Optionally, a plurality of deposition tools may be held in a ganged assembly or array of tools, and operated to deposit one or more traces of material in a single pass.
Alternatively, the material may be deposited by pin transfer or pad transfer, employing a pin or pad or ganged assembly or array of pins or pads.
The application of the interconnect material may be automated; that is, the movement of the tool or the ganged assembly or array of tools, and the deposition of material, may be controlled robotically, programmed as appropriate by the operator.
Alternatively the interconnect material may be applied by printing, for example using a print head (which may have a suitable array of nozzles), or for example by screen printing or using a mask or stencil.
As
The illustrated examples have one image sensor die mounted over the support. In other embodiments two or more image sensor die are mounted over and electrically connected to the support. In such embodiments the various die may be operationally the same, providing redundancy or additive image-forming capability. Or, for example, the various die may be operational at different parts of the spectrum. For example, three die operating in the visible region may be sensitive respectively to red, green, and blue wavelengths; and, in such embodiments, an additional fourth die may be sensitive at wavelengths generally over the visible region. Or, for example, one or more die may be sensitive to a part or parts of the visible region, and one or more additional die may be sensitive to wavelengths outside the visible region, such as UV, deep UV, and/or IR, for example.
The support shown in the examples of
Additional electrical devices may be electrically connected to the side of the support opposite the side over which the optical sensor die is mounted. Any of a variety of electrical devices may be deployed in such embodiments; including, for example, a semiconductor die; a stack of semiconductor die; a semiconductor die package; one or more passive or active electrical features; a carrier having electrical circuitry; a carrier having electrically connected passive features or active features. By way of example,
of an interconnect material that is applied in a flowable form, in a manner similar to that described above for connection of the image sensor die to the sensor die mount side of the support. Suitable connections alternatively include wire-bonding, tab-interconnect, flip-chip interconnect, and the like. The die in the stack 62 may have the same functionality (or example, they may be memory die), or they may have different functionalities; and the die may have the same or different dimensions. The stack 62 may include more than two die; and, a single die may be mounted on the substrate in place of the stack 62.
In
In other embodiments the optical sensor die is mounted over and electrically connected to the support, and an additional electrical device (or a device stack having one or more additional electrical devices) is interposed between the optical sensor die and the support. The optical sensor die may optionally be electrically connected to the interposed electrical device (or to one or more of the additional devices in the stack); the interposed additional device (or one or more of the devices) may optionally be electrically connected to the support; and, where a stack of devices is interposed between the optical sensor die and the support, the additional devices may optionally be connected to each other in the stack. Any of a variety of electrical devices may be deployed in such embodiments, including, for example, a semiconductor die; a stack of semiconductor die; a semiconductor die package; one or more passive or active electrical features; a carrier having electrical circuitry; a carrier having electrically connected passive features or active features. Some illustrative examples follow.
Interposed electrical device (or devices) may have dimensions smaller than a dimension of the overlying image sensor die, and in such embodiments the interconnect sidewall of the image sensor die may overhang the interposed device (or devices).
Other embodiments are within the claims.
This application claims priority from S. J. S. McElrea et al. U.S. Provisional Application No. 61/093,001, filed Aug. 29, 2008, titled “Image sensor”, which is hereby incorporated herein by reference.
| Number | Date | Country | |
|---|---|---|---|
| 61093001 | Aug 2008 | US |
