Patent Application
20170005112
The present invention relates generally to suspended semiconductor device structures and in particular to disposing different device types on the same substrate.
Field effect transistors (FETs) can be semiconductor devices fabricated on a bulk semiconductor substrate or on a silicon-on-insulator (SOI) substrate. FET devices generally consist of a source, a drain, a gate, and a channel between the source and drain. The gate is separated from the channel by a thin insulating layer, typically of silicon oxide, called the gate oxide. A voltage drop generated by the gate across the oxide layer induces a conducting channel between the source and drain thereby controlling the current flow between the source and the drain. Current integrated circuit designs use complementary metal-oxide-semiconductor (CMOS) technology that use complementary and symmetrical pairs of p-type and n-type metal oxide semiconductor field effect transistors (MOSFETs) for logic functions.
The integrated circuit industry is continually reducing the size of the devices, increasing the number of circuits that can be produced on a given substrate or chip. It is also desirable to increase the performance of these circuits, increase the speed, and reduce the power consumption. A three-dimensional chip fabrication approach, such as a finFET, has been developed for semiconductor devices. A finFET is a non-planar FET, generally regarded as a type of suspended channel device. The “fin” is a narrow, vertical silicon base channel between the source and the drain. The fin is covered by the thin gate oxide and bordered on two or three sides by an overlying gate structure. The multiple surfaces of the gate allow for more effective suppression of “off-state” leakage current. The multiple surfaces of the gate also allow enhanced current in the “on” state, also known as drive current. These advantages translate to lower power consumption and enhanced device performance.
In the area of suspended channel device structures, the suspension step is a pivotal point in the process sequence. In several integration flows, the use of an SOI wafer is often proposed, however, this adds to the overall technology cost, so the use of a bulk silicon wafer is often preferred. Several flows for bulk wafers have been considered, but these process flows may often rely on oxidizing a region under the fin or nanowire after the channel is protected by a hard mask and spacer, resulting in volumetric expansion of the oxide underneath the channel.
Embodiments of the present invention disclose a method of forming a silicon-on-insulator substrate and the resulting substrate. A silicon-on-insulator substrate which includes a semiconductor substrate, a buried oxide layer, and a semiconductor layer is provided. A hard mask layer is formed over a first region of the silicon-on-insulator substrate. A first silicon-germanium layer is epitaxially grown on the semiconductor layer within a second region of the silicon-on-insulator substrate. The second region is at least a portion of the semiconductor layer not covered by the hard mask layer. A thermal annealing process is performed, such that germanium atoms from the first silicon-germanium layer are migrated to the portion of the semiconductor layer to form a second silicon-germanium layer. The hard mask layer is removed. A layer of semiconductor material is epitaxially grown on top of the semiconductor layer and the second silicon-germanium layer, where the layer of semiconductor material composed of the same material as semiconductor layer.
Embodiments in accordance with the present invention contemplate the difficulty in tuning device strength in finFET-implemented circuitry. Adjusting device width, as one might attempt in planar CMOS (complementary metal-oxide-semiconductor transistors), is not an option in non-planar implementations, and attempting to weaken a FET (field-effect transistor) with dopants is undesirable due to the random dopant fluctuation (RDF) associated with some fabrication processes.
Fabrication of large-scale integration devices that include multiple functions can present particular problems. Processors that include a CPU (central processing unit) and a GPU (graphics processing unit) are in demand for inclusion in laptop computers, notebooks, and tablets. A CPU generally requires high-performance FETs, whereas, for GPU design, power consumption may be a more important concern. Consequently, FETs with lower drive current, perhaps implemented using devices with a lower overall device width, would be well-suited for such an application.
Embodiments in accordance with the present invention contemplate forming more than one region on a silicon on insulator (SOI) wafer. One region may remain silicon, thus lending itself to fabrication of finFET devices for the CPU portion of a device. In another region silicon-germanium (SiGe) on insulator (SGOI) may be formed, with a silicon epitaxial layer (silicon epi) grown on top of it. The lower SiGe layer may be employed as a release layer, thus enabling fabrication of nanowire FETs having a lower effective channel width (Weft) for the GPU portion.
An illustrative embodiment in accordance with the present invention is directed toward formation of a finFET device in an appropriate region of a wafer. Forming a buried gate structure wherein the gate is beneath the fin of a finFET device can allow for reduced height of the gate above the fin, thereby reducing the proximity of the gate to the source/drain contacts. The reduced surface area of the gate in proximity to the source/drain contacts can reduce the parasitic capacitance of the finFET device. Detailed descriptions of embodiments of the claimed structures and methods are disclosed herein; however, it is to be understood that the disclosed embodiments are merely illustrative of the claimed structures and methods that may be embodied in various forms. In addition, each of the examples given in connection with the various embodiments is intended to be illustrative, and not restrictive. Further, the figures are not necessarily to scale, some features may be exaggerated to show details of particular components. Therefore, specific structural and functional details disclosed herein are not to be interpreted as limiting, but merely as a representative basis for teaching one skilled in the art to variously employ the methods and structures of the present disclosure.
Example embodiments in accordance with the present invention will now be described in detail with reference to the figures.
It should be appreciated that embodiments of the invention are not limited to the embodiment depicted in
Any known method of fabricating a semiconductor wafer such as semiconductor wafer 100 can be used in various embodiments of the invention. Additionally, semiconductor wafer 100 may be purchased from a vendor prior to performing the fabrication steps depicted in
In general, hard mask layer 210 can be any hard mask material that can act as an etch mask during the patterning of semiconductor layer 130, as described in greater detail with respect to
In general, hard mask layer 210 is removed from the region of semiconductor wafer 100 generally designated as region 260, which is intended to be utilized as an active region for the formation of nanowire FET devices. Similarly, hard mask layer 210 is not removed from the region of semiconductor wafer 100 generally designated as region 250, which is intended to be utilized as an active region for the formation of finFET devices. In various embodiments of the invention, multiple regions such as region 260 where hard mask layer 210 is removed may be present. The embodiment depicted in
In one embodiment, SiGe layer 310 is composed of a silicon-germanium alloy which includes 30% germanium and 70% Silicon. In another embodiment, SiGe layer 310 is composed of pure germanium. In a preferred embodiment, SiGe layer 310 includes between 25% and 35% germanium. In general, SiGe layer 310 can be any silicon-germanium alloy which includes at least 15% germanium. SiGe layer 310 can be formed using a process such as chemical vapor deposition (CVD). In other embodiments, any other known process for selectively growing a layer of semiconductor material can be used. In one embodiment, SiGe layer 310 is formed to a height of 20nm, and in other embodiments SiGe layer 310 is formed to a height between 5 nm and 50 nm.
The presence of a dielectric material such as hard mask layer 210 prevents SiGe layer 310 from being formed within region 250. In the depicted embodiment, SiGe layer 310 is formed selectively only on the exposed portion of semiconductor layer 130 present within region 260.
In various embodiments, additional planarization or CMP steps are utilized to even the top of SiGe layer 310 with the top of hard mask layer 210 and to ensure that the top surface of SiGe layer 310 is relatively flat.
A germanium condensation process is a high-temperature thermal anneal which is performed in an oxidizing environment. In a preferred embodiment, the thermal anneal is performed at a temperature between 1000 degrees Celsius and 1200 degrees Celsius. In one embodiment, the oxidizing environment in which the thermal anneal is performed is composed of an oxidizing agent such as oxygen, nitrous oxide, or water vapor which may be diluted in an inert ambient such as nitrogen or argon. The purpose of the germanium condensation process is to enrich the germanium content of the portion of semiconductor layer 130 present within region 260 through the migration of germanium atoms from SiGe layer 310 into semiconductor layer 130, thus forming SiGe layer 410. As a result of the presence of an oxidizing environment, an oxide layer such as silicon oxide (SiO2) forms on the exposed portions of SiGe layer 410. In general, because germanium is not incorporated into the oxide layer, the germanium is driven into the underlying silicon or silicon-germanium layer to enrich the germanium content of the underlying layer. In embodiments where a germanium condensation process is utilized, the silicon oxide which forms as a result of the germanium condensation process is selectively removed using a process such as a hydrogen fluoride (HF) dip.
A thermal mix process is a high-temperature thermal anneal which is performed in an inert environment, such as a noble gas or nitrogen. Similarly to a germanium condensation process, the high temperature thermal anneal results in the migration of germanium atoms from SiGe layer 310 into the portion of semiconductor layer 130 present within region 260, thus forming SiGe layer 410. Due to the lack of an oxidizing environment in a thermal mix process, no silicon oxide is formed on the exposed portions of SiGe layer 410.
In a preferred embodiment, after the germanium condensation or thermal mix processing, SiGe layer 410 is composed of roughly 30% Germanium and 70% Silicon. Based on the thicknesses of semiconductor layer 130, the thickness of SiGe layer 310, and the length and temperature of the germanium condensation or thermal mix process used in various embodiments of the invention, the percentage of germanium within SiGe layer 310 is selected to achieve the desired percentage of germanium present within SiGe layer 410.
In general, the additional semiconductor material which is formed has the same composition as the material of which semiconductor layer 130 is formed. Additionally, in preferred embodiments, the material of which the additional semiconductor material is formed has etch selectivity to the material of which SiGe layer 410 is formed.
Once semiconductor wafer 100 reaches the form depicted in
Examples of the result of fin patterning and formation within regions 250 and 260 are depicted and described in greater detail with respect to
In various embodiments, any known method for making a finFET device using the fins formed and depicted in
In various embodiments, either a gate-first process or a replacement gate process can be used to form a nanowire transistor device using the nanowires or fins formed using semiconductor wafer 100. In a gate-first process, the nanowires are released by selectively removing SiGe layer 410, then a metal gate structure is formed above and on the exposed sidewalls of the suspended nanowire. Once the gate structure has been formed, source and drain regions are formed in the nanowire adjacent to the gate structure.
In a replacement gate process, a dummy gate structure is formed prior to releasing the nanowire. Once the dummy gate structure is formed, source and drain regions are formed in the nanowire. After the formation of source and drain regions, the dummy gate is removed, the nanowire is released by selectively removing SiGe layer 410, and a metal gate structure is formed in the place of the dummy gate.
Additionally, it should be appreciated that after release, the nanowires formed remain rigidly attached to semiconductor wafer 100 by being attached to “pads” of semiconductor material at each of the terminal ends of each nanowire, in accordance with an embodiment of the invention. The process of anchoring a suspended nanowire to a “pad” of semiconductor material is well known in the art, and any known method for attaching a suspended nanowire to a semiconductor wafer can be used in various embodiments of the invention.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Detailed descriptions of embodiments of the claimed structures and methods are disclosed herein; however, it is to be understood that the disclosed embodiments are merely illustrative of the claimed structures and methods that may be embodied in various forms. In addition, each of the examples given in connection with the various embodiments is intended to be illustrative, and not restrictive. Further, the figures are not necessarily to scale, some features may be exaggerated to show details of particular components. Therefore, specific structural and functional details disclosed herein are not to be interpreted as limiting, but merely as a representative basis for teaching one skilled in the art to variously employ the methods and structures of the present disclosure.
References in the specification to “one embodiment”, “an embodiment”, “an example embodiment”, etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to affect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.
For purposes of the description hereinafter, the terms “upper”, “lower”, “right”, “left”, “vertical”, “horizontal”, “top”, “bottom”, and derivatives thereof shall relate to the disclosed structures and methods, as oriented in the drawing figures. The terms “overlying”, “atop”, “positioned on” or “positioned atop” mean that a first element, such as a first structure, is present on a second element, such as a second structure, wherein intervening elements, such as an interface structure may be present between the first element and the second element. The term “direct contact” means that a first element, such as a first structure, and a second element, such as a second structure, are connected without any intermediary conducting, insulating or semiconductor layers at the interface of the two elements.
Having described various embodiments of implementing a hybrid finFET device and nanowire device using selective SGOI (which are intended to be illustrative and not limiting), it is noted that modifications and variations may be made by persons skilled in the art in light of the above teachings. It is therefore to be understood that changes may be made in the particular embodiments disclosed which are within the scope of the invention as outlined by the appended claims.
