Patent Application
20130143392
Power electronics are widely used in a variety of applications. Power electronic devices are commonly used in circuits to modify the form of electrical energy, for example, from AC to DC, from one voltage level to another, or in some other way. Such devices can operate over a wide range of power levels, from milliwatts in mobile devices to hundreds of megawatts in a high voltage power transmission system. Despite the progress made in power electronics, there is a need in the art for improved electronics systems and methods of operating the same.
The present invention relates generally to electronic devices. More specifically, the present invention relates to forming structures using III-nitride semiconductor materials. Merely by way of example, the invention has been applied to methods and systems for manufacturing semiconductor devices including gallium-nitride (GaN) based layers and one or more layers of in-situ SiN. The methods and techniques can be applied to a variety of compound semiconductor systems such as Schottky diodes, PIN diodes, vertical junction field-effect transistors (JFETs), thyristors, and other devices.
According to an embodiment of the present invention, a method of fabricating a diode in gallium nitride (GaN) materials is provided. The method includes providing a n-type GaN substrate having a first surface and a second surface and forming a n-type GaN drift layer coupled to the first surface of the n-type GaN substrate. The method also includes forming an in-situ SixNy layer coupled to the n-type GaN drift layer opposite the n-type GaN substrate and at least partially removing portions of the SixNy layer and the n-type GaN drift layer to form a plurality of void regions and a remaining portion of the SixNy layer. The method further includes selectively regrowing a p-type epitaxial layer in the void regions.
According to another embodiment of the present invention, a method of fabricating an epitaxial structure is provided. The method includes providing a III-nitride substrate having a first conductivity type, a first surface, and a second surface opposing the first surface and forming a first GaN-based epitaxial layer having a first conductivity type and coupled to the first surface of the III-nitride substrate. The method also includes forming a second GaN-based epitaxial layer over the first GaN-based epitaxial layer. The second GaN-based epitaxial layer has a second conductivity type. The method further includes forming an in-situ protective layer comprising silicon and nitrogen. The in-situ protective layer is coupled to the second GaN-based epitaxial layer opposite the first GaN-based epitaxial layer. The method additionally includes at least partially removing portions of the in-situ protective layer and the second GaN-based epitaxial layer to form at least one gate structure, removing a remaining portion of the in-situ protective layer, and forming a first metallic structure coupled to the gate structure.
Numerous benefits are achieved by way of the present invention over conventional techniques. For example, embodiments of the present invention enable improved protection and layer regrowth options in comparison with conventional techniques. Additionally, the use of deposition and complete or partial removal of SiN layers, in combination with regrowth and etching techniques detailed herein, may provide enhanced dimensional accuracy over conventional techniques. These and other embodiments of the invention, along with many of its advantages and features, are described in more detail in conjunction with the text below and attached figures.
In the appended figures, similar components and/or features may have the same reference label. Further, various components of the same type may be distinguished by following the reference label by a dash and a second label that distinguishes among the similar components. If only the first reference label is used in the specification, the description is applicable to any one of the similar components having the same first reference label irrespective of the second reference label.
Embodiments of the present invention relate to electronic devices. More specifically, the present invention relates to forming semiconductor devices including gallium-nitride (GaN) based layers and one or more layers of in-situ SiN. Merely by way of example, the invention has been applied to methods and systems for manufacturing diode structures using gallium-nitride (GaN) based epitaxial layers. The methods and techniques can be applied to form a variety of types of structures for numerous types of semiconductor devices, including, but not limited to, junction field-effect transistors (JFETs), diodes, thyristors, vertical field-effect transistors, thyristors, and other devices, including merged PIN, Schottky diodes, and the like.
GaN-based electronic and optoelectronic devices are undergoing rapid development, and generally are expected to outperform competitors in silicon (Si) and silicon carbide (SiC). Desirable properties associated with GaN and related alloys and heterostructures include high bandgap energy for visible and ultraviolet light emission, favorable transport properties (e.g., high electron mobility and saturation velocity), a high breakdown field, and high thermal conductivity. In particular, electron mobility, μ, is higher than competing materials for a given background doping level, N. This provides low resistivity, ρ, because resistivity is inversely proportional to electron mobility, as provided by equation (1):
where q is the elementary charge.
Another superior property provided by GaN materials, including homoepitaxial GaN layers on bulk GaN substrates, is high critical electric field for avalanche breakdown. A high critical electric field allows a larger voltage to be supported over smaller length, L, than a material with a lower critical electric field. A smaller length for current to flow together with low resistivity give rise to a lower resistance, R, than other materials, since resistance can be determined by equation (2):
where A is the cross-sectional area of the channel or current path.
A Schottky diode is formed by an interface between lightly n-type doped GaN and a metal with a larger work function than the GaN, such as nickel. In order to fully utilize the high critical field properties of GaN, edge termination can be utilized for the Schottky contact to avoid premature breakdown between the underlying n-GaN and the Schottky metal at the metal corner. In order to form a field plate for edge termination, an insulator may be utilized on the GaN surface. According to aspects of the present invention, in-situ SiN may be utilized for this layer, or as a part of this layered structure. According to other aspects of the invention, an in-situ SiN layer may be partially removed prior to selective regrowth of an additional layer, such as a p+ GaN regrowth layer.
The inventors have determined that many GaN-based devices may benefit from in-situ SiN deposition, for example, immediately following growth of a final (Al)GaN layer. The SiN layer may be used to protect the (Al)GaN, or other, surface from contamination during device processing. For example, during processing, GaN and/or AlGaN surfaces and the like, may advantageously be maintained in-situ while a SiN layer is deposited, and the SiN layer may be maintained during subsequent processing steps that may include air exposure, etching environments, and/or chemical contamination, any of which may damage exposed GaN and/or AlGaN surfaces. In some embodiments, the SiN, or portions thereof, may be removed as necessary, for example prior to deposition of a metal to form a Schottky contact. Devices that may be fabricated according to such methods may include, for example, Schottky barrier diodes, PiN diodes, thyristors, and many variations of transistors including JFETS, MISFETS, HEMTs, and the like. The following non-limiting examples describe a few such devices that may include a SiN layer grown in the reactor, e.g. after III-N growth.
According to embodiments of the present invention, the use of an in-situ SiN layer following growth of an n-GaN layer, for example, may beneficially protect the surface during the entire device process, e.g., up until deposition of a Schottky metal. The in-situ SiN layer can be referred to as an in-situ protective layer. In a particular embodiment, the in-situ SiN material can be partially or wholly removed prior to the metal deposition process for the Schottky contact, e.g., by wet or dry etching using KOH or CF4 plasma.
A SiN layer is formed in-situ, i.e., in the growth reactor, and is coupled to the GaN drift layer (1020). The SiN layer may be deposited according to techniques known in the art, and may include, for example, Si3N4, SiNx or other compositions. Thus, the use of the term “SiN” layer is intended to include all compositions of materials including silicon and nitrogen in stoichiometric and other proportions. In embodiments, the in-situ SiN layer may be formed, for example, using silane from a doping source or a separate direct silane source or any Si precursor. Reactive N2 is also typically provided in the form of NH3 that would be already present for GaN growth. In some embodiments, an additional ex-situ SiO2, oxynitride, or Al2O3 layer may be applied to the in-situ SiN layer, or remaining portions of the SiN layer, e.g., to provide even further selectivity for subsequent regrowth steps or the like. Other in-situ layers could include a lower temperature polycrystalline GaN or AN layer that could easily be removed by wet etching after processing.
The method 1000 also includes patterning portions of the SiN layer and the first epitaxial layer (1030), and optionally removing portions of the SiN layer and underlying portions of the GaN drift layer, e.g., to form windows in which a p+ GaN layer may be regrown during later stages of the fabrication process. The patterned removal of portions of the SiN layer and the GaN drift layer may be accomplished, for example, by etching and other techniques known in the art. The removal of portions of the SiN layer and the GaN drift layer may result in a plurality of epitaxial structures.
The method additionally includes forming another epitaxial layer, such as a regrown p+ GaN layer, for example, in the areas not covered by the remaining SiN layer (1040). That is, a GaN layer may be regrown as a second epitaxial layer in the portions, in plan view, no longer coated with SiN.
The method further includes forming an additional SiN layer over the second epitaxial layer and optionally patterning this layer and the remaining SiN and/or GaN drift layer (1050). In embodiments, the additional SiN layer may be formed in-situ without breaking chamber from S1020. The remaining SiN from the initial in-situ layer may be removed prior to forming the additional SiN layer, or it may be subsumed in the additional SiN layer. The additional SiN layer may formed as a blanket coating, and may also be etched, or otherwise patterned, as needed, for formation of additional structures, such as contacts, etc.
The method also includes forming additional structures (e.g., metallic structures) over the second SiN layer and/or any exposed portions of the regrown GaN layer and/or GaN drift layer (1060). For example, a metallic structure suitable for use as a Schottky contact may be formed in contact with the exposed portions of the regrown GaN layer and the GaN drift layer, e.g., in a space where the new SiN layer has been etched away. Other structures may also be formed including, for example, various edge termination structures, or the like.
It should be appreciated that the specific steps illustrated in
As shown in
The properties of the first GaN epitaxial layer 112 can also vary, depending on desired functionality. As discussed further herein, the first GaN epitaxial layer 112 can serve as a drift region for the Schottky diode, and therefore can be a relatively low-doped material. For example, the first GaN epitaxial layer 112 can have an n−conductivity type, with dopant concentrations ranging from 1×1014 cm−3 to 1×1018 cm−3. Furthermore, the dopant concentration can be uniform, or can vary, for example, as a function of the thickness of the drift region.
The thickness of the first GaN epitaxial layer 112 can also vary substantially, depending on the desired functionality. As discussed above, homoepitaxial growth can enable the first GaN epitaxial layer 112 to be grown far thicker than layers formed using conventional methods. In general, in some embodiments, thicknesses can vary between 0.5 μm and 100 μm, for example. In other embodiments thicknesses are greater than 5 μm. Resulting parallel plane breakdown voltages for the Schottky diode 100 can vary depending on the embodiment. Some embodiments provide for breakdown voltages of at least 100V, 300V, 600V, 1.2 kV, 1.7 kV, 3.3 kV, 5.5 kV, 13 kV, or 20 kV.
Different dopants can be used to create n- and p-type GaN epitaxial layers and structures disclosed herein. For example, n-type dopants can include silicon, oxygen, or the like. P-type dopants can include magnesium, beryllium, calcium zinc, or the like.
As also shown in
The inventors have determined that structural damage may be present at the interface of subsequently regrown layers due, for example, to the fact that GaN-based materials are quite hard and present issues for the etching processes that are commonly used, sometimes utilizing a significant sputtering component. Therefore, for example, regrowth of a p-type GaN layer on an n-type GaN surface may result in the formation of a p-n junction that is characterized by less than optimal electrical characteristics including leakage currents. Without limiting embodiments of the present invention, the inventors believe that in-situ formation of a SiN layer, which may be partially or totally removed later, over the GaN epitaxial layer used as the regrowth surface can be effective in protecting the GaN layer and result in better junction formation during regrowth or other growth processes.
Referring to
Although a plurality of recessed trenches are illustrated in
It should be noted that the recesses 118, and other structural features related to partial removal of epitaxial layers, may be variously sized depending on, for example, specific structure and device parameters. According to various embodiments described herein, epitaxial structures can be sized and spaced to form edge termination structures, while other epitaxial structures may be used to form p-type contacts or buried structures. For example, according to some embodiments, p-type contacts can range from 2 μm to 20 μm wide, and buried structures can range from 0.5 μm to 10 μm wide. Additionally, according to some embodiments, the distance between buried structures and/or contacts can range from 0.2 μm to 10 μm in length. In some embodiments, an n-type epitaxial regrowth layer may be used to control potential between floating p-type edge termination structures. One of ordinary skill in the art would recognize such passivation can be utilized in other embodiments provided herein.
Referring to
The thickness of the second GaN epitaxial layer 122 can vary, depending on the process used to form the layer and the device design. In some embodiments, the thickness of the second GaN epitaxial layer 122 is between 0.1 μm and 5 μm. In other embodiments, the thickness of the second GaN epitaxial layer 122 is between 0.3 μm and 1 μm.
The second GaN epitaxial layer 122 can be highly doped, for example in a range from about 5×1017 cm−3 to about 1×1019 cm−3. Additionally, as with other epitaxial layers, the dopant concentration of the second GaN epitaxial layer 122 can be uniform or non-uniform as a function of thickness. In some embodiments, the dopant concentration increases with thickness, such that the dopant concentration is relatively low near the first GaN epitaxial layer 112 and increases as the distance from the first GaN epitaxial layer 112 increases. Such embodiments provide higher dopant concentrations at the top of the second GaN epitaxial layer 122 where metal contacts can be subsequently formed. Other embodiments may utilize heavily doped contact layers (not shown) to form ohmic contacts.
One method of forming the second GaN epitaxial layer 122, and other layers described herein, can be through a regrowth process that uses an in-situ etch and diffusion preparation processes. These preparation processes are described more fully in U.S. patent application Ser. No. 13/198,666, filed on Aug. 4, 2011, the disclosure of which is hereby incorporated by reference in its entirety.
Referring to
Metal layer 130 may be, for example, one or more layers of ohmic metal that serve as a contact for the cathode of a Schottky diode. For example, the metal layer 130 can comprise a titanium-aluminum (Ti/Al) ohmic metal. Other metals and/or alloys can be used including, but not limited to, aluminum, nickel, gold, combinations thereof, or the like. In some embodiments, an outermost metal of the metal layer 130 can include gold, tantalum, tungsten, palladium, silver, or aluminum, combinations thereof, and the like. The metal layer 130 can be formed using any of a variety of methods such as sputtering, evaporation, or the like.
The device 100 illustrated in
Although some embodiments, such as that depicted in
The fabrication process illustrated in
It should also be noted that the inventive concepts described herein can be applied to various devices where, for example, an in-situ SiN layer can be deposited after a GaN layer, and then subsequently completely or partially removed during device processing. In the example provided in
According to aspects of the invention, an in-situ SiN layer 222 is also be provided over second GaN epitaxial layer 220. As shown in
For example, in some embodiments, the GaN substrate 300 can have an n+ conductivity type with dopant concentrations ranging from 1×1017 cm−3 to 1×1019 cm−3, and the first GaN epitaxial layer 310 can have a n−conductivity type, with dopant concentrations ranging from 1×1014 cm−3 to 1×1018 cm3. The thickness of the first GaN epitaxial layer 310 can be anywhere from 0.5 μm and 100 μm or over 100 μm, depending on desired functionality and breakdown voltage. The channel region 324, which can have a n− conductivity type with a dopant concentration similar to the first GaN epitaxial layer 310, can be anywhere from between 0.1 μm and 10 μm thick, and the width of the channel region 324 (i.e., the distance between gate regions 322) for a normally-off vertical JFET can be between 0.5 μm and 10 μm. For a normally-on vertical JFET, the width of the channel region 324 can be greater. The source region 326 can have a thickness of between 500 Å and 5 μm and an n-type conductivity with a dopant concentration equal to or greater than 1×1018 cm3. The gate regions 322 and the edge termination structures 320-1, 320-2, 320-3 can be from 0.1 μm and 5 μm thick and have a p+ conductivity type with dopant concentrations in a range from about 1×1017 cm−3 to about 1×1019 cm−3. Gate regions 322 and the edge termination structures 320-1, 320-2, 320-3 may be formed as discussed herein using various applications and removal of an in-situ SiN layer.
As shown in
The method also includes forming a second GaN epitaxial layer having a second conductivity type over the first GaN epitaxial layer (2020). For instance, if the first conductivity type is an n-type conductivity, the second conductivity type can be a p-type conductivity, and vice versa. The second GaN epitaxial layer may be coupled to, for example, an AlGaN layer, or etch stop layer, if present. In some embodiments, the second GaN epitaxial layer may be used to form gate, edge termination, or other structures, and may be a continuous regrowth over the AlGaN layer and/or portions of the first GaN epitaxial layer. As mentioned previously, one method of forming the second GaN epitaxial layer, and other layers described herein, can be through a regrowth process that uses an in-situ etch and diffusion preparation processes, e.g., as described more fully in U.S. patent application Ser. No. 13/198,666, filed on Aug. 4, 2011, the disclosure of which is hereby incorporated by reference in its entirety.
The method further includes forming an in-situ SiN layer, i.e. in the growth reactor, coupled to the second GaN epitaxial layer (2030). The in-situ SiN layer may be deposited according to techniques known in the art, and may include, for example, Si3N4, SiNx or other suitable compositions.
Portions of the SiN layer, and underlying portions of the second GaN epitaxial layer are removed (2040), e.g. to form one or more diode contact structures or the like. The patterned removal of portions of the SiN layer and the second GaN epitaxial layer may be accomplished, for example, by etching down to an AlGaN layer etch stop layer, if present, and other techniques known in the art.
Additional structures are formed, for example, using deposition and/or patterning and removal processes on the surface of the AlGaN layer, if present, or exposed surfaces of the first or second GaN epitaxial layers (2050). Such structures may include, for example, source and/or drain ohmic contacts, Schottky contacts, metal-insulator stacks, pn junctions or the like. Additional structures may be metallic, such as Ti/Al, dielectrics like silicon nitride, or semiconductor materials including additional III-nitride layers. Remaining portions of the SiN layer may optionally be removed during this process, such as those remaining over portions of the second GaN epitaxial layer to be used for contacts, field plates, or the like.
Additionally, the method includes forming additional metallic structures, e.g., a Schottky gate metal over a remaining portion of the second GaN epitaxial layer (2060). For example, a metallic structure forming a Schottky contact may be formed in contact with the exposed portions of the second conductivity type GaN epitaxial layer. Other structures may also be formed including other types of gates such as pn junctions or MIS capacitor or, for example, various edge termination structures, or the like.
It should be appreciated that the specific steps illustrated in
As shown in
The thickness of the AlGaN layer 430 can vary, depending on the process used to form the layer and the device design. In some embodiments, the thickness of the AlGaN layer 430 may be between 20 and 500 Å, for example.
The thickness of the second GaN (or AlGaN) epitaxial layer 440 can vary, depending on the process used to form the layer and the device design. In some embodiments, the thickness of the second GaN epitaxial layer 440 is between 100 Å and 3 μm. In other embodiments, the thickness of the second GaN epitaxial layer 440 is between 0.1 μm and 1 μm.
As shown in
The removal can be performed by a controlled etch using an etch mask (not shown but having the dimensions of the remaining portions of SiN layer 450 and second epitaxial layer 440) designed to stop at approximately the interface between the second epitaxial layer 440 and the AlGaN layer 430. Inductively-coupled plasma (ICP) etching and/or other common GaN etching processes can be used. In the illustrated embodiment, the material removal process used to remove portions of the SiN layer 450 and second epitaxial layer 440 terminates at the interface of layer 440 and layer 430, however, in other embodiments, the process may terminate at a different depth, for example, extending into or leaving a portion of the AlGaN layer 430 and/or first GaN epitaxial layer 420.
As shown in
The remaining portions of the SiN layer 450 may be removed prior to subsequent processing and addition of the ohmic metal contact over the second GaN epitaxial layer 440. For example, prior to metal deposition of the ohmic contact, the in-situ SiN can be removed by wet or dry etching using for example, KOH or CF4 plasma, respectively.
The first metallic structure 530 can be one or more layers of ohmic metal that serve as a contact for the cathode of the PIN diode. For example, the metallic structure 530 can comprise a titanium-aluminum (Ti/Al) ohmic metal. Other metals and/or alloys can be used including, but not limited to, aluminum, nickel, gold, combinations thereof, or the like. In some embodiments, an outermost metal of the metallic structure 530 can include gold, tantalum, tungsten, palladium, silver, or aluminum, combinations thereof, and the like. The first metallic structure 530 can be formed using any of a variety of methods such as sputtering, evaporation, or the like.
As shown in
According to aspects of the invention, a SiN layer may be deposited in-situ during the fabrication process of the device shown in
Second metallic structure 560 is electrically coupled to the device structure 520-3. This second metallic structure 560 can be formed using the same techniques used to form the metallic structure 530, and also can include similar metals and/or alloys. The second metallic structure 560 electrically coupled to the device structure 520-3 can serve as an electrical contact (e.g., an anode) for the PIN diode.
As also shown in
One of ordinary skill in the art would recognize many variations, modifications, and alternatives to the examples provided herein. As illustrated herein, edge termination structures can be provided in a variety of shapes and forms, depending on physical features of the semiconductor device for which the edge termination structures provides its function. For instance, in certain embodiments, edge termination structures may not circumscribe the semiconductor device. Additionally or alternatively, conductivity types of the examples provided herein can be reversed (e.g., replacing an n-type semiconductor material with a p-type material, and vice versa), depending on desired functionality. Moreover, embodiments provided herein using GaN can use other III-nitride materials in addition or as an alternative to GaN. Other variations, alterations, modifications, and substitutions are contemplated.
It is also understood that the examples and embodiments described herein are for illustrative purposes only and that various modifications or changes in light thereof will be suggested to persons skilled in the art and are to be included within the spirit and purview of this application and scope of the appended claims.
