Patent Application
20220285505
The present disclosure relates to indium-gallium-nitride (InGaN) layers having a substantially relaxed region and to devices fabricated upon the InGaN layers. The substantially relaxed Wurtzite (0001) InGaN regions have an in-plane, or “a”, lattice parameter greater than or equal to 3.19 Å. The substantially relaxed InGaN regions are grown on a plurality of III-nitride seed regions such as GaN, InGaN, AlGaN, or MN seed regions. During growth, InGaN grown on the seed regions relaxes and coalesces to provide substantially relaxed InGaN regions that can be used as a growth surface for other semiconductor materials. The InGaN layers can be used to fabricate optical and electronic devices for use as light sources in systems for illumination and display applications.
Compound semiconductor materials are typically deposited, or grown, atomically-lattice-matched to a growth substrate to avoid the generation of growth defects such as dislocations. In some cases, it is desirable that the lattice parameter of a compound semiconductor material be altered to provide materials and/or devices and/or systems with particular characteristics.
InGaN is currently the material of choice for the active layer(s) of GaN-based optoelectronic devices including, for example, blue- or violet-emitting light-emitting diodes (LED) which are currently the basis for most LED-based illumination and display systems commercialized to date, and the violet-emitting laser diode (LD) which is the basis for the Blu-Ray™ industry. Today, such devices are manufactured using InGaN active layers grown pseudomorphically on gallium-nitride (GaN) epitaxial layers. Unfortunately, the crystalline atomic lattice parameter of InGaN is larger than that of GaN, resulting in severe strain, and increasingly poor material quality with increasing InN mole fraction or increasing thickness for InGaN grown on GaN (InGaN/GaN). This limits the performance of optoelectronic devices based on InGaN/GaN including, for example, LEDs and LDs.
Attempts to grow high-quality, planar, relaxed InGaN for device applications have so far been unsuccessful in commercialization. Graded-layer approaches, used in certain III-V material systems, have been attempted for InGaN using low-temperature molecular beam epitaxy (MBE). However, the relaxation mechanism is associated with the appearance of a high density of misfit dislocations, stacking faults, and threading dislocations, leading to poor material quality. Similar approaches using commercially preferred metal organic chemical vapor deposition (MOCVD) for c-plane InGaN are compromised by the lack of a slip system for (polar) c-plane growth and attempts to exploit non- and semi-polar growth planes result in material having a high defect density. Hydride vapor phase epitaxy (HYPE) has been used to grow thick InGaN layers with the objective of reducing crystalline defects, but the approach is limited in terms of achievable InN mole fractions and is only applicable to N-polar surfaces and therefore is not ideal for low-cost manufacturing. Growth of strained InGaN layers that can be lifted-off and bonded to compliant carriers to facilitate relaxation has been attempted, but the method results in limited lattice dilation and non-planar, trenched, surfaces. The use of nano-column or nano-rod device structures designed to avoid strain limits of conventional heteroepitaxy results in non-planar device geometries less suitable for manufacturing and can exhibit low optical quality.
The use of patterning and re-growth has been used to grow high quality, lattice-mismatched heteroepitaxy for single-element (e.g., Ge on Si) and binary III-V (e.g., GaAs on Si) zinc-blende semiconductors. However, similar approaches for Wurtzite semiconductors and/or ternary alloys such as InGaN have not been successful.
According to the present invention, a III-nitride semiconductor structure, comprises (a) seed regions comprising InxGa1-xN (0≤x<1) and a Wurtzite III-nitride crystal structure; (b) a first plane parallel to a (0001) plane of the Wurtzite III-nitride structure and intersecting the seed regions; wherein, an intersection of the first plane and a first edge of a seed region locates a InxGa1-xN/InyGa1-yN heterojunction, wherein 0<y≤1 and y>x; and the InxGa1-yN/InyGa1-yN heterojunction is coplanar with a first crystallographic plane of the seed region; (c) any second plane parallel to the (0001) plane of the Wurtzite III-nitride crystal structure and intersecting a second edge of the seed region locates a III-nitride heterojunction, wherein the III-nitride heterojunction is coplanar with a second crystallographic plane of the seed region; and (d) a (0001) InGaN region overlying the seed regions, wherein the (0001) InGaN region is characterized by an in-plane a-lattice parameter that is greater than 3.19 Å, wherein each of the first crystallographic plane and the second crystallographic plane is crystallographically equivalent.
According to the present invention, semiconductor devices comprise a III-V semiconductor structure according to the present invention.
According to the present invention, lighting systems comprise the semiconductor device according to the present invention.
According to the present invention, display systems comprise the semiconductor device according to the present invention.
Those skilled in the art will understand that the drawings described herein are for illustration purposes only. The drawings are not intended to limit the scope of the present disclosure.
“Substantially uniform lattice parameter” refers to a semiconductor layer characterized by a local lattice parameter of the semiconductor layer that varies less than 1% with respect to an average lattice parameter such as, for example, less than 0.5% with respect to an average lattice parameter, or less than 0.1% with respect to an average lattice parameter.
“Defect density” refers to the density, in plain view, of extended defects, such as dislocations, in a semiconductor layer. The defect density can be determined using, for example, etching (and counting etch pit density, EPD), cathodoluminescence to observe and count dark spots, atomic force microscopy (AFM) to observe and count small pits.
A lattice parameter can be determined using X-ray diffraction (XRD) and reciprocal space map (RSM) analysis. High-angle, or near grazing incidence, XRD techniques can be used to determine the lattice parameter of upper layers in a structure in which the lattice parameter may vary as a function of depth.
“III-V material” refers to a compound semiconductor material comprising at least one column-III element and at least one column-V element from the Periodic Table.
“Growth plane” refers to a plane parallel to the deposition plane of material onto a planar surface, such as that of a conventional substrate growth surface.
“Substantially perpendicular to the growth plane” refers to a surface that forms an angle with respect to the growth plane that is approximately 90 degrees such as from 88 degrees to 92 degrees with respect to the growth plane.
Wurtzite GaN is characterized by a Wurtzite crystal structure having room-temperature a- and c-lattice parameters of 3.189 Å, and 5.185 Å, respectively. The crystal plane normal to the c-lattice parameter direction (“c-direction”) is the c-plane, which has a Ga-face (0001) and a N-face (000-1). The plane that contains the c-direction and is perpendicular to the a-lattice parameter direction (“a-direction”) is the (11-20) plane, or “a-plane”. The plane containing the c-direction and rotated 30 degrees with respect to the a-direction is the (1-100) plane, or “m-plane”.
Wurtzite InxGa1-xN has the same crystal structure as Wurtzite GaN, but includes a non-zero molar fraction of InN, x, to form a ternary compound wherein a specified fraction of column-III atoms are In and the remainder are Ga. InN has room-temperature a- and c-lattice parameters of 3.545 Å, and 5.703 Å, respectively, and InxGa1-xN has room-temperature a- and c-lattice parameters of between that of GaN and InN, and according to the molar fraction.
Although the present description focuses on growing (0001) InGaN on a GaN seed surface, the method is applicable to other Wurtzite materials, such as InGaN on MN, AlGaN on MN, and AlGaN on GaN. Furthermore, the invention is applicable to non-basal-plane Wurtzite structures, such as so-called non- and semi-polar GaN and related materials. Finally, the invention is also applicable to other compound semiconductor systems, including zinc blende materials such as InGaAs on GaAs, and InGaSb on GaSb, and II-VI compound semiconductor systems.
“Relaxed InGaN” refers to InGaN material that exhibits an in-plane lattice parameter that is equal to, or nearly equal to, that of fully relaxed InGaN material. For example, Wurtzite relaxed InGaN has a room-temperature a-plane lattice parameter greater than 3.189 Å(0% InN) and up to 3.545 Å (100% InN). This is in contrast to a strained InGaN material, such as InGaN which is grown pseudomorphic to GaN and thus exhibits an in-plane lattice parameter equal to, or nearly equal to, that of GaN (that is, ˜3.189 Å), regardless of InN mole fraction. Such strained InGaN material is referred to as InGaN/GaN.
“In-plane lattice parameter” refers to crystal lattice spacing within the growth plane. For (0001) material, the in-place lattice parameter is the a-lattice parameter.
“Lateral growth” refers to growth in a direction other than normal to the growth plane, including parallel to the growth plane.
Reference is now made in detail to certain embodiments of materials, semiconductor structures, optoelectronic devices, and methods. The disclosed embodiments are not intended to be limiting of the claims. To the contrary, the claims are intended to cover all alternatives, modifications, and equivalents.
The present invention teaches the formation of a large-area, planar, coherent, at least partially but substantially uniformly relaxed compound semiconductor material layer for use in an optical and/or electronic device. Large area refers to areas larger than 1 mm2 such as larger than 1 cm2 in extent. Planar refers to a semiconductor layer that exhibits at least one surface that is substantially flat and is largely free of significant thickness variations within the large area. For example, a planar semiconductor layer can have an RMS roughness less than 1 nm, as determined using atomic force microscopy. A planar semiconductor layer can have a thickness, for example, within +/−10% of the average thickness. Coherent refers to the fact that the material is substantially crystalline, as opposed to amorphous. Relaxed refers to the fact that the in-plane lattice parameter of the material is approximately that of a free-standing, coherent, 100% relaxed version of the material. Substantially relaxed refers to a material in which the in-plane lattice parameter of the material is within 30% of that of a free-standing, coherent, 100% relaxed version of the material. Uniformly refers to a substantially non-varying in-plane lattice parameter within the large area, upon which optical and/or electronic device structures can be built. In addition, the invention is applicable to a wide range of semiconductor crystal systems, including Wurtzite crystal structures, and to high-order alloys including ternary and quaternary alloys. Finally, the invention is suitable for structures grown by a number of growth methods, but in particular metal-organic chemical vapor deposition (MOCVD).
In particular, the present invention teaches the formation of a large-area, planar, coherent, at least partially but substantially uniformly relaxed indium gallium nitride (InGaN) material layer for use as a base layer for an optical and/or electronic device. Various compositions (i.e., InN molar fractions) are achievable. Coherent refers to the fact that the InGaN material is substantially crystalline, as opposed to amorphous. Relaxed refers to the fact that the InGaN material's lattice parameter is approximately that of a free-standing, coherent, 100% relaxed InGaN material of the same composition. Uniformly relaxed refers to layers with in-plane lattice parameters that are largely non-varying over the vast majority of the large area in a plane containing the growth plane. Such relaxed InGaN material is referred to, in the present invention, as relaxed InGaN such as Native InGaN®.
The invention further teaches the formation of optical and/or electrical devices and systems based on said Relaxed InGaN, which may include other InGaN layers grown pseudomorphically to relaxed InGaN (i.e., InGaN/InGaN), such as Native InGaN®.
Other features and aspects of this invention will be apparent from the following description and the accompanying drawings. In particular, the teachings in the present invention are applicable to other compound semiconductor device materials, such as aluminum gallium nitride, aluminum gallium indium nitride, III-As, III-P, III-Sb, etc.
The present invention discloses the use of a semiconductor seed material deposited on a substrate to register crystalline growth of a compound semiconductor material. The seed material has a plurality of seed regions with edges that are planar seed surface portions and each normal to these planar seed surface portions have a crystallographically equivalent direction that is not parallel to a normal to the large area of the substrate. The limited (preferably, one) number of exposed planar seed surface crystallographically equivalent orientations ensures uniform relaxation and compositional control of the InGaN material grown thereon, avoiding competing growth modes and problems associated with uncontrolled compositional control such as non-uniform InN incorporation, rough surfaces, etc., when variable seed surface orientations are presented for InGaN growth simultaneously. The dimensions of the seed surface portions are limited in extent such that additional compound semiconductor material can be seeded and readily relax, during growth, towards its relaxed lattice parameter. The resulting “relaxed” compound semiconductor material is subsequently grown out and coalesced to form a large-area (i.e., area greater than ×1 mm2, preferably greater than 1×1 cm2) film. The large-area, relaxed compound semiconductor material film provides a template for the growth of improved optical and/or electronic device structures.
In particular, the present invention discloses the use of GaN seed regions with seed surface portions to register crystalline growth of InGaN. The dimensions of, and geometries associated with the GaN seed surface(s) are limited in extent such that the InGaN material can be seeded and readily relax during growth towards its relaxed lattice parameter. The crystallographic direction characterizing the normals to the planar seed surface portions may be a non-polar direction, such as (11-20) or (1-100) or a plane rotated between them, or a semi-polar direction, such as (1-101). The (relaxed) InGaN layer is subsequently grown out and coalesced into a planar, large-area film. The large-area, relaxed InGaN film provides a template for the growth of improved InGaN-based optical and/or electronic device structures.
An example of a method for growing a relaxed InGaN region is shown in
As shown in
The orientation of the GaN seed surface can be determined by the patterning and upon the growth orientation of the GaN layer. The orientation of the seed surface is further dependent on the angle of the surface of the etched GaN layer. For example, for a (0001) GaN layer and near vertical etching, the orientation of the GaN seed surface can vary from approximately (1-100) to (11-20) and any orientation rotated in between them. This orientation can be selected to optimize InGaN growth conditions and InGaN material quality.
For InGaN growth on certain GaN seed surfaces, especially those substantially perpendicular to the main surface of the substrate, to facilitate coalescence, it may be desirable to enhance lateral-vs-vertical growth by optimizing growth conditions and/or choosing GaN seed surface orientation that promotes a fast growth rate.
The small dimensions of the GaN seed surface promote relaxation of the InGaN material deposited thereon, and provides a planar, crystallographic orientation to facilitate coherent InGaN growth. During growth, InGaN grows coherently and relaxes toward its relaxed lattice parameter, and eventually coalesces with a neighboring InGaN growth front. Referring to
In the present InGaN growth method, relaxation occurs mostly laterally, i.e., by twist, rather than by tilting which occurs when InGaN relaxation is attempted directly on a GaN (0001) surface. The latter approach introduces vertical InGaN strain gradients which become problematic during subsequent growth and coalescence of the InGaN. Instead, the present invention provides for reduced tilting which allows the final coalesced film to be substantially free of strain and/or compositional inhomogeneities, thus providing a high quality planar relaxed InGaN large-area surface for semiconductor growth. Moreover, because relaxation occurs uniformly at the GaN seed surface, vertical strain gradients, which can be generated when strained layers are first grown pseudomorphically (then etched and relaxed), are largely avoided.
In the InGaN growth methods provided by the present disclosure, InGaN growth is to occur mainly at surfaces of the GaN seed material, and growth of InGaN on other exposed surfaces should be minimized or avoided altogether. For this reason, it can be beneficial to etch through the GaN seed material and into the underlying substrate, to move the substrate growth surface away from the InGaN nucleation region. In addition, growth conditions of the InGaN layer can be selected to promote growth at one or more GaN seed surfaces as opposed to InGaN nucleation and growth on the substrate, which would present a competitive growth mode. This approach is illustrated in
The InGaN material is coalesced above the masking layer 1303 to form a relaxed InGaN region 1304 with planar InGaN surface 1305c. A plane 1308a parallel to the primary surface of the original growth substrate and positioned within relaxed InGaN region 1304 is predominantly characterized by an in-plane a-lattice parameter a2. In particular, at a center point 1305 between the GaN seed surfaces, the InGaN lattice parameter along plane 1308a is characterized by a2, and at a center point above the GaN seed surfaces, the InGaN a-lattice parameter along plane 1308a is slightly less than a2. In plan-view (not shown) the variation in in-plane a-lattice parameter within plane 1308a is characterized by the two-dimensional mask pattern applied to the GaN seed layer (see
GaN seed regions 1302 have in-plane dimensions, for example, that are less than 3 μm, less than 0.3 μm, or less than 0.03 μm. The height of GaN seed regions 1302 can be, for example, less than 3 μm, less than 0.3 μm, or less than 0.03 μm. The distances between neighboring GaN seed regions 1302, e.g., the width of GaN seed regions 1302, can be less than 3 μm, less than 0.3 μm, or less than 0.03 μm. The thickness of mask layer 1303 can be, for example, from 0.01 μm to 1 μm, from 0.02 μm to 0.8 μm, from 0.05 μm to 0.5 μm, or from 0.1 μm to 0.4 μm.
Further control over thickness and compositional uniformity of the relaxed InGaN growth may be provided by growing multilayer structures, rather than using bulk InGaN layers. For example, a 25% bulk InGaN layer may be replaced, for example, by alternating layers of 3 nm GaN and 1 nm InN, or 2 nm GaN and 2 nm In0.5Ga0.5N. Layer thicknesses for the individual layers can range, for example, from 0.5 nm to 100 nm, such as from 1 nm to 30 nm. Multiplayer structures are not limited to the base layer but may be used throughout the epitaxial stack including the semiconductor device layers such as n-type, p-type and active layers overlying the relaxed InGaN layer, or in layers between the relaxed InGaN base layer and the device layers.
The increased lattice parameter of the relaxed InGaN layer compared to that of InGaN/GaN allows for growth of subsequently deposited semiconductor layers at much higher temperatures than for InGaN/GaN. For example, InGaN with an a-lattice parameter of 3.205 Å has been shown to incorporate about 7% InN, compared to about 4% for InGaN/GaN. Because InN mole fraction incorporation into GaN is inversely proportional to growth temperature in MOCVD, this suggests that an InGaN a-lattice parameter increase of about 0.015 to 0.020 can increase the useful growth temperature by about 50° C. Further increases in InGaN a-lattice parameter will allow even higher temperatures to be used for the same InN mole fraction. This effect can be exploited not only in the realization of higher quality semiconductor layers grown on relaxed InGaN achieved by reduced point-defect formation at higher temperatures, but also by the reduction or elimination of pits that occur at the location of threading dislocations in the surfaces of InGaN films. Ideally, the growth temperature of the InGaN layers is kept sufficiently high to eliminate or at least restrict the pits to diameters much less than 1 μm, such as less than 200 nm, or less than 50 nm. Small pits can be “filled” using thin, high-temperature GaN or AlGaN layers grown over the pitted InGaN films.
Methods provided by the present disclosure can include recursion, which may be helpful in obtaining large lattice parameter changes. For example, a relaxed InGaN layer may be used as a seed layer, to provide seed surfaces for growth of higher-InN mole fraction layers. The resulting, new relaxed InGaN layer, could then be used as a seed layer in another turn of the process, and so on. This approach may be helpful in obtaining relaxed InGaN layers with very high InN mole fractions, which may be suitable as base layers for the growth of active semiconductive layers for emitting at long wavelengths, such as beyond red, to deep red and even infra-red emission, for example at wavelengths within a range from 700 nm to 1.6 μm.
A relaxed InGaN layer provided by the present disclosure can serve as a template for and/or supporting structure for growing optical and/or electrical devices. Very large area wafers are possible, including 150 mm, 200 mm or larger diameter wafers, which facilitates high volume, low cost manufacturing of these devices.
As an example,
As shown in
The semiconductor structures shown in
Relaxed InGaN layers provided by the present disclosure are applicable to a wide range of compound semiconductor devices which impact the performance of a wide range of system solutions for various applications, including lighting devices and systems (
Target compositions for the a relaxed InGaN layer can be selected according to intended device, application, and performance requirements. For conventional InGaN light-emitting diodes lattice-matched to GaN, the best performing devices are those emitting in the violet wavelength range. At these wavelengths, the strain state of InGaN quantum wells with respect to the GaN base layers is from about 1% to 2%. The corresponding compositional differences are sufficiently high such that bandgap engineering can provide very high quantum efficiency devices, while the strain state is sufficiently low to allow for relatively thick InGaN quantum well (QW) layers which serve to reduce carrier density and mitigate non-radiative Auger recombination (aka “droop”). Applying this acceptable range of strain states to other emission wavelengths, preferred compositional ranges for relaxed InGaN base layers provided by the present disclosure can be calculated for a wide range of emitters, from blue (about 450 nm) to the infra-red (about 1.3 μm) wavelengths. The preferred ranges are listed in Tables 1 and 2.
12%
x
min=−6.046E-07λ2+1.837E-03λ−6.917E-01,(λ≥440 nm) EQN. 1
x
max=−6.152E-07+2+1.847E-03λ−6.142E-01,(λ≥440 nm) EQN. 2
Similarly, as a function of peak emission wavelength, λ, the in-plane (“a”) lattice parameter, a, for a relaxed InxGa1-xN base layer should satisfy the condition amin≤a≤amax, where amin and amax are defined by EQN. 3 and EQN. 4, respectively:
a
min=−2.067E-07λ2+6.366E-04λ−2.951,(λ≥440 nm) EQN. 3
a
max=−2.190E-07λ2+6.575E-04λ−2.970,(λ≥440 nm) EQN. 4
Methods and semiconductor structures provided by the present disclosure can be adapted to fabricate Vertical Cavity Surface Emitting Layers (VCSELs). The compositional choices for relaxed InGaN base layers for LDs or VCSELs are similar to those for LEDs and are shown in Tables 1 and 2.
As shown in
The InGaN material is coalesced above the masking layer 1703 to form a relaxed InGaN layer 1704 with planar surface 1705c. A plane 1708a parallel to the primary surface of the original growth substrate and positioned within InGaN layer 1704 near surface1705c is predominantly characterized by an InGaN in-plane a-lattice parameter a2. At a center point 1705 between the GaN seed regions, the InGaN lattice parameter is a2, and at a center point within the GaN seed regions, the in-plane a-lattice parameter slightly less than a2. In plan-view (not shown) the variation in in-plane a-lattice parameter within plane 1708b is characterized by the two-dimensional mask pattern applied to the seed layer material (see
GaN seed regions 1702a can have in-plane dimensions, for example, less than 3 μm, less than 0.3 μm, or less than 0.03 μm. The height of GaN seed regions 1702a can be, for example, less than 3 μm, less than 0.3 μm, or less than 0.03 μm. The distances between neighboring GaN seed regions 1702a can be, for example, less than 3 μm, less than 0.3 μm, or less than 0.03 μm. The thickness of mask material 1703 can be, for example, from 0.01 μm to 1 μm.
A III-nitride semiconductor structure can comprise (a) seed regions comprising InxGa1-xN (0≤x<1) and a Wurtzite III-nitride crystal structure; (b) a first plane parallel to a (0001) plane of the Wurtzite III-nitride structure and intersecting the seed regions; wherein, an intersection of the first plane and a first edge of a seed region locates a InxGa1-xN/InyGa1-yN heterojunction, wherein 0<y≤1 and y>x; and the InxGa1-xN/InyGa1-yN heterojunction is coplanar with a first crystallographic plane of the seed region; (c) any second plane parallel to the (0001) plane of the Wurtzite III-nitride crystal structure and intersecting a second edge of the seed region locates a III-nitride heterojunction, wherein the III-nitride heterojunction is coplanar with a second crystallographic plane of the seed region; and (d) a (0001) InGaN region overlying the seed regions, wherein the (0001) InGaN region is characterized by an in-plane a-lattice parameter that is greater than 3.19 Å. wherein each of the first and second crystallographic planes is crystallographically equivalent.
The first parallel plane can intersect two facets of a seed region. The facets of the seed region are parallel to a crystallographic plane of the seed region, such as a crystallographic plane of a Wurtzite crystal structure. The facets of the seed region can be crystallographically equivalent facets. The intersection of the first parallel plane with a facet of the seed region locates a heterojunction such as a InxGa1-xN/InyGa1-yN where 0≤x<1, 0<y≤1, and y>x.
Any second plane parallel to the 0001) plane of the Wurtzite III-nitride crystal structure and intersecting the seed regions locates a III-nitride heterojunction. The second plane can intersect the same facets as the first plane. The second plane can intersect facets of the seed regions that are coplanar with a crystallographic plane of the seed region. Each of the crystallographically planes can be a crystallographically equivalent plane. Each of the seed regions can be characterized by facets paralleled to crystallographic planes of the seed region such as crystallographic planes of a Wurtzite crystal structure. Each of the crystallographic planes can be crystallographically equivalent planes. Each of the crystallographic planes can be crystallographically equivalent to the {10-11} plane. Each of the crystallographic planes can be crystallographically equivalent to the {1-100} plane. Each of the crystallographic planes can be crystallographically equivalent to the {11-20} plane. Each of the crystallographic planes can be a (1-100) plane or a (11-20) plane.
An InGaN region is situated between the seed regions. The InGaN region, or at least a portion of the InGaN region between the seed regions can be a partially relaxed InGaN region. The InGaN region can comprise more than one InGaN layer where each of the InGaN layers has a different elemental composition. A (0001) InGaN region can overly the seed regions. The (0001) InGaN region can be a fully relaxed InGaN region and can have an in-plane a-lattice parameter that is greater than 3.19 Å, such from 3.20 Å to 3.50 Å.
A seed region can have 2 or more facets, such as 2, 3, 4, 5, or 6 facets. A seed region can have 3 or 6 facets. A seed region can have, for example, a rectangular base, a triangular base, a square base, a pentagonal base, or a hexagonal base. A seed region can have a triangular base or a hexagonal base.
Each seed region can comprise, for example, GaN, and can have, for example, a lattice parameter of about 3.189 Å. Each seed region can comprise GaN and each of the InxGa1-xN/InyGa1-yN heterojunctions and the III-nitride heterojunctions is a GaN—InGaN heterojunction.
For example, as shown in
In another example, the masking step can be eliminated, and the entire process can be completed in situ in the growth chamber. For example, as shown in
Because the (0001) growth surface area is smaller than the (10-11) growth surface area, the latter growth mode dominates, allowing the InGaN to relax and become the dominant growth suface with increasing film thickness. It can be useful to grow the InGaN layers at higher temperatures than is typical for InGaN/GaN growth, which is possible because the relaxed InGaN material can incorporate In much more easily than InGaN pseudomorphic to GaN. The increased growth temperature allows the v-pit defects to fill in to provide a coalesced, planar film. Control over the morphology and compositional uniformity of the relaxed InGaN growth can be facilitated by growing multilayer structures, rather than by using bulk InGaN layers. For example, a 25% bulk InGaN layer may be replaced by alternating layers of 3 nm GaN and 1 nm InN, or 2 nm GaN and 2 nm In0.5Ga0.5N. Layer thicknesses for the individual layers can range, for example, from 0.5 nm to 100 nm, such as from 1 nm to 30 nm. Many periods of such multilayer structures can be used, such as from 2 to 10 layers, from 2 to 100 layers, or greater than 100 layers.
As an example, a c-plane (0001) sapphire substrate can be loaded into a MOCVD reactor capable of supplying at least tri-methyl gallium, tri-methyl indium, and ammonia. A low-temperature GaN nucleation layer can be provided, followed by higher temperature GaN growth which can include three-dimensional island formation before coalescing into a two-dimensional (0001) GaN film. This three- to two-dimensional transition helps redirect threading dislocations laterally and helps to reduce the overall threading dislocation density at the growth surface, which can be reduced to less than 1E9 cm−2. A dislocation density of 1E8 cm−2 can be achieved eventually in the planar GaN layer. Next, the growth temperature can be reduced (e.g., less than 800° C.) to form v-pit structures at dislocation cores, which are characterized by inclined (10-11) planes. These planes can form an angle with respect to the (0001) growth surface of about 63 degrees. The thickness of the low temperature layer controls the v-pit height and is increased by growth such that the total surface area of exposed {10-11} facets is greater than the surfaced area of (0001), as shown in Table 3 for this specific example.
For example, in the case of a dislocation density of 1E8 cm−2, the target v-pit height can be 0.14 μm or greater.
After the target surface area-ratio between the (10-11) and (0001) material can achieved, TMI is flowed into the chamber to grow one or more InGaN layers on the (10-11) seed regions and to induce strain relaxation. The InGaN layers can be alternated by GaN layers periodically. For example, each InGaN layer can be from 0.5 nm to 100 nm thick, such as from 1 nm to 30 nm thick, and can be sandwiched between GaN layers having a similar thickness. To induce strain relaxation, the average composition of the strain relaxation layers should be reasonably high, for example, the average InN content can be greater than 5%. After or before strain relaxation is initiated, the growth temperature can be raised to help planarize the growth and achieve a planar, uniform, relaxed (0001) InGaN layer for device fabrication.
It is important to note that although the foregoing discussion is directed to GaN seed regions, it is also possible to utilize InGaN (or AlGaN) seed regions, provided the material is pseudomorphic to any underlying GaN layer, e.g., GaN nucleation and/or buffer layers. The seed regions are regions in the vicinity of the InGaN—GaN (or InGaN—InGaN) heterojunctions that eventually induce relaxation. The seed material below these regions is referred to as seed material and not seed regions.
Relaxed InGaN layers and semiconductor structures comprising relaxed InGaN layers provided by the present disclosure can be used to fabricate electronic and optoelectronic devices including InGaN-based optoelectronic devices such as LEDs and LDs (and VCSELs). LEDs and LDs comprising relaxed InGaN layers provided by the present disclosure can be used in lighting systems and display systems. In particular, for LEDs, devices may be formed on a relaxed InGaN base layer on a substrate. The substrate can be thinned by techniques such as grinding, lapping, or etching, and can be diced by means known in the art such as sawing, scribe-and-break, or laser scribing and breaking, to provide individual LED chips or dies. LED chips or die dimensions can be from, for example, from 250 μm2 to 10 mm2. Individual LED chips can then be attached to suitable package elements, which provide leads for electrical contacting and heatsinking the devices. Die-attach can be accomplished using any suitable method such as epoxy or silicone attachment, or solder-based attach. Electrical connection for the chip to the package can be completed by using bond wire such as Au or Ag wires, to connect the anode and cathode leads in the package to respective contact metallizations, i.e., electrodes, on the LED chip. In the case of flip-chip devices, electrical contact can be made through an intermediary submount, positioned between the LED chip and package. The chip electrodes can be attached to the submount carrier by means such as solder attach or Au-bump attach. The submount carrier can be diced and then mounted into the package by any suitable method.
Desired emission color from the packaged LED device is obtained by fabricating and providing a relaxed InGaN-based LED, with a desired peak emission wavelength. Multiple such LED chips, optionally with different peak emission wavelengths, can be included in separate packages, or combined together in a multi-chip package. For example, a single package can include red-emitting, green-emitting, and blue-emitting LED chips, which may be arranged in a circuit and electrically coupled to a driver circuit, either within or outside the package, for operating the LEDs. The circuit details and driver can be selected to allow the different color LEDs to operate separately, or together, to provide a wide range of total emission characteristics, including white light emission for use in illumination applications, or for use as a backlight for a liquid crystal display (LCD) device, such as a television display, computer monitor, mobile phone display, wearable display device, etc.
One or more LED chips can be combined with luminescent down-conversion materials to provide a desired emission spectrum. Such luminescent down-conversion materials may include phosphors, semiconductor nanoparticles such as quantum dots, or perovskite materials. Multiple luminescent down-conversion materials can be combined together in a single package. The LED chip emission wavelength can be selected to excite the luminescent down-conversion materials so that emission from the package is a combination of the LED chip direct emission and that of the luminescent down-conversion material, or the emission may be primarily just that of the luminescent down-conversion material, with the LED chip light fully absorbed by the luminescent down-conversion materials or otherwise blocked or filtered from exiting the package. Packaged LEDs using luminescent down-conversion materials can be used to produce white light, which can be useful in illumination applications. Such devices can be electrically coupled to driver circuits, powered by an external power source such as mains or battery power, thermally coupled to a heatsink, and optically coupled to various optics or lenses to provide lighting devices such as LED lamps or LED light fixtures.
LED chips with smaller dimensions may be fabricated using the present invention. In particular, devices with dimensions from 1 μm2 to 50 μm2, so called “microLEDs”, can be fabricated. For micro-LEDs, conventional dicing techniques are less suitable and therefore other means for singulating devices are often employed. For example, dicing may be enabled by forming LEDs of desired dimensions on a substrate, and then bonding the top surfaces of the LEDs to a carrier, such as blue tape or a submount carrier, then removing the substrate. The individual devices may then be picked up and placed into a package element or onto a backplane for microLED based display. Advanced die-handling techniques, as known in the art, can be used for handling microLED devices. In particular, red-emitting, green-emitting, and blue-emitting LEDs based on the present invention may be formed into microLEDs and arranged to provide a microLED display and incorporated into systems such as televisions, computer monitors, tablets, mobile phones, wearable device, etc.
LDs incorporating relaxed InGaN layers provided by the present disclosure can also be incorporated into various systems. LD packaging is similar to LED packaging as described herein, except that means are provided for managing the higher power densities in a LD device from a thermal perspective and means for optically accessing the laser facet is provided. LDs of multiple emission colors may be provided in separate packages or combined into a single package. LDs may be coupled to luminescent down-conversion materials to provide a desired emission spectrum. LDs are useful in applications wherein very high light density is required, such as in automotive forward lighting systems, or projection displays, which may include light modulation means such as rastering optics, micro-mirror devices, or LCD modulators.
Examples of lighting and display systems are shown in
The invention is further defined by the following aspects.
Aspect 1. A III-nitride semiconductor structure, comprising an InGaN region, wherein the InGaN region comprises a relaxed (0001) InGaN region; and the relaxed (0001) InGaN region has an in-plane a-lattice parameter characterized by a periodicity in at least one direction.
Aspect 2. The semiconductor structure of aspect 1, wherein the relaxed InGaN region is characterized by a c-plane growth orientation.
Aspect 3. The semiconductor structure of any one of aspects 1 to 2, wherein the relaxed InGaN region is characterized by a mean in-plane a-lattice parameter greater than 3.19 Å.
Aspect 4. The semiconductor structure of any one of aspects 1 to 3, wherein the relaxed InGaN region has a thickness less than 3 μm.
Aspect 5. The semiconductor structure of any one of aspects 1 to 4, wherein the relaxed InGaN region has a thickness from 20 nm to 1 μm.
Aspect 6. The semiconductor structure of any one of aspects 1 to 5, wherein the relaxed InGaN region has a defect density less than 5E9 cm2.
Aspect 7. The semiconductor structure of any one of aspects 1 to 6, wherein the relaxed InGaN region comprises an InGaN—GaN superlattice.
Aspect 8. The semiconductor structure of any one of aspects 1 to 7, further comprising: a plurality of mask regions underlying a first portion of the relaxed InGaN region; and a plurality of non-mask regions underlying a second portion of the relaxed InGaN region.
Aspect 9. The semiconductor structure of aspect 8, wherein each of the plurality of mask regions comprises a dielectric material.
Aspect 10. The semiconductor structure of aspect 9, wherein the dielectric material comprises silicon nitride, silicon oxide, or aluminum oxide.
Aspect 11. The semiconductor structure of any one of aspects 8 to 10, wherein each of plurality of mask regions has a thickness from 20 nm to 2 μm.
Aspect 12. The semiconductor structure of any one of aspects 8 to 10, wherein each of the plurality of mask regions has a thickness less than 2 μm.
Aspect 13. The semiconductor structure of any one of aspects 8 to 12, wherein a maximum in-plane dimension of each of the plurality of non-mask regions is less than 1 μm.
Aspect 14. The semiconductor structure of any one of aspects 8 to 13, further comprising a seed region underlying each of the plurality of mask regions.
Aspect 15. The semiconductor structure of aspect 14, wherein the seed region comprises GaN, MN, or AlGaN.
Aspect 16. The semiconductor structure of any one of aspects 14 to 15, wherein the seed region has a thickness from 20 nm to 2 μm.
Aspect 17. The semiconductor structure of any one of aspects 14 to 16, wherein the seed region has a thickness less than 2 μm.
Aspect 18. The semiconductor structure of any one of aspects 14 to 17, wherein, a seed region comprises a horizontal interface and a seed interface; the horizontal interface is substantially co-planar with the (0001) InGaN crystallographic plane; and\the seed interface comprises a planar seed portion that is not parallel to the horizontal interface.
Aspect 19. The semiconductor structure of aspect 18, wherein the planar seed portion comprises an a-plane, an m-plane, or a plane between an a-plane and an m-plane.
Aspect 20. The semiconductor structure of aspect 19, wherein, the horizontal interface is characterized by a c-plane orientation; and the planar seed portion is not co-planar with the horizontal interface.
Aspect 21. The semiconductor structure of any one of aspects 19 to 20, wherein the planar seed portion comprises a heterojunction.
Aspect 22. The semiconductor structure of aspect 21, wherein the heterojunction is a GaN—InGaN heterojunction.
Aspect 23. The semiconductor structure of aspect 22, wherein, the seed region comprises GaN; the planar seed portion comprises a GaN/InGaN heterojunction; and the GaN/InGaN heterojunction is substantially parallel a the GaN (1-100) crystallographic plane, a GaN (11-20) crystallographic plane, or a crystallographic plane between a GaN (1-100) and a GaN (11-20) crystallographic plane.
Aspect 24. The semiconductor structure of any one of aspects 8 to 23, wherein the plurality of non-mask regions comprises InGaN.
Aspect 25. The semiconductor structure of any one of aspects 8 to 24, wherein the plurality of non-mask regions is characterized by a pattern.
Aspect 26. The semiconductor structure of any one of aspects 8 to 25, wherein the plurality of non-mask regions is characterized by a non-mask region periodicity in at least one dimension.
Aspect 27. The semiconductor structure of aspect 26, wherein the periodicity of the in-plane a-lattice parameter of the relaxed InGaN region corresponds to the non-mask region periodicity.
Aspect 28. The semiconductor structure of any one of aspects 8 to 27, wherein the plurality of non-mask regions is characterized by an array of shapes.
Aspect 29. The semiconductor structure of aspect 28, wherein a shape comprises an edge that is oriented with respect to a crystallographic plane of InGaN.
Aspect 30. The semiconductor structure of aspect 29, wherein the edge is mis-oriented by +/−1° with respect to with respect to an InGaN a-plane or an InGaN m-plane.
Aspect 31. The semiconductor structure of any one of aspects 29 to 30, wherein the edge is oriented parallel to a (1-100) InGaN crystallographic plane.
Aspect 32. The semiconductor structure of any one of aspects 29 to 31, wherein the edge is oriented parallel to a (11-20) InGaN crystallographic plane.
Aspect 33. The semiconductor structure of any one of aspects 29 to 31, wherein the edge is oriented in a direction that is not parallel to a (1-100) InGaN crystallographic plane and is not parallel to a (11-20) InGaN crystallographic plane.
Aspect 34. The semiconductor structure of any one of aspects 8 to 33, further comprising a substrate underlying each of the plurality of non-mask regions and the each of the plurality of mask regions.
Aspect 35. The semiconductor structure of aspect 34, wherein the substrate comprises sapphire, silicon, silicon-carbide, gallium-nitride, silicon-on-insulator (SOI), or aluminum-nitride.
Aspect 36. The semiconductor structure of any one of aspects 8 to 35, further comprising: a substrate underlying each of the plurality of non-mask regions; and a cavity within the non-mask region and overlying a portion of the substrate.
Aspect 37. The semiconductor structure of any one of aspects 1 to 36, wherein the III-V semiconductor structure has an area defined by a width and a length; and the area is greater than 0.1 mm2.
Aspect 38. The semiconductor structure of aspect 37, wherein the periodicity is characterized by a period that is at least 10 times less than the width and/or at least 10 times less than the length.
Aspect 39. The semiconductor structure of any one of aspects 37 to 38, wherein a number of non-mask regions within the area is greater than 10.
Aspect 40. The semiconductor structure of any one of aspects 1 to 39, wherein, within a period associated with the periodicity, the in-plane a-lattice parameter varies between a minimum and maximum value around a mean in-plane a-lattice parameter of less than 1%.
Aspect 41. The semiconductor structure of any one of aspects 1 to 40, further comprising a plurality of seed regions underlying a first portion of the relaxed InGaN region, wherein, each of the plurality of seed regions comprise a plurality of planar seed portions; and each of the plurality of planar seed portions are not co-planar (0001) InGaN crystallographic plane.
Aspect 42. The semiconductor structure of aspect 41, wherein the planar seed portions form at least a portion of a pyramidal shape having a hexagonal base.
Aspect 43. The semiconductor structure of any one of aspects 41 to 42, wherein each of the plurality of planar seed portions is characterized by a (1-101) crystallographic plane.
Aspect 44. The semiconductor structure of any one of aspects 41 to 43, further comprising a plurality of mask regions underlying a second portion of the relaxed InGaN region, wherein each of the plurality of seed portions extends above the plurality of mask regions.
Aspect 45. The semiconductor structure of aspect 44, further comprising a seed layer underlying each of the plurality of mask regions and underlying each of the plurality of seed regions.
Aspect 46. The semiconductor structure of aspect 45, wherein the seed layer and each of the plurality of seed regions are contiguous.
Aspect 47. The semiconductor structure of aspect 46, further comprising a substrate underlying the seed layer.
Aspect 48. The semiconductor structure of any one of aspects 44 to 47, further comprising a substrate underlying each of the plurality of seed regions and underlying each of the plurality of mask regions.
Aspect 49. The semiconductor structure of any one of aspects 1 to 48, wherein in a plane parallel to the InGaN c-plane and through the relaxed InGaN region, the in-plane a-plane lattice parameter is greater than 3.19 Å.
Aspect 50. The semiconductor structure of any one of aspects 1 to 49, further comprising a plurality of non-mask regions underlying a portion of the relaxed InGaN region, wherein a periodicity of the lattice parameter of the relaxed InGaN region corresponds to a periodicity of the plurality of non-mask regions.
Aspect 51. The semiconductor structure of any one of aspects 1 to 50, further comprising a plurality of seed regions underlying a portion of the relaxed InGaN region, wherein, each of the plurality of seed regions is characterized by an in-plane a-lattice parameter a1; the relaxed InGaN region is characterized by an in-plane a-lattice parameter a2; and a2 is greater than a1.
Aspect 52. The semiconductor structure of any one of aspects 1 to 51, further comprising a plurality of seed regions underlying a portion of the relaxed InGaN region, wherein, the relaxed InGaN region and the plurality of the seed regions form a plurality of heterojunctions; and each of the plurality of heterojunctions is not parallel to the growth plane of the seed region and the relaxed InGaN region.
Aspect 53. The semiconductor structure of any one of aspects 1 to 52, further comprising a plurality of seed regions underlying a portion of the relaxed InGaN region, wherein, the relaxed InGaN region and the plurality of the seed regions form a plurality of heterojunctions; and each of the plurality of heterojunctions is perpendicular to the c-plane of the relaxed InGaN region.
Aspect 54. The semiconductor structure of any one of aspects 1 to 53, further comprising a plurality of seed regions underlying a portion of the relaxed InGaN region, wherein, the relaxed InGaN region and the plurality of the seed regions form a plurality of heterojunctions; and each of the plurality of heterojunctions is parallel to the InGaN a-plane, parallel to the InGaN m-plane, or at angle between the InGaN a-plane and the InGaN m-plane.
Aspect 55. The semiconductor structure of any one of aspects 1 to 54, further comprising a plurality of seed regions underlying a portion of the relaxed InGaN region, wherein, the plurality of seed regions is characterized by a periodicity in at least one direction; and the periodicity of the in-plane a-lattice parameter of the relaxed InGaN region corresponds to the periodicity of the plurality of seed regions.
Aspect 56. The semiconductor structure of aspect 55, wherein the periodicity of the in-plane a-lattice parameter of the relaxed InGaN region is the same as the periodicity of the plurality of seed regions.
Aspect 57. The semiconductor structure of any one of aspects 1 to 56, further comprising an n-doped semiconductor layer, an active semiconductor layer, and a p-doped semiconductor layer overlying the relaxed InGaN region.
Aspect 58. The semiconductor structure of any one of aspects 1 to 57, further comprising a plurality of semiconductor epitaxial layers overlying the relaxed InGaN region.
Aspect 59. A III-nitride semiconductor structure, comprising: an InGaN region, wherein the InGaN region comprises a relaxed (0001) InGaN region; a plurality of mask regions underlying a first portion of the relaxed InGaN region; a plurality of non-mask regions underlying a second portion of the relaxed InGaN region; and a seed region underlying each of the mask regions.
Aspect 60. The semiconductor structure of aspect 59, wherein, the seed regions comprise GaN; and the non-mask regions between the seed regions and underlying the second portion of the InGaN region comprise InGaN.
Aspect 61. The semiconductor structure of any one of aspects 59 to 60, wherein, in a plane parallel to the c-plane of the relaxed InGaN region and bisecting a seed region, an in-plane a-lattice parameter within the seed region is less than the in-plane a-lattice parameter between seed regions and underlying the second portion of the InGaN region.
Aspect 62. A semiconductor device comprising the III-V semiconductor structure of any one of aspects 1 to 61.
Aspect 63. The semiconductor device of aspect 62, wherein the semiconductor device comprises an optoelectronic device.
Aspect 64. The semiconductor device of aspect 62, wherein the semiconductor device comprises a light emitting diode or a laser diode.
Aspect 65. The semiconductor device of aspect 64, further comprising a peak emission wavelength.
Aspect 66. The semiconductor device of aspect 65, wherein the peak emission wavelength is between 440 nm and 460 nm, and the in-plane a-lattice parameter is between 3.196 Å and 3.214 Å.
Aspect 67. The semiconductor device of aspect 65, wherein the peak emission wavelength is between 520 nm and 540 nm, and the in-plane a-lattice parameter is between 3.235 Å and 3.253 Å.
Aspect 68. The semiconductor device of aspect 65, wherein the peak emission wavelength is between 580 nm and 600 nm, and the in-plane a-lattice parameter is between 3.260 Å and 3.282 Å.
Aspect 69. The semiconductor device of aspect 65, wherein the peak emission wavelength is between 620 and 640 nm, and the in-plane a-lattice parameter is between 3.282 and 3.296 Å.
Aspect 70. The semiconductor device of aspect 65, wherein the peak emission wavelength is between 690 and 710 nm, and the in-plane a-lattice parameter is between 3.303 Å and 3.324 Å.
Aspect 71. The semiconductor device of aspect 65, wherein the peak emission wavelength is between 840 nm and 870 nm, and the in-plane a-lattice parameter is between 3.346 Å and 3.367 Å.
Aspect 72. The semiconductor device of aspect 65, wherein the peak emission wavelength is between 940 nm and 980 nm, and the in-plane a-lattice parameter is between 3.374 Å and 3.392 Å.
Aspect 73. The semiconductor device of aspect 65, wherein the peak emission wavelength is between 1300 nm and 1350 nm, and the in-plane a-lattice parameter is between 3.435 Å and 3.456 Å.
Aspect 74. A lighting system comprising the semiconductor device of any one of aspects 62 to 73.
Aspect 75. A display system comprising the semiconductor device of any one of aspects 62 to 73.
Finally, it should be noted that there are alternative ways of implementing the embodiments disclosed herein. Accordingly, the present embodiments are to be considered as illustrative and not restrictive, and the claims are not to be limited to the details given herein but may be modified within the scope and equivalents thereof.
This application is a continuation of International Application No. PCT/US2020/061377, filed on Nov. 19, 2020, which claims priority to U.S. application Ser. No. 16/689,064, filed on Nov. 19, 2019, now issued as U.S. Pat. No. 10,847,625, each of which is incorporated by reference in its entirety.
| Number | Date | Country | |
|---|---|---|---|
| Parent | PCT/US2020/061377 | Nov 2020 | US |
| Child | 17746431 | US | |
| Parent | 16689064 | Nov 2019 | US |
| Child | PCT/US2020/061377 | US |
