Claims
- 1. An insulating barrier extending between a first conductive region and a second conductive region, the insulating barrier for tunnelling charge carriers from the first conductive region to the second conductive region, the insulating barrier comprising:
a first portion contacting the first region; and a second portion contacting the first portion and extending towards the second region, wherein the first portion is substantially thinner than the second portion, the first portion being constructed in a first dielectric and the second portion being constructed in a second dielectric different from the first dielectric, characterised in that the first dielectric has a lower dielectric constant than the second dielectric.
- 2. The insulating barrier according to claim 1, wherein the first and second dielectrics and the thickness of the first and second portions are chosen such that, upon applying a voltage suitable for tunnelling over the insulating barrier, the voltage drop over the first portion is higher than the voltage drop over the second portion.
- 3. The insulating barrier according to claim 2, wherein the insulating barrier is further provided tunnelling charge carriers from the second conductive region to the first conductive region, and
further comprising a third portion extending between the second portion and the second region, the third portion being substantially thinner than the second portion and being constructed in a third dielectric different from the second dielectric, the third dielectric having a lower dielectric constant than the second dielectric.
- 4. The insulating barrier according to claim 3, wherein the third portion has substantially the same thickness as the first portion and that the third dielectric is the same as the first dielectric.
- 5. The insulating barrier according to claim 4, wherein the first, second and third dielectrics are chosen such that, in absence of a voltage difference over the insulating barrier, the first, second and third portions have substantially the same potential energy barrier.
- 6. The insulating barrier according to claim 5, wherein the insulating barrier is constructed as a three-layered structure with the first and third portions being constructed in SiO2 and the second portion in Al2O3.
- 7. The insulating barrier according to claim 2, wherein the first and second dielectrics are chosen such that, in absence of a voltage difference over the insulating barrier, the first portion has a higher potential energy barrier than the second portion.
- 8. The insulating barrier according to claim 7, wherein the insulating barrier is constructed as a two-layered structure, with the first dielectric being either SiO2 or Si3N4 and the second dielectric being either HfO2 or ZrO2.
- 9. A memory device comprising the insulating barrier of claim 1.
- 10. A memory device comprising:
a semiconductor substrate having two heavily doped regions which are spaced by a channel region, a first insulating barrier on top of the channel region, a floating gate on top of the first insulating barrier, a second insulating barrier on top of the floating gate, and a control gate on top of the second insulating barrier, wherein the second insulating barrier is an insulating barrier according to claim 2.
- 11. The memory device of claim 10, wherein the second insulating barrier is an insulating barrier according to claim 3.
- 12. The memory device of claim 10, further comprising a program gate which is capacitively coupled to the floating gate,
wherein the first and second insulating barriers are both insulating barriers according to claim 7, the first portion of the first insulating barrier contacting the substrate and the first portion of the second insulating barrier contacting the floating gate.
- 13. The memory device of claim 10, further comprising a program gate which is capacitively coupled to the floating gate, and
wherein the first insulating barrier extends over a portion of the channel region and over a portion of the first heavily doped region, wherein the floating gate is on top of the first insulating barrier, wherein the second insulating barrier extends over the floating gate and over a portion of the channel region not covered by the first insulating barrier, and wherein the second insulating barrier is an insulating barrier according to claim 7, the first portion of the second insulating barrier contacting the floating gate.
- 14. The memory device of claim 10, further comprising a program gate which is capacitively coupled to the floating gate, and
wherein the two heavily doped regions comprise first and second heavily doped regions, wherein the first insulating barrier extends over a portion of the channel region and over a portion of the first heavily doped region, wherein the second insulating barrier extends over the floating gate and over a portion of the channel region not covered by the first insulating barrier, and wherein the first insulating barrier is an insulating barrier according to claim 7, the second portion of the first insulating barrier contacting the floating gate.
Priority Claims (1)
Number |
Date |
Country |
Kind |
01204106.7 |
Oct 2001 |
EP |
|
REFERENCE TO RELATED APPLICATIONS
[0001] This application claims priority benefits to U.S. provisional application Serial No. 60/287,192, filed on Apr. 27, 2001, entitled “Insulating Barrier.” This application also claims priority to European Patent Application EP 01204106.7 filed on Oct. 19, 2001. This application incorporates by reference U.S. provisional application Serial No. 60/287,192 in its entirety. This application also incorporates by reference European Patent Application EP 01204106.7 in its entirety.
Provisional Applications (1)
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Number |
Date |
Country |
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60287192 |
Apr 2001 |
US |