The present application claims priority from Japanese Patent Application JP2009-225903 filed on Sep. 30, 2009, the content of which is hereby incorporated by reference into this application.
The invention relates to a high-voltage insulation circuit board which is used in an electric power apparatus such as an electric power converter or the like such as power semiconductor device, inverter module, or the like and to a power semiconductor device or inverter module using such an insulation circuit board.
Hitherto, as an insulation circuit board for an electronic apparatus which is subjected to a severe temperature environment such as a vehicle-mounting environment or the like, a ceramic board having excellent heat radiation performance and heat resistance is a main stream. However, in association with a demand for low costs of the electronic apparatus, a shift to a resin board in which a high radiation insulation resin is used for an insulation layer is increasing year by year.
As shown in
The dielectric breakdown mentioned above will now be described by using
However, according to the Patent Literature 1, since the concave portion 7 is formed in the insulation layer 2, a pre-process is necessary and in the case of comparing with the forming method of the wiring pattern 3 in the related art, costs rise. Also, according to the Patent Literature 2, since it is necessary to work the shape of the end section of the wiring pattern 3 by the discharge, laser, or the like, costs rise similarly. Further, according to the Patent Literature 2, there are such many problems that since it can be applied only to a ceramic substrate, an applying range is limited, since a solder wettability due to an increase in substrate temperature at the time of fusing deteriorates, fine processing techniques such as a proper processing time and the like are necessary, and the like. On the other hand, it is an object of the invention to provide an insulation circuit board in which the electric field concentration at the end sections of the wiring pattern 3 is reduced, the partial discharging 4 is suppressed, and the reliability is high although the existing insulation circuit board and forming method of the wiring pattern 3 by the chemical etching are used. It is a further object of the invention to provide a power semiconductor device or inverter module having a high insulation reliability by using the insulation circuit board using the wiring pattern 3.
To accomplish the above objects, according to the invention, there is provided an insulation circuit board comprising: a metal base substrate; and wiring patterns which are formed onto at least one of surfaces of the metal base substrate through an insulation layer, characterized in that between two adjacent wiring patterns in which an electric potential difference exists among the wiring patterns, at least one or more wiring patterns or conductors which are in contact with the insulation layer and have an electric potential in a range of the electric potential difference between the adjacent wiring patterns are arranged.
Further, according to the invention, the insulation circuit board is characterized in that the insulation layer which is in contact with the metal base substrate and the wiring patterns is one of a resin mainly consisting of an epoxy resin, a resin mainly consisting of a polyimide resin, a resin mainly consisting of a silicone resin, a resin mainly consisting of an acrylic resin, and a resin mainly consisting of an urethane resin or a resin consisting of a denatured material or mixture of those resins.
Further, according to the invention, the insulation circuit board is characterized in that an inorganic filler which is dispersed into the insulation layer which is in contact with the metal base substrate and the wiring patterns is one of Al2O3 (alumina), SiO2 (silica), AlN (aluminum nitride), BN (boron nitride), ZnO (zinc oxide), SiC (silicon carbide), Si3N4 (silicon nitride), and MgO (magnesium oxide), a filler adapted to improve heat radiation performance and insulation performance in a manner similar to those compounds, or a mixture of two or more kinds of those compounds.
Further, according to the invention, the insulation circuit board is characterized in that the insulation layer which is in contact with the metal base substrate and the wiring patterns is one of ceramic materials each mainly consisting of Al2O3 (alumina), ZrO2 (zirconia), AlN (aluminum nitride), or BN (boron nitride), a ceramic material which has characteristics similar to those of those ceramic materials, whose fundamental component consists of a metal oxide, and which is burned and solidified by a heat treatment of a high temperature, or an inorganic material consisting of a denatured material or mixture obtained by mixing a glass component into the ceramic material.
Further, according to the invention, the insulation circuit board is characterized in that in order to provide the electric potential in the range of the potential difference between the adjacent wiring patterns, a resistor is arranged between the two adjacent wiring patterns where the electric potential difference exists.
Further, according to the invention, the insulation circuit board is characterized in that the electric potential in the range of the potential difference between the adjacent wiring patterns is provided from a circuit for forming the electric potential by a portion other than a portion on the insulation circuit board.
Further, it is an object of the invention to provide a power semiconductor device or inverter module characterized in that the foregoing insulation circuit board is used, circuit parts including semiconductor elements connected to the wiring patterns are mounted, and the wiring patterns are arranged.
To accomplish the above object, according to the invention, there is provided a power semiconductor device comprising: a metal base substrate; wiring patterns which are formed onto at least one of surfaces of the metal base substrate through an insulation layer; and semiconductor elements connected to the wiring patterns, characterized in that between two adjacent wiring patterns in which an electric potential difference exists among the wiring patterns, at least one or more wiring patterns or conductors which are in contact with the insulation layer and have an electric potential in a range of the electric potential difference between the adjacent wiring patterns are arranged.
Further, according to the invention, the power semiconductor device is characterized in that the two adjacent wiring patterns are an input potential wiring pattern and a ground potential wiring pattern.
Further, according to the invention, the power semiconductor device is characterized in that the two adjacent wiring patterns are output wiring patterns of a three-phase alternating current connected to the semiconductor elements.
Further, it is an object of the invention to provide an inverter module having the foregoing power semiconductor device.
According to the invention, while using the conventional insulation circuit board construction and wiring pattern forming method, the electric field concentration at the end sections of the wiring pattern to which a high voltage is applied is reduced and partial-discharge-resistant characteristics are improved. Therefore, even in high-density mounted wirings in which a distance between the wiring patterns is small, the insulation circuit board having the high insulation reliability can be realized by low costs. Providing of the power semiconductor device or inverter module using the insulation circuit board and having the high insulation reliability can be realized.
Other objects, features, and advantages of the present invention will be apparent from the following description of the embodiments of the invention with reference to the accompanying drawings.
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Embodiments of the invention will be described hereinbelow by using the drawings.
The drawings which are used in the following description are schematic diagrams and it should be noted that a relation between a thickness and plane dimensions, ratios among the thicknesses of respective layers, and the like differ from those of an actual circuit board. Therefore, specific thicknesses and dimensions should be judged in consideration of the following description. Naturally, portions whose dimensional relations and ratios differ are also included in the respective drawings.
Each of
The embodiment of
The potential difference between the adjacent wiring patterns 31 and 33 in the embodiment denotes a potential difference at a certain time point in the case where an electric potential which is applied to the wiring pattern 3 time-sequentially changes and the potential difference between the adjacent wiring patterns 31 and 33 changes. Therefore, even if the potential difference between the adjacent wiring patterns 31 and 33 is not high at a certain time point, in the case where the potential difference between the adjacent wiring patterns 31 and 33 is large at a different time point, such a case is incorporated in the adjacent wiring patterns 31 and 33.
In the invention, in the case where one or more wiring patterns 32 or conductors having an electric potential in a range of the potential difference between the adjacent wiring patterns 31 and 33 showing the high potential difference is/are arranged, it is desirable that a potential difference between the wiring pattern 31 on the high potential side and the wiring pattern 32 and a potential difference between the wiring pattern 32 and the wiring pattern 33 on the low potential side are equal to 350V or less. It is a value which is obtained from a Paschen's law. According to the Paschen's law, it is mentioned that a lowest value of the potential difference at the time of occurrence of a spark discharge in the air at an ordinary temperature in the case of presuming a parallel electric field is equal to about 350V. Therefore, this is because when a space other than the insulation layer 2 which is in contact with the wiring patterns 31, 32, and 33 was filled with a filler such as a sealing resin or the like, even if a void or the like occurred, so long as the potential difference between the wiring patterns 3 is equal to 350V or less, no discharge occurs in the void.
In the invention, if two or more wiring patterns 32 or conductors are arranged, it is desirable that a potential difference between the adjacent wiring patterns 32 or conductors is equal to 350V or less. Thus, this is because from the Paschen's law mentioned above, when the space other than the insulation layer 2 which is in contact with the wiring patterns 32 or conductors was filled with the filler such as a sealing resin or the like, even if the void or the like occurred, so long as the potential difference between the wiring patterns 32 or conductors is equal to 350V or less, no discharge occurs in the void.
Thus, according to the embodiment, since the potential difference between the adjacent wiring patterns 3 decreases, when the voltage is applied, the electric field concentration at the end sections of the wiring pattern 31 on the high potential side is lightened, thereby raising a partial discharging voltage. The partial-discharge-resistant performance of the insulation circuit board in
The wiring pattern 32 which is newly arranged has a material and a shape similar to those of the adjacent wiring patterns 31 and 33. Therefore, the embodiment according to the invention can be easily realized by the conventional insulation circuit construction and forming method of the wiring patterns 3. The insulation performance of the insulation circuit board can be improved by low costs.
As shown in
Further, in order to realize the embodiment of the invention shown in
In the case where the density of the wiring patterns 3 on the insulation circuit board is high and an element, for example, the chip resistor or the like to form the potential difference between the wiring patterns 31 and 33 showing the high potential difference cannot be mounted to the wiring patterns 3 on the insulation circuit board, it is sufficient to form an electric potential for the wiring pattern 32 by a portion other than the portion on the insulation circuit board. For this purpose, for example, a bus bar wiring for supplying a power source to the insulation circuit board, a terminal portion of a capacitor for the power source, or the like corresponds to such a portion. It is sufficient to supply an input voltage including the intermediate electric potential formed there to the insulation circuit board.
Thus, the intermediate electric potential can be easily obtained even in the insulation circuit board on which the wiring patterns are formed at a high density and the elements are mounted without a gap.
In an outline of the inverter circuit of the motor control system, generally, as shown in a circuit diagram of
Among the wiring patterns 3 shown in
According to the embodiment, even in the power semiconductor device or inverter module using the high-density mounting wirings in which the distance between the wiring patterns is small, the power semiconductor device or inverter module having the high insulation reliability can be realized at low costs.
In order to verify an effect of the invention hereinbelow, analysis models are formed for the embodiments of the invention and comparative examples and local electric fields at the end sections of the high-potential wiring pattern 31 are derived by simulation.
The epoxy resin (dielectric constant: 4) insulation layer 2 having a thickness of 2.0 mmt is formed on the metal base substrate 1 having a thickness of 2.0 mmt and an electrolytic copper foil having a thickness of 0.1 mmt is further adhered onto the insulation layer 2. After that, the wiring patterns 31 and 33 formed by the chemical etching and the wiring pattern 32 according to the invention are formed onto the copper foil. An inclination angle of the side surface of each of the wiring patterns 31, 32, and 33 is equal to 60°. The wiring patterns 31 and 33 are away from each other by the distance R1 between the wiring patterns. Further, the wiring pattern 32 is arranged at the position of the distance R2 between the wiring patterns corresponding to the equal distance from each of the wiring patterns 31 and 33. Electric potentials of the wiring patterns 31, 32, and 33 are equal to 900V, 450V, and 0V, respectively.
The epoxy resin (dielectric constant: 4) insulation layer 2 having a thickness of 0.2 mmt is formed on the metal base substrate 1 having a thickness of 2.0 mmt and an electrolytic copper foil having a thickness of 0.1 mmt is further adhered onto the insulation layer 2. After that, the wiring patterns 31 and 33 formed by the chemical etching and the wiring pattern 32 according to the invention are formed onto the copper foil. An inclination angle of the side surface of each of the wiring patterns 31, 32, and 33 is equal to 60°. The wiring patterns 31 and 33 are away from each other by the distance R1 between the wiring patterns. Further, the wiring pattern 32 is arranged at the position of the distance R2 between the wiring patterns corresponding to the equal distance from each of the wiring patterns 31 and 33. Electric potentials of the wiring patterns 31, 32, and 33 are equal to 900V, 450V, and 0V, respectively.
The epoxy resin (dielectric constant: 4) insulation layer 2 having a thickness of 0.2 mmt is formed on the metal base substrate 1 having a thickness of 2.0 mmt and an electrolytic copper foil having a thickness of 0.1 mmt is further adhered onto the insulation layer 2. After that, the wiring patterns 31 and 33 formed by the chemical etching and the wiring patterns 32A and 32B according to the invention are formed onto the copper foil. An inclination angle of the side surface of each of the wiring patterns 31, 33, 32A, and 32B is equal to 60°. The wiring patterns 31 and 33 are away from each other by the distance R1 between the wiring patterns. Further, the wiring patterns 32A and 32B are arranged at the positions of the distance R2 between the wiring patterns corresponding to the equal distance from each of the wiring patterns 31 and 33. Electric potentials of the wiring patterns 31, 32A, 32B, and 33 are equal to 900V, 600V, 300V, and 0V, respectively.
The epoxy resin (dielectric constant: 4) insulation layer 2 having a thickness of 0.2 mmt is formed on the metal base substrate 1 having a thickness of 2.0 mmt and an electrolytic copper foil having a thickness of 0.1 mmt is further adhered onto the insulation layer 2. After that, the wiring patterns 31 and 33 formed by the chemical etching and the wiring patterns 32B and 32A according to the invention are formed onto the copper foil. An inclination angle of the side surface of each of the wiring patterns 31, 33, 32B, and 32A is equal to 60°. The wiring patterns 31 and 33 are away from each other by the distance R1 between the wiring patterns. Further, the wiring patterns 32B and 32A are arranged at the positions of the distance R2 between the wiring patterns corresponding to the equal distance from each of the wiring patterns 31 and 33. Electric potentials of the wiring patterns 31, 32A, 32B and 33 are equal to 900V, 600V, 300V, and 0V, respectively.
The epoxy resin (dielectric constant: 4) insulation layer 2 having a thickness of 2.0 mmt is formed on the metal base substrate 1 having a thickness of 2.0 mmt and an electrolytic copper foil having a thickness of 0.1 mmt is further adhered onto the insulation layer 2. After that, the wiring patterns 31 and 33 formed by the chemical etching are formed onto the copper foil. An inclination angle of the side surface of each of the wiring patterns 31 and 33 is equal to 60°. The wiring patterns 31 and 33 are away from each other by the distance R1 between the wiring patterns. Further, electric potentials of the wiring patterns 31 and 33 are equal to 900V and 0V, respectively.
The epoxy resin (dielectric constant: 4) insulation layer 2 having a thickness of 0.2 mmt is formed on the metal base substrate 1 having a thickness of 2.0 mmt and an electrolytic copper foil having a thickness of 0.1 mmt is further adhered onto the insulation layer 2. After that, the wiring patterns 31 and 33 formed by the chemical etching are formed onto the copper foil. An inclination angle of the side surface of each of the wiring patterns 31 and 33 is equal to 60°. The wiring patterns 31 and 33 are away from each other by the distance R1 between the wiring patterns. Further, electric potentials of the wiring patterns 31 and 33 are equal to 900V and 0V, respectively.
To the analysis model of the embodiment shown in
TABLE 1 shows local electric field ratios of the end sections of the wiring pattern 31 on the high potential side in the embodiment shown in
As shown in TABLE 1, the local electric fields at the end sections of the wiring pattern 31 on the high potential side in the embodiment shown in
To the analysis models of the embodiments shown in
TABLE 2 shows local electric field ratios of the end sections of the wiring pattern 31 on the high potential side in Comparative Example 2 and the embodiments of
As shown in TABLE 2, in Comparative Example 2, the local electric fields at the end sections of the wiring pattern 31 on the high potential side is not changed even if the distance RI between the wiring patterns differs. This means that the local electric fields at the end sections of the wiring pattern 31 on the high potential side is strongly influenced by the metal base substrate 1 which is closely arranged and an influence by the wiring pattern 33 on the low potential side is small. On the other hand, in the embodiments of
To evaluate the influence which is exerted on the reducing effect of the local electric fields at the end sections of the wiring pattern 31 on the high potential side according to the invention by the distance R2 between the wiring patterns, an analysis in the case where the distance R2 between the wiring patterns in the embodiments of
TABLE 3 shows local electric field ratios of the end sections of the wiring pattern 31 on the high potential side in the embodiments of
As shown in TABLE 3, in the embodiments of
Although the embodiments have been mentioned above, the invention is not limited to them but it will be obvious to a person with ordinary skill in the art that various changes and modifications are possible within the spirit of the invention and the scope of annexed claims.
Number | Date | Country | Kind |
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2009-225903 | Sep 2009 | JP | national |
Filing Document | Filing Date | Country | Kind | 371c Date |
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PCT/JP2010/052847 | 2/24/2010 | WO | 00 | 2/2/2012 |