Patent Application
20050212105
An integrated circuit (IC) die may include electrical devices that are integrated with a semiconductor substrate. The IC die may also include conductive paths that electrically couple the electrical devices to one another and to external connections. The die may include several layers of conductive paths, with each layer separated from adjacent layers by an inter-layer dielectric (ILD). The ILD may comprise material having an extremely low dielectric constant (k) in order to minimize capacitance coupling and crosstalk between the conductive paths.
Low-k ILD materials often exhibit a coefficient of thermal expansion (CTE) that differs significantly from other elements to which they are coupled, such as the other elements of the IC die and elements of an IC substrate to which the IC die is coupled. Moreover, low-k ILD materials are often brittle. These two characteristics may cause low-k ILD materials to crack during IC die and/or IC package fabrication.
Underfill material portion 10 defines openings 15. Openings 15 may be configured to pass electrical interconnects through underfill material portion 10. The electrical interconnects may in turn couple an IC die to an IC substrate. Such an arrangement might reduce ILD mechanical failures and/or provide high fabrication throughput.
An IC die may be located on one side of openings 15 and an IC substrate to which the IC die is coupled may be located on an opposite side of openings 15. With reference to
Underfill material portion 20 may define openings 25 that function similarly to openings 15 of underfill material portion 10. Openings 25 may therefore pass electrical interconnects through underfill material portion 20 for coupling an IC die to an IC substrate. The IC die and/or IC substrate may be identical to the IC die and/or IC substrate that is coupled by the electrical interconnects passed by openings 15. The embodiments described below and shown in
Underfill material portion 10 is coupled to underfill material portion 20 via coupling 30. Coupling 30 may comprise a physical connection that provides efficient separation of portion 10 from portion 20, or may simply comprise a solid region of material. According to some embodiments, a material located between portion 10 and portion 20 is different from the material of which portion 10 and portion 20 is composed.
In some embodiments, tape 1 includes additional underfill material portions coupled to underfill material portion 10 and/or to underfill material portion 20. For example, a portion of underfill material may be coupled to end 27 of portion 20 in the manner that portion 20 is coupled to portion 10. Accordingly, tape 1 may comprise a series of connected portions of underfill material that may be dispensed from a roll or other suitable dispensing system.
Side 42 of IC die 40 includes electrical contacts 44. IC die 40 may comprise a flip chip arrangement in which electrical devices that are integrated therein reside between a substrate of IC die 40 and electrical contacts 44. In some embodiments, the substrate resides between the electrical devices and electrical contacts 44.
Electrical contacts 44 may comprise copper or lead-based contacts fabricated upon IC die 40. Electrical contacts 44 may comprise Controlled Collapse Chip Connect (C4) solder bumps. In this regard, conductive contacts 44 may be recessed under, flush with, or extending above first side 42 of IC die 40. Electrical contacts 44 may be electrically coupled to the electrical devices that are integrated into IC die 40.
First side 52 of substrate 50 includes electrical contacts 54. Electrical contacts 54 may comprise C4 solder bumps or plated copper contacts. Electrical contacts 54 may be recessed under, flush with, or extending above first side 52 of substrate. Although the embodiments of
Initially, no-flow underfill material is dispensed on a carrier at 82. No-flow underfill material may be dispensed according to any currently- or hereafter-known system, including a linear pump and a positive rotary displacement pump. The dispensed no-flow underfill material may be uncured, partially-cured or fully cured according to various embodiments. Partially- or fully-cured material may be dispensed in a laminate, sheet and/or tape form.
The underfill material is pressed against a template at 84 to create openings in the underfill material.
Projections 110 may be hollow so as to collect portions of underfill material 10 that are “punched-out” during 84. Underfill material 10 may be partially cured prior to 84 to enable clean removal of material from the areas in which openings are to be created. According to some embodiments, underfill material 10 is heated just prior to 84 to establish a desired degree of curing.
The portion of underfill material is attached to an IC substrate at 86. The IC substrate may be precleaned prior to 86. According to some embodiments, the portion of underfill material is laminated onto the IC substrate. The portion of underfill material and the IC substrate may again be cleaned after 86.
An IC die may be attached to the system of
Such a system may then be heated in order to form integral electrical connections between the IC die and the IC substrate, and/or to fully cure portion of underfill material 10. After curing, portion of underfill material 10 may form an inert protective polymer. Underfill material portion 10 may also include fluxing additives to deoxidize the metal surfaces of the electrical contacts of the IC die and of electrical interconnects 70. In some embodiments, flux is also or alternatively placed on the metal surfaces prior to heating.
IC substrate 50 of system 60 may comprise multiple layers of conductive traces that are separated by layers of dielectric material and electrically coupled by vias formed within the dielectric material. Such traces and vias may electrically couple through-hole pins 210 to electrical contacts 54. Accordingly, pins 210 may carry signals such as power and I/O signals between IC die 40 and external devices. Pins 210 may be mounted directly on motherboard 230 or onto a socket (not shown) that is in turn mounted directly to motherboard 230. Motherboard 230 may comprise a memory bus (not shown) that is electrically coupled to pins 210 and to memory 220. Motherboard 230 may therefore electrically couple memory 220 to IC die 40. Memory 220 may comprise any type of memory for storing data, such as a Single Data Rate Random Access Memory, a Double Data Rate Random Access Memory, or a Programmable Read Only Memory.
The several embodiments described herein are solely for the purpose of illustration. The various features described herein need not all be used together, and any one or more of those features may be incorporated in a single embodiment. Some embodiments may include any currently or hereafter-known versions of the elements described herein. Therefore, persons skilled in the art will recognize from this description that other embodiments may be practiced with various modifications and alterations.
