The present application contains subject matter related to concurrently filed U.S. patent application by Seng Guan Chow and Heap Hoe Kuan entitled “Multichip Package System” which is identified by Ser. No. 11/326,211. The related application is assigned to STATS ChipPAC Ltd. and the subject matter thereof is incorporated herein by reference thereto.
The present application contains subject matter also related to concurrently filed U.S. patent application by Seng Guan Chow and Heap Hoe Kuan entitled “Image Sensor Package System” which is identified by Ser. No. 11/326,206. The related application is assigned to STATS ChipPAC Ltd. and the subject matter thereof is incorporated herein by reference thereto.
The present application contains subject matter also related to concurrently filed U.S. patent application by Il Kwon Shim, Byung Joon Han, Kambhampati Ramakrishna, and Seng Guan Chow entitled “Encapsulant Cavity Integrated Circuit Package System” which is identified by Ser. No. 11/306,628. The related application is assigned to STATS ChipPAC Ltd. and the subject matter thereof is incorporated herein by reference thereto.
The present invention relates generally to integrated circuit package systems, and more particularly to an integrated circuit package system including stacked die.
In the electronics industry, as products such as cell phones and camcorders become smaller and smaller, increased miniaturization of integrated circuit (IC) packages has become more and more critical. At the same time, higher performance and lower cost have become essential for new products.
Usually, many individual integrated circuit devices are constructed on the same wafer and groups of integrated circuit devices are separated into individual integrated circuit die.
One approach to putting more integrated circuit dies in a single package involves stacking the dies with space between the dies for wire bonding. The space is achieved by means of a thick layer of organic adhesive or in combination with inorganic spacers of material such as silicon (Si), ceramic, or metal. Unfortunately, the stacking adversely affects the performance of the package because of decreased thermal performance due to the inability to remove heat through the organic adhesive and/or inorganic spacers. As the number of dies in the stack increases, thermal resistance increases at a faster rate. Further, such stacked dies have a high manufacturing cost.
Generally, semiconductor packages are classified into a variety of types in accordance with their structures. In particular, semiconductor packages are classified into an in-line type and a surface mount type in accordance with their mounting structures. Examples of in-line type semiconductor packages include a dual in-line package (DIP) and a pin grid array (PGA) package. Examples of surface mount type semiconductor packages include quad flat package (QFP) and a ball grid array (BGA) package.
Recently, the use of surface mount type semiconductor packages has increased, as compared to in-line type semiconductor packages, in order to obtain an increased element mounting density of a printed circuit board. A conventional semiconductor package has a size considerably larger than that of the semiconductor chip used. For this reason, this semiconductor package cannot meet the recent demand for a light, thin, simple, miniature structure. As a result, it is hard for the conventional semiconductor package to meet the demand for a highly integrated miniature structure.
Furthermore, the fabrication method used to fabricate the conventional semiconductor package involves a relatively large number of processes. For this reason, a need therefore exists for reducing the costs through use of simplified processes. In view of the ever-increasing need to save costs and improve efficiencies, it is more and more critical that answers be found to these problems.
The present invention provides an integrated circuit package system including providing a wafer with bond pads formed on the wafer. A solder bump is deposited on one or more bond pads. The bond pads and the solder bump are embedded within a mold compound formed on the wafer. A groove is formed in the mold compound to expose a portion of the solder bump. The wafer is singulated into individual die structures at the groove.
Certain embodiments of the invention have other aspects in addition to or in place of those mentioned or obvious from the above. The aspects will become apparent to those skilled in the art from a reading of the following detailed description when taken with reference to the accompanying drawings.
In the following description, numerous specific details are given to provide a thorough understanding of the invention. However, it will be apparent that the invention may be practiced without these specific details. In order to avoid obscuring the present invention, some well-known circuits, system configurations, and process steps are not disclosed in detail.
Likewise, the drawings showing embodiments of the device are semi-diagrammatic and not to scale and, particularly, some of the dimensions are for the clarity of presentation and are shown greatly exaggerated in the drawing FIGs. Generally, the device can be operated in any orientation. The same numbers are used in all the drawing FIGs. to relate to the same elements.
The term “horizontal” as used herein is defined as a plane parallel to the conventional plane or surface of the wafer, regardless of its orientation. The term “vertical” refers to a direction perpendicular to the horizontal as just defined. Terms, such as “on”, “above”, “below”, “bottom”, “top”, “side” (as in “sidewall”), “higher”, “lower”, “upper”, “over”, and “under”, are defined with respect to the horizontal plane.
The term “processing” as used herein includes deposition of material or photoresist, patterning, exposure, development, etching, cleaning, and/or removal of the material or photoresist as required in forming a described structure.
Referring now to
The first semiconductor structure 110 includes a die 114 having a mold compound 116. The die 114 has bond pads 118 electrically connected to the integrated circuits (not shown) within the die 114. The mold compound 116 includes solder bumps 120 bonded to the bond pads 118, and a recess 121 formed into the edges of the mold compound 116.
The recess 121 partially expose the solder bumps 120. Electrical connectors, including wire bonds 122 and bond wires 124, couple the solder bumps 120 to the printed circuit board 102. The height of the recess 121 is tall enough to provide a clearance for the electrical connectors disposed underneath the second semiconductor structure 112. The wire bonds and a portion of the bond wires are located within the recess 121. The combined height of the mold compound 116 and the die 114 is greater than the height of the electrical connectors.
The second semiconductor structure 112 includes a die 126 having a mold compound 128. A bottom surface of the die 126 is coupled to a top surface of the mold compound 116 of the first semiconductor structure 110. The die 126 has bond pads 130 electrically connected to the integrated circuits (not shown) within the die 126. The mold compound 128 includes solder bumps 132 bonded to the bond pads 130, and a recess 133 formed into the edges of the mold compound 128. The recess 133 partially exposes the solder bumps 132. Electrical connectors, including wire bonds 134 and bond wires 136, couple the solder bumps 132 to the printed circuit board 102.
The recesses 121 and 133 can be on two sides of the first and second semiconductor structures 110 and 112 or on all four sides for quad-packages. The first and second semiconductor structures 110 and 112 can be subsequently encapsulated in an encapsulant 138 to protect the bond wires 124 and 136 and to form the integrated circuit package system 100 with a low profile.
Referring now to
The recesses 121 and 133 can be on two sides of the first and second semiconductor structures 110 and 112 or on all four sides for quad-packages. The first and second semiconductor structures 110 and 112 can be subsequently encapsulated to protect the bond wires 124 and 136 and to form the integrated circuit package system 200 with a low profile.
Referring now to
Referring now to
Referring now to
The planarization permits the dies 124 and 126 to be extremely thin but partially supported for strength by the mold compounds 116 and 128 so they may be safely handled. This extreme thinness also helps reduce the package profile. Furthermore, the planarization allows for better accuracy for the following sawing step.
Referring now to
The groove 502 reduces the thickness of the mold compound 304, which must be sawn, while the mold compound 304 helps prevent defects during the dicing operation.
Referring now to
In greater detail, an integrated circuit package system including stacked die, according to an embodiment of the present invention, is performed as follows:
It has been discovered that the present invention thus has numerous aspects.
An aspect of the present invention is that it valuably supports and services the historical trend of reducing costs, simplifying systems, and increasing performance.
These and other valuable aspects of the present invention consequently further the state of the technology to at least the next level.
The resulting processes and configurations are straightforward, cost-effective, uncomplicated, highly versatile and effective, can be implemented by adapting known technologies, and are thus readily suited for efficiently and economically manufacturing large die IC packaged devices.
While the invention has been described in conjunction with a specific best mode, it is to be understood that many alternatives, modifications, and variations will be apparent to those skilled in the art in light of the aforegoing description. Accordingly, it is intended to embrace all such alternatives, modifications, and variations that fall within the scope of the included claims. All matters hithertofore set forth herein or shown in the accompanying drawings are to be interpreted in an illustrative and non-limiting sense.
Number | Name | Date | Kind |
---|---|---|---|
5607227 | Yasumoto et al. | Mar 1997 | A |
5977640 | Bertin et al. | Nov 1999 | A |
6083811 | Riding et al. | Jul 2000 | A |
6121682 | Kim | Sep 2000 | A |
6130448 | Bauer et al. | Oct 2000 | A |
6143588 | Glenn | Nov 2000 | A |
6144507 | Hashimoto | Nov 2000 | A |
6204562 | Ho et al. | Mar 2001 | B1 |
6225699 | Ference et al. | May 2001 | B1 |
6266197 | Glenn et al. | Jul 2001 | B1 |
6294406 | Bertin et al. | Sep 2001 | B1 |
6297131 | Yamada et al. | Oct 2001 | B1 |
6369454 | Chung | Apr 2002 | B1 |
6396116 | Kelly et al. | May 2002 | B1 |
6407381 | Glenn et al. | Jun 2002 | B1 |
6420244 | Lee | Jul 2002 | B2 |
6455353 | Lin | Sep 2002 | B2 |
6534419 | Ong | Mar 2003 | B1 |
6707140 | Nguyen et al. | Mar 2004 | B1 |
6828665 | Pu et al. | Dec 2004 | B2 |
6881611 | Fukasawa et al. | Apr 2005 | B1 |
6900079 | Kinsman et al. | May 2005 | B2 |
6900528 | Mess et al. | May 2005 | B2 |
6900549 | Brooks | May 2005 | B2 |
6906415 | Jiang et al. | Jun 2005 | B2 |
6906416 | Karnezos | Jun 2005 | B2 |
6930378 | St. Amand et al. | Aug 2005 | B1 |
6930396 | Kurita et al. | Aug 2005 | B2 |
6933598 | Karnezos | Aug 2005 | B2 |
6951982 | Chye et al. | Oct 2005 | B2 |
6972481 | Karnezos | Dec 2005 | B2 |
7034387 | Karnezos | Apr 2006 | B2 |
7034388 | Yang et al. | Apr 2006 | B2 |
7045887 | Karnezos | May 2006 | B2 |
7049691 | Karnezos | May 2006 | B2 |
7053476 | Karnezos | May 2006 | B2 |
7053477 | Karnezos et al. | May 2006 | B2 |
7057269 | Karnezos | Jun 2006 | B2 |
7061088 | Karnezos | Jun 2006 | B2 |
7064426 | Karnezos | Jun 2006 | B2 |
7071568 | St. Amand et al. | Jul 2006 | B1 |
7081678 | Liu | Jul 2006 | B2 |
7084500 | Swnson et al. | Aug 2006 | B2 |
7090482 | Tsukahara et al. | Aug 2006 | B2 |
7093358 | Akram et al. | Aug 2006 | B2 |
7101731 | Karnezos | Sep 2006 | B2 |
7109574 | Chiu et al. | Sep 2006 | B2 |
7115990 | Kinsman | Oct 2006 | B2 |
7119427 | Kim | Oct 2006 | B2 |
7122906 | Doan | Oct 2006 | B2 |
7176506 | Beroz et al. | Feb 2007 | B2 |
7183191 | Kinsman et al. | Feb 2007 | B2 |
7218005 | Tago | May 2007 | B2 |
7221059 | Farnworth et al. | May 2007 | B2 |
7298045 | Fujitani et al. | Nov 2007 | B2 |
7335994 | Klein et al. | Feb 2008 | B2 |
20020024124 | Hashimoto | Feb 2002 | A1 |
20020096755 | Fukui et al. | Jul 2002 | A1 |
20020100955 | Potter et al. | Aug 2002 | A1 |
20020130404 | Ushijima et al. | Sep 2002 | A1 |
20030008510 | Grigg et al. | Jan 2003 | A1 |
20030113952 | Sambasivam et al. | Jun 2003 | A1 |
20030153134 | Kawata et al. | Aug 2003 | A1 |
20040016939 | Akiba et al. | Jan 2004 | A1 |
20040061213 | Kazemos | Apr 2004 | A1 |
20040119153 | Kazemos | Jun 2004 | A1 |
20040124540 | Chen et al. | Jul 2004 | A1 |
20040166605 | Kuratomi et al. | Aug 2004 | A1 |
20040201087 | Lee | Oct 2004 | A1 |
20040212096 | Wang | Oct 2004 | A1 |
20050051882 | Kwon et al. | Mar 2005 | A1 |
20050075053 | Jung | Apr 2005 | A1 |
20060043556 | Su et al. | Mar 2006 | A1 |
Number | Date | Country | |
---|---|---|---|
20070158833 A1 | Jul 2007 | US |