Integrated circuit (IC) chips are usually mounted on IC packages. Different types of IC packages cater to different types of applications and requirements. With the increase in processing power, heat dissipation has become one of the core issues in IC packaging. The heat generated by the IC chip in a package affects the overall performance and reliability of the device. Heat dissipation is thus an important aspect in IC packaging because unwanted heat in a circuit needs to be dissipated to prevent an excessive rise in temperature that could possibly affect the performance of the circuit.
The thermal resistance of an IC package is one measure of the ability of the IC package to transfer heat generated by the IC chip out of the IC package. An IC package with a high thermal resistance has a low thermal performance because of its inefficiency in transferring heat generated by its IC chip. Therefore, packages that have a high thermal resistance are unsuitable for high power applications, e.g., circuitry that are operating above 3 watts.
The thermal resistance in an IC package depends very much on the materials used in that IC package. For example, in a conventional wire-bond ball grid array (BGA), the molding compound used may have a low thermal conductivity and would thus be a poor heat conductor. As such, a conventional wire-bond BGA package may only be suitable for low power applications. An embedded heat slug may be used to improve the thermal conductivity of an IC package. However, the use of a heat slug limits the size of the die as it takes up a substantial substrate area.
Therefore, it is desirable to reduce the thermal resistance of an IC package to improve its thermal performance. It is also desirable to have a cost-effective method to reduce the thermal resistance without limiting the size of the die that can be mounted on the IC package. It is within this context that the invention arises.
Embodiments of the present invention include apparatuses and a method for creating an IC package with a heat conductor.
It should be appreciated that the present invention can be implemented in numerous ways, such as a process, an apparatus, a system, or a device. Several inventive embodiments of the present invention are described below.
In one embodiment, an IC package is disclosed. The IC package includes an IC disposed on a package substrate. A molding compound is injected onto the surface of the package substrate. The injected molding compound surrounds the IC and covers a perimeter area of the top surface of the IC. A heat conductor is disposed on the top surface of the IC such that the heat conductor is surrounded by the molding compound. In one embodiment, the heat conductor is shaped such that the heat conductor substantially fills the hole created by the molding compound.
In another embodiment in accordance with the present invention, a method of packaging an IC is disclosed. The method includes placing an IC onto a packaging substrate. Molding compound is injected into the IC package so that the molding compound surrounds the IC and covers a portion of the top surface of the packaging substrate. The molding compound also covers a perimeter area of the top surface of the IC. A heat conductor is disposed on the top surface of the IC. The heat conductor is in direct contact with the center area of the top surface of the IC and is surrounded by the molding compound.
In yet another embodiment, an IC package is disclosed. The IC package comprises a package substrate with an IC disposed on the surface of the package substrate. A molding compound surrounds the IC and covers a perimeter area of the top surface of the IC, forming a cavity on the top surface of the IC. A heat conductor is placed in the cavity. The heat conductor fills the cavity formed by the molding compound. In one embodiment, the heat conductor is in direct contact with the center area of the top surface of the IC.
Other aspects of the invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.
The invention may best be understood by reference to the following description taken in conjunction with the accompanying drawings in which:
The following embodiments describe apparatuses and a method for creating an IC package with a heat conductor.
It will be obvious, however, to one skilled in the art, that the present invention may be practiced without some or all of these specific details. In other instances, well-known operations have not been described in detail in order not to unnecessarily obscure the present invention.
The embodiments described herein provide techniques to create an IC package with a heat conductor to improve heat dissipation and thermal performance. One embodiment describes an IC package with a high thermal conductivity material used as a heat conductor. Another embodiment describes the process to create an IC package with a heat conductor. These embodiments reduce thermal resistance without limiting the size of the IC chip. Embedding a heat conductor with a high thermal conductivity in the IC package instead of using a conventional heat slug frees up space on the package substrate. Having a heat conductor also allows the device to potentially support medium to high power applications.
Depositing a heat conductor with a relatively high thermal conductivity on top of ICs improves the thermal performances of the IC package. Typical molding compound may not be an effective heat conductor and as such, devices without a built-in heat conductor may not be able to support medium to high power applications that generate a substantial amount of heat. Having a built-in heat conductor improves heat dissipation in the IC and unlike an embedded heat slug, the heat conductor does not take up substantial surface area on the package substrate. Therefore, the described embodiments provide a cost-effective solution to reduce the thermal resistance in an IC package.
The embodiments, thus far, were described with respect to integrated circuits. The method and apparatus described herein may be incorporated into any suitable circuit. For example, the method and apparatus may be incorporated into numerous types of devices such as microprocessors or programmable logic devices. Exemplary programmable logic devices include programmable array logic (PAL), programmable logic array (PLA), field programmable logic array (FPLA), electrically programmable logic devices (EPLD), electrically erasable programmable logic device (EEPLD), logic cell array (LCA), field programmable gate array (FPGA), application specific standard product (ASSP), application specific integrated circuit (ASIC), just to name a few.
Although the method operations were described in a specific order, it should be understood that other operations may be performed in between described operations, described operations may be adjusted so that they occur at slightly different times or described operations may be distributed in a system which allows the occurrence of the processing operations at various intervals associated with the processing, as long as the processing of the overlay operations are performed in a desired way.
Although the foregoing invention has been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications can be practiced within the scope of the appended claims. Accordingly, the present embodiments are to be considered as illustrative and not restrictive, and the invention is not to be limited to the details given herein, but may be modified within the scope and equivalents of the appended claims.
Number | Name | Date | Kind |
---|---|---|---|
5705851 | Mostafazadeh et al. | Jan 1998 | A |
5883430 | Johnson | Mar 1999 | A |
6534859 | Shim et al. | Mar 2003 | B1 |
6720649 | Huang | Apr 2004 | B2 |
8211753 | Ramakrishna et al. | Jul 2012 | B2 |
20010015492 | Akram et al. | Aug 2001 | A1 |
20020166687 | Tornovist et al. | Nov 2002 | A1 |
20030057550 | Zhao et al. | Mar 2003 | A1 |
20030107124 | Huang | Jun 2003 | A1 |
20050046012 | Ramakrishna et al. | Mar 2005 | A1 |
20060019429 | Lee et al. | Jan 2006 | A1 |
20070278664 | Carney et al. | Dec 2007 | A1 |
20080157347 | Takashima | Jul 2008 | A1 |
20090096115 | Huang et al. | Apr 2009 | A1 |
20090127690 | Jaducana et al. | May 2009 | A1 |
20100001410 | Kang | Jan 2010 | A1 |