Patent Application
20230343814
This application is directed, in general, to integrated circuit layouts and in particular, a landing pad of the integrated circuit.
In integrated circuit (IC) layouts, it can be advantageous to place a coil in between a pad (e.g., a contact pad or landing pad or bump pad, PAD) functioning as chip interface to transfer from/to the chip, and an electrostatic discharge (ESD) protection diode, with small area and small parasitic to the signal.
One aspect provides an integrated circuit including a chip substrate having an upper isolation layer with a pad thereon and a coil located below the pad, where, in a dimension perpendicular to a surface of the chip substrate, a perimeter of the coil overlaps with a perimeter of the pad.
Another aspect provides another integrated circuit package including the integrated circuit with the chip substrate, the pad and the coil and further including, one or more first conductive interconnects electrically connecting the coil to the pad, one or more conductive second interconnects electrically connecting the coil to an electrostatic discharge diode located on a base isolation layer of the chip substrate, and, one or more conductive third interconnects electrically connecting the coil to integrated circuit devices located on the base isolation layer.
Another aspect includes a computer having one or more of the integrated circuits.
Reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
Embodiments of the disclosure follow from my idea that instead of placing a PAD, coil and ESD diode horizontally next to each other in an IC layout, the coil can be placed under the PAD to therefore save the layout area and reduce routing parasitics (e.g., parasitic resistance or parasitic capacitance).
This layout design has not have been considered previously because typical fabrication layout rules do not allow a PAD in IC layers next to or overlapping the coil. Additional, traditionally it is thought that because having a PAD overlapping the coil will increase coil impedance, which is to be avoided, the layout design rules require the coil to stand alone or apart in the layout of PADS. However, for some IC layouts not as sensitive to impedance increases, the layout design disclosed herein can advantageously reduce routing parasitics with only a small increase in coil impedance. Moreover, as disclosed herein, while having a PAD overlapping with the coil increases coil impedance, making the coil perimeter bigger than the PAD perimeter can give spacing between the overlapping coil and PAD to mitigate the increased impedance.
Additionally, as part of this disclosure, I recognized that it is important to balance potential reductions the coil's Quality factor (“Q”) with increasing the coil's inductance. I discovered that with the PAD over of the coil, Q can be reduced substantially, while inductance can be increased but to a lesser extent. To mitigate Q degradation, the coil's size can be increased relative to the size of the PAD, but, this will cause inductance to increase. However, since the increase in inductance is relatively smaller as compared to the increase in Q this arrangement of coil and PAD is acceptable.
One embodiment of the disclosure is an integrated circuit that includes such a PAD and coil arrangement.
With continuing reference to
In a dimension 120 perpendicular to a surface 125 of the chip substrate 105, a perimeter 130 of the coil overlaps with a perimeter 132 of the PAD.
In some embodiments, as illustrated in
In some embodiments, in the dimension 120 perpendicular to the surface 125, the perimeter 132 of the PAD 110 is within the perimeter 130 of the coil 115 (e.g.,
In some embodiments, in the dimension 120 perpendicular to the surface 125, the perimeter 130 of the coil 115 is within the perimeter 132 of the PAD 110 (e.g.,
For instance, in some embodiments, in the dimension 120 perpendicular to the surface 125, in the dimension 120 perpendicular to the surface 125, the perimeter 130 of the coil 115 is partially outside the perimeter 132 of the PAD 110 (e.g.,
In any such embodiments, the coil 115 can be electrically connected to the PAD 110 by one or more conductive interconnects (e.g., first interconnects 140). For instance, in some such embodiments, the conductive interconnects 140 can pass through one or more intermediate isolation layers 145 located between the upper isolation layer 107 and the lower isolation layer 117.
In any such embodiments, the coil 115 can be connected by one or more conductive interconnects (e.g., second interconnects 150) to an electrostatic discharge diode 152 located on a base isolation layer 155 of the chip substrate 105. In some such embodiments, the conductive interconnects 150 can pass through one or more redistribution isolation layers 157 located between the lower isolation layer 117 and the base isolation layer 155.
In any such embodiments, the coil 115 can be connected by one or more conductive interconnects (e.g., third interconnects 160) to integrated circuit devices 162 located on a base isolation layer 155 of the chip substrate 105. Non-limiting examples of integrated circuit devices 162 can include one more of a transistor, resistor, capacitor, varactor, diode of the IC 100.
In some embodiments, the coil 115 can be single turn coil while in other embodiments the coil can be a multi-turn coil (e.g., a two, three or four turn coil).
In any such embodiments, the perimeter 130 of the coil 115 coil can have a rectangular, circular, octagonal or other-regular or irregular shaped perimeter as familiar to those skilled in the pertinent art.
In any such embodiments, the perimeter 132 of the PAD 110 can have a rectangular, circular, octagonal or other regular or irregular shaped perimeters as familiar to those skilled in the pertinent art, e.g., as required by a particular fabrication process for solder bump connection.
Another embodiment of the disclosure is an integrated circuit package 180 that any embodiments of the IC disclosed herein. For instance the package can include an IC 100 with the chip substrate 105 having a upper isolation layer 107 with a PAD 110 thereon, a coil 115 located on an lower isolation layer 117, where in a dimension 120 perpendicular to a surface 125 of the chip substrate 105, a perimeter 130 of the coil overlaps with a perimeter 132 of the PAD.
Further, the package 180 can include one or more conductive first interconnects 140 electrically connecting the coil 115 to the PAD 110, one or more conductive second interconnects 150 electrically connecting the coil 115 to an electrostatic discharge diode 152 located on a base isolation layer 155 of the chip substrate 105 and one or more conductive third interconnects 160 electrically connecting the coil 115 to integrated circuit devices 162 located on the base isolation layer 155.
In any such embodiments, the package 180 can further including an input/output solder bump 170 (“I/O bump”
In any such embodiments of the package 180, the integrated circuit devices 162 can includes one or more of a transistor, resistor, capacitor, varactor or diode or similar components as familiar to those skilled in the pertinent art.
Another embodiment of the disclosure is a computer.
Those skilled in the art to which this application relates will appreciate that other and further additions, deletions, substitutions and modifications may be made to the described embodiments.
