Patent Application
20140070321
The technical field relates generally to integrated circuits and methods for fabricating integrated circuits, and more particularly relates to integrated circuits having boron-doped SiGe channels and methods for fabricating such integrated circuits.
Transistors such as metal oxide semiconductor field effect transistors (MOSFETs) or simply field effect transistors (FETs) or MOS transistors are the core building blocks of the vast majority of semiconductor integrated circuits (ICs). A FET includes a gate electrode as a control electrode overlying a semiconductor substrate and spaced apart source and drain regions in the substrate between which a current can flow. A gate insulator is disposed between the gate electrode and the semiconductor substrate to electrically isolate the gate electrode from the substrate. A control voltage applied to the gate electrode controls the flow of current through a channel in the substrate underlying the gate electrode between the source and drain regions. The ICs are usually formed using both P-channel FETs (PMOS transistors or PFETs) and N-channel FETs (NMOS transistors or NFETs) and the IC is then referred to as a complementary MOS or CMOS circuit.
There is a continuing trend to incorporate more and more circuitry on a single IC chip. To incorporate the increasing amount of circuitry, the size of each individual device in the circuit and the size and spacing between device elements (the feature size) must decrease. To achieve scaling of semiconductor devices, a variety of unconventional and/or “exotic” materials are being contemplated. High dielectric constant materials, also referred to as “high-k dielectrics,” such as hafnium silicon oxynitride (HfSiON) and hafnium zirconium oxide (HfZrOx), among others, are considered for the 45 nm technology node and beyond to allow scaling of gate insulators. To prevent Fermi-level pinning, metal gates with the proper work function are used as gate electrodes on the high-k dielectrics. Such metal gate electrodes typically are formed of a metal gate-forming material such as lanthanum (La), aluminum (Al), magnesium (Mg), ruthenium (Ru), titanium-based materials such as titanium (Ti) and titanium nitride (TiN), tantalum-based materials such as tantalum (Ta) and tantalum nitride (TaN) or tantalum carbide (Ta2C), or the like.
In high-k/metal-gate technologies, silicon germanium (SiGe) may be used to form channels for PFETs to enhance electron mobility in the channels and reduce the threshold voltage (V(t)) of the transistors. However, SiGe as a channel material has a few drawbacks. In particular, the V(t) shift of the PFET is a function of the Ge content and thickness of the SiGe channel. The higher the weight percent (wt. %) of Ge in the SiGe channel the lower the PFET V(t), and the thicker the SiGe channel the lower the PFET V(t). Unfortunately, the interface trap density of the SiGe channel increases with higher wt. % of Ge resulting in higher leakage current and reduced current density. Additionally, if the SiGe channel becomes relatively thick, the channel can show signs of plastic stress relaxation, which detrimentally affects the PFET's functionality.
Accordingly, it is desirable to provide integrated circuits (e.g., including high-k/metal-gate technologies) with PFET channels that help enhance electron mobility in the channels and reduce the V(t) of the transistors without substantially increasing leakage current, reducing current density, and/or detrimentally affecting the functionality of the PFETs, and methods for fabricating such integrated circuits. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.
Methods for fabricating integrated circuits are provided herein. In accordance with an exemplary embodiment, a method for fabricating an integrated circuit includes recessing a PFET active region to form a recessed PFET surface region. A boron-doped SiGe channel is formed overlying the recessed PFET surface region.
In accordance with another exemplary embodiment, a method for fabricating an integrated circuit is provided. The method includes masking a NFET active region with a hard mask. A PFET active region is etched to form a recessed PFET surface region. A boron-doped SiGe channel is epitaxially grown overlying the recessed PFET surface region.
In accordance with another exemplary embodiment, an integrated circuit is provided. The integrated circuit includes a PFET active region and a boron-doped SiGe channel formed in the PFET active region. A gate electrode structure is formed above the boron-doped SiGe channel. Source and drain regions are formed in the PFET active region adjacent to the boron-doped SiGe channel.
The various embodiments will hereinafter be described in conjunction with the following drawing figures, wherein like numerals denote like elements, and wherein:
The following Detailed Description is merely exemplary in nature and is not intended to limit the various embodiments or the application and uses thereof Furthermore, there is no intention to be bound by any theory presented in the preceding background or the following detailed description.
Various embodiments contemplated herein relate to integrated circuits with improved PFET channels, and methods for fabricating such integrated circuits. In accordance with one embodiment, during early stages of the fabrication of an integrated circuit (IC), a PFET active region of a semiconductor substrate is recessed, e.g., via wet or dry etching, to form a recessed PFET surface region. A boron-doped SiGe channel is formed overlying the recessed PFET surface region. In an exemplary embodiment, the SiGe channel is in-situ doped with boron during a selective epitaxial growth process. A gate electrode structure is formed above the boron-doped SiGe channel. In an exemplary embodiment, the gate electrode structure is a metal gate electrode structure and includes a high-k dielectric layer, a P-type work function metal layer, and metal gate material layer. Source and drain regions are formed in the PFET active region adjacent to the boron-doped SiGe channel. It has been found that the SiGe channel doped with a relatively small amount of boron (e.g., a boron doping level of from about 1.0×1018 to about 1.0×1019 boron atoms/cm3) helps enhance electron mobility in the channel and further reduces the V(t) of the transistor while the channel thickness and wt. % of Ge in the channel are maintained within ranges that do not substantially increase the interface trap density or detrimentally affect the functionality of the PFETs.
In an exemplary embodiment, an isolation structure 20 (e.g., shallow trench isolation STI) is provided in the semiconductor layer 14. The isolation structure 20 defines corresponding NFET and PFET active regions 22 and 24, which are to be understood as a semiconductor regions having formed therein and/or receiving an appropriate dopant profile as required for forming transistor elements. The NFET and PFET active regions 22 and 24 correspond to the active regions of transistors 26 and 28 (see
The IC 10 as shown in
The portion 32 of the hard mask layer 30 overlying the PFET active region 24 is selectively removed with an etchant, such as hydrochloric acid (HF) or other oxide etchant if the hard mask layer 30 is formed of silicon oxide, to expose a surface 34 of the PFET active region 24. A portion 36 of the hard mask layer 30 remains to protectively cover or mask the NFET active region 22.
The process continues by recessing the PFET active region 24 to form a recessed PFET surface region 38. As illustrated, the PFET active region 24 is recessed to a depth (indicated by single headed arrows “d”) to allow a subsequently-deposited silicon-based material channel, i.e., a boron-doped SiGe channel 40, to achieve a height approximately equal to the height of a surface 42 of the NFET active region 22. In an exemplary embodiment, the depth “d” is from about 5 to about 10 nm. The recessed PFET surface region 38 may be formed by exposing the surface 34 of the PFET active region 24 to a dry etching process and/or a wet etching process. For example, the recessed PFET surface region 38 may be formed on the basis of a substantially anisotropic etch behavior on the basis of a plasma assisted etch, while, in other cases, the recessed PFET surface region 38 may be formed by wet chemical etch chemistries, which may have a crystallographic anisotropic etch behavior, or on the basis of a combination of plasma assisted etch and wet chemical etch chemistries.
In an exemplary embodiment, the boron-doped SiGe channel 40 has a boron doping level of from about 1.0×1018 to about 1.0×1019 boron atoms/cm3, for example, from about 2.5×1018 to about 7.5×1018 boron atoms/cm3. In one embodiment, it has been found that forming the boron-doped SiGe channel 40 having a boron doping level of at least about 1.0×1018 helps enhance electron mobility in the channel 40 and reduce the V(t) of the transistor 28 (see
The process continues as illustrated in
Correspondingly overlying the high-k dielectric layers 50 and 52 are N-type and P-type work function metal layers 54 and 56. In an exemplary embodiment, the N-type work function metal layer 54 is formed of TaC, TiC, or the like, and the P-type work function metal layer 56 is formed of TiN or the like. Disposed over the N-type and P-type work function metal layers 54 and 56 are metal gate material layers 58 and 60, respectively. The metal gate material layers 58 and 60 may be formed of a conductive metal, such as tungsten (W) or the like. Polysilicon layers 62 and 64 are formed correspondingly overlying the metal gate material layers 58 and 60.
The transistors 26 and 28 include sidewall spacers 66 that are formed along the gate electrode structures 44 and 46. The source and drain regions 48 are formed in the semiconductor layer 14 laterally adjacent to the gate electrode structures 44 and 46, and metal silicide regions 68 and 70 are formed in the respective transistors 26 and 28. In particular, the metal silicide regions 68 are formed in the semiconductor layer 14 laterally offset from the respective channels 40 and 49 and are used for forming device contacts with the source and drain regions 48 of the transistors 26 and 28 as is well known in the art.
The IC 10 as shown in
Accordingly, integrated circuits and methods for fabricating integrated circuits have been described. In accordance with one embodiment, during early stages of the fabrication of an integrated circuit (IC), a PFET active region of a semiconductor substrate is recessed to form a recessed PFET surface region. A boron-doped SiGe channel is formed overlying the recessed PFET surface region. It has been found that the SiGe channel doped with a relatively small amount of boron helps enhance electron mobility in the channel and further reduce the V(t) of the transistor while the channel thickness and wt. % of Ge in the channel are maintained within ranges that do not substantially increase the interface trap density or detrimentally affect the functionality of the PFETs.
While at least one exemplary embodiment has been presented in the foregoing detailed description of the disclosure, it should be appreciated that a vast number of variations exist. It should also be appreciated that the exemplary embodiment or exemplary embodiments are only examples, and are not intended to limit the scope, applicability, or configuration of the disclosure in any way. Rather, the foregoing detailed description will provide those skilled in the art with a convenient road map for implementing an exemplary embodiment of the disclosure. It being understood that various changes may be made in the function and arrangement of elements described in an exemplary embodiment without departing from the scope of the disclosure as set forth in the appended claims.
