Patent Application
20240105586
Not Applicable
The present disclosure generally relates to capacitors and, more particularly, to double-sided capacitors that exhibit high capacitance and low series resistance.
Capacitors are an important part of many integrated and embedded circuits and are commonly used as energy storage structures, filters, or as specific components of complex circuits. Capacitors generally make use of high surface area to achieve high capacitance values and are commonly arranged as a pair of thin electrodes separated by a dielectric and rolled into a tight cylindrical structure to optimize the surface area per unit volume. They are also made as deep trenches in silicon to benefit from more surface area, or as layers of dielectric and metal stacked and connected to each other to benefit from both permittivity and surface area.
Efforts to maximize capacitance and minimize equivalent series resistance (ESR) of capacitors have led to the development of double-sided capacitors such as those described in Applicant's own U.S. Patent Application Pub. No. 2023/0067888, entitled “Planar High-Density Aluminum Capacitors for Stacking and Embedding” (“the '888 publication”), and U.S. patent application Ser. No. 18/223,194 (“the '194 application”), filed Jul. 18, 2023 and entitled “Pre-Drilled Vias to capture Double Sided Capacitance,” the entire contents of each of which is incorporated by reference herein. Such arrangements may define a second electrode (e.g., a cathode), such as a conductive polymer, metal, or ceramic, that is disposed on both sides of a first electrode (e.g., an anode) made of aluminum that has been etched or otherwise modified to have a high surface area, with an oxide layer formed therebetween to act as the dielectric. While such double-sided capacitors have the potential to double the usable surface area of the first electrode, they require the formation of structures for accessing the first and second electrodes, including the side of the first electrode that is opposite to the device terminals. To this end, blind and through vias may be formed and filled with a conductive material to provide electrical connections between the electrodes and the device terminals. However, these vias take up valuable surface area, limiting the capacitance of the device. At the same time, when such vias are cut through the built-up stack, their formation may generate heat (due to laser drilling, for example), which may lower the conductivity of the second electrode material, increasing the ESR of the capacitor. In the worst case, debris and mechanical tensions caused by via formation may lead to delamination or fracture, resulting in device failure.
The present disclosure contemplates various devices and methods for overcoming the above drawbacks accompanying the related art. One aspect of the embodiments of the present disclosure is an integrated passive device (IPD) comprising a conductive substrate having a front side and a back side and a plurality of layers including a front dielectric layer on the front side of the conductive substrate, a back dielectric layer on the back side of the conductive substrate, a front conductive polymer layer on the front dielectric layer, and a back conductive polymer layer on the back dielectric layer. The plurality of layers may define a front isolation trench revealing the front side of the conductive substrate and a back isolation trench revealing the back side of the conductive substrate. The IPD may further comprise a first metal contact electrically connected to the conductive substrate by way of a first blind via defined from a front outer surface of the IPD to the front side of the conductive substrate. The first blind via may be positioned within the front isolation trench. The IPD may further comprise a second metal contact electrically isolated from the first metal contact and electrically connected to the front and back conductive polymer layers. The second metal contact may be electrically connected to the back conductive polymer layer by way of a through via defined from the front outer surface of the IPD to a back outer surface of the IPD. The through via may be positioned within the front isolation trench and the back isolation trench.
The front isolation trench may include a first stretch and a second stretch on opposite borders of the IPD. The first blind via may be positioned within the first stretch of the front isolation trench. The through via may be positioned within the second stretch of the front isolation trench. The front isolation trench may include a third stretch and a fourth stretch on opposite borders of the IPD connecting the first and second stretches of the front isolation trench.
The IPD may comprise a third metal contact electrically connected to the conductive substrate by way of a second blind via defined from a back outer surface of the IPD to the back side of the conductive substrate. The second blind via may be positioned within the back isolation trench. The back isolation trench may include a first stretch and a second stretch on opposite borders of the IPD respectively aligned with the first and second stretches of the front isolation trench. The second blind via may be positioned within the first stretch of the back isolation trench. The through via may be positioned within the second stretch of the back isolation trench. The back isolation trench may include a third stretch and a fourth stretch on opposite borders of the IPD connecting the first and second stretches of the back isolation trench.
Another aspect of the embodiments of the present disclosure is an IPD comprising a conductive substrate having a front side and a back side and a plurality of layers including a front dielectric layer on the front side of the conductive substrate, a back dielectric layer on the back side of the conductive substrate, a front conductive polymer layer on the front dielectric layer, and a back conductive polymer layer on the back dielectric layer. The plurality of layers may define a front isolation trench revealing the front side of the conductive substrate and a back isolation trench revealing the back side of the conductive substrate. The IPD may further comprise a first metal contact electrically connected to the conductive substrate and a second metal contact electrically isolated from the first metal contact and electrically connected to the front and back conductive polymer layers. The second metal contact may be electrically connected to the back conductive polymer layer by way of a through via defined from the front outer surface of the IPD to a back outer surface of the IPD. The through via may be positioned within the front isolation trench and the back isolation trench.
The front isolation trench may include a first stretch and a second stretch on opposite borders of the IPD. The back isolation trench may include a first stretch and a second stretch on opposite borders of the IPD respectively aligned with the first and second stretches of the front isolation trench. The through via may be positioned within the second stretch of the front isolation trench and the second stretch of the back isolation trench. The front isolation trench may include a third stretch and a fourth stretch on opposite borders of the IPD connecting the first and second stretches of the front isolation trench. The back isolation trench may include a third stretch and a fourth stretch on opposite borders of the IPD connecting the first and second stretches of the back isolation trench.
Another aspect of the embodiments of the present disclosure is an IPD comprising a conductive substrate having a front side and a back side and a plurality of layers including a front dielectric layer on the front side of the conductive substrate, a back dielectric layer on the back side of the conductive substrate, a front conductive polymer layer on the front dielectric layer, and a back conductive polymer layer on the back dielectric layer. The plurality of layers may define a front isolation trench revealing the front side of the conductive substrate and a back isolation trench revealing the back side of the conductive substrate. The IPD may further comprise a first metal contact electrically connected to the conductive substrate by way of a first blind via defined from a front outer surface of the IPD to the front side of the conductive substrate. The first blind via may be positioned within the front isolation trench. The IPD may further comprise a second metal contact electrically isolated from the first metal contact and electrically connected to the front and back conductive polymer layers.
The front isolation trench may include a first stretch and a second stretch on opposite borders of the IPD. The first blind via may be positioned within the first stretch of the front isolation trench. The IPD may comprise a third metal contact electrically connected to the conductive substrate by way of a second blind via defined from a back outer surface of the IPD to the back side of the conductive substrate, the second blind via being positioned within the back isolation trench. The back isolation trench may include a first stretch and a second stretch on opposite borders of the IPD respectively aligned with the first and second stretches of the front isolation trench. The second blind via may be positioned within the first stretch of the back isolation trench. The front isolation trench may include a third stretch and a fourth stretch on opposite borders of the IPD connecting the first and second stretches of the front isolation trench. The back isolation trench may include a third stretch and a fourth stretch on opposite borders of the IPD connecting the first and second stretches of the back isolation trench.
In the IPD of any of the aspects of the embodiments of the present disclosure, the plurality of layers may include a front metallization layer arranged to promote electrical conductivity between the front conductive polymer layer and the second metal contact and a back metallization layer arranged to promote electrical conductivity between the back conductive polymer layer and the second metal contact. The plurality of layers may include a front carbonaceous layer on the front conductive polymer layer and a back carbonaceous layer on the back conductive polymer layer. The front metallization layer may be on the front carbonaceous layer and the back metallization layer being on the back carbonaceous layer.
These and other features and advantages of the various embodiments disclosed herein will be better understood with respect to the following description and drawings, in which like numbers refer to like parts throughout, and in which:
The present disclosure encompasses various embodiments of integrated passive devices (IPD) containing capacitors and methods of manufacturing the same. The detailed description set forth below in connection with the appended drawings is intended as a description of several currently contemplated embodiments and is not intended to represent the only form in which the disclosed subject matter may be developed or utilized. The description sets forth the functions and features in connection with the illustrated embodiments. It is to be understood, however, that the same or equivalent functions may be accomplished by different embodiments that are also intended to be encompassed within the scope of the present disclosure. It is further understood that the use of relational terms such as first and second and the like are used solely to distinguish one from another entity without necessarily requiring or implying any actual such relationship or order between such entities.
Advantageously, one or both of these same isolation trenches 160-1, 160-2 may be the site of features such as vias for connecting the IPD 100 to external devices in order to incorporate the IPD 100 into energy storage structures, filters, or other circuit components depending on the particular application. In this way, the same area of the substrate 110 that is reserved for isolation may be leveraged to make electrical connections to the device terminals, allowing for a more efficient use of surface area that reduces the risk of thermal and mechanical damage by eliminating the need to drill through other portions of the layer buildup. In particular, the terminals of the IPD 100 may include a first metal contact 170-1 (e.g., an anode terminal) that is electrically connected to the conductive substrate 110 by way of one or more first blind vias 172-1 defined from a front outer surface 102 of the IPD 100 to the front side 112 of the conductive substrate 110. As shown, the first blind via(s) 172-1 may advantageously be positioned within the front isolation trench 160-1. The terminals of the IPD 100 may further include a second metal contact 180-1 (e.g., a cathode terminal) that is electrically isolated from the first metal contact 170-1 and electrically connected to the front and back conductive polymer layers 130-1, 130-2. The second metal contact 180-1 may be connected to the front conductive polymer layer 130-1 by way of one or more blind vias 184-1 formed between the second metal contact 180-1 and a landing pad 186-1 that is electrically connected to the front conductive polymer layer 130-1 (e.g., with intervening carbon and metal layers as described below). The second metal contact 180-1 may also be electrically connected to the back conductive polymer layer 130-2 by way of one or more through vias 182 defined from the front outer surface 102 of the IPD 100 to a back outer surface 104 of the IPD 100. For example, the through via(s) 182 may terminate at another metal contact 180-2 formed on the back outer surface 104 of the IPD 100, which may be connected to the back conductive polymer layer 130-2 by way of one or more blind vias 184-2 formed between the second metal contact 180-2 and a landing pad 186-2 that is electrically connected to the back conductive polymer layer 130-2 (e.g., with intervening carbon and metal layers as described below). As shown, the through via(s) 182 may advantageously be positioned within the front isolation trench 160-1 and the back isolation trench 160-2.
In addition to the first and second metal contacts 170-1, 180-1, which may be provided on the front outer surface 102 of the IPD 100 (allowing for connection of the IPD 100 to external circuits from a single side in some cases), the IPD 100 may additionally have third and/or fourth metal contacts 170-2, 180-2 provided on the back outer surface 104 of the IPD 100 opposite the front outer surface 102. The third metal contact 170-2 may be electrically connected to the conductive substrate 110 by way of one or more second blind vias 172-2 defined from the back outer surface 104 of the IPD 100 to the back side 114 of the conductive substrate 110. As shown, the second blind via(s) 172-2 may be positioned within the back isolation trench 160-2. The fourth metal contact 180-2 may, as described above, be electrically connected to the second metal contact 180-1 and to the front and back conductive polymer layers 130-1, 130-2 by way of the through via(s) 182, the blind vias 184-1, 184-2, and the landing pads 186-1, 186-2. In the case of multiple stacked capacitors within the same IPD 100, it is contemplated that the passthrough connection defined by the through via 182 and the second and fourth metal contacts 180-1, 180-2 may be preserved through stacking (i.e., may remain unblocked and functional) by the implementation of appropriate stacking arrangements.
As best seen in
A process of making the IPD 100 may begin with providing the conductive substrate 110, which may be made of aluminum, an aluminum alloy, or another material that is etched or otherwise modified to have a high surface area, such as an etched aluminum foil as described in the '888 publication. Alternative or additional modifications to increase the surface area of the conductive substrate 110 may include deposition of a sintered aluminum powder or other aluminum, aluminum oxide, titanium, or titanium oxide powder thereon. The conductive substrate 110 may be a metal foil as described in Applicant's own U.S. Patent Application Pub. No. 2023/0073898, entitled “Modified Metal Foil Capacitors and Methods for Making Same,” the entire contents of which is incorporated by reference herein. As illustrated, the conductive substrate 110 may thus comprise a solid metal portion 116 and a high surface area portion 118 on front and back sides 112, 114 thereof. It is noted that the formation of isolation trenches 160-1, 160-2 and blind vias 172-1, 172-2 from the outside of the IPD 100 to the front or back side 112, 114 of the conductive substrate 110 may (though need not necessarily) stop at the solid metal portion 116 as illustrated in
The dielectric layer 120-1, 120-2 (separately referenced as front and back layers), which may be a naturally occurring oxide layer (e.g., an aluminum oxide layer) or one that has been grown by an anodization process (e.g., by placing the conductive substrate 110 in an electrolytic solution and passing a current through the solution), grown by thermal oxidation in a humidity chamber, or coated on the conductive substrate 110 (e.g., by atomic layer deposition), may then be formed on both sides of the conductive substrate 110. As may be appreciated, the dielectric layer 120-1, 120-2 may, in general, exhibit the same high surface area as the underlying conductive substrate 110 as it fills in and takes the shape of the various tunnels and recesses that may result from the etching or other modification to the material of the conductive substrate 110. Higher dielectric constant materials are also contemplated in order to improve capacitance for the same surface area, such as HfO2, ZrO2, BaO, and TiO2. These materials may be deposited instead of or in addition to aluminum oxide (Al2O3), for example, by conformal deposition such as selective atomic layer deposition (ALD).
The conductive polymer layer 130-1, 130-2 may then be provided on the front and back dielectric layers 120-1, 120-2, in some cases following a process of pre-drilling one or more vias as described in the '194 application. In this way, the second electrode (e.g., cathode) defined by the conductive polymer layer 130-1, 130-2 may beneficially extend over both sides of the first electrode (e.g., anode) defined by the conductive substrate 110 with the dielectric layer 120-1, 120-2 therebetween, effectively taking advantage of both sides of the conductive substrate 110 to double the surface area and thus the capacitance. It is noted that, like the dielectric layer 120-1, 120-2, the conductive polymer layer 130-1, 130-2 may exhibit the same high surface area as the underlying conductive substrate 110 as it fills in and takes the shape of the various tunnels and recesses that may result from the etching or other modification to the material of the conductive substrate 110, in this case with the dielectric layer 120-1, 120-2 sandwiched therebetween. A variety of conductive polymers may be suitable for use as the second electrode of the capacitor described herein. The conductive polymer layer 130-1, 130-2 may, for example, comprise one or more of a polypyrrole, a polythiophene, a polyaniline, a polyacetylene, a polyphenylene, a poly(p-phenylene-vinylene), PEDOT:PSS (poly(3,4-ethylenedioxythiophene) polystyrene sulfonate), or P3HT (poly(3-hexylthiophene-2,5-diyl)).
As shown in
After the stack buildup on both sides of the conductive substrate 110, the isolation trenches 160-1, 160-2 may be formed, followed by formation of the blind and through vias 172-1, 172-2, 182 within the isolation trenches 160-1, 160-2 as described above. Additional vias 184-1, 184-2 and landing pads 186-1, 186-2 may be formed at this stage as well for electrical connection of the second and fourth metal contacts 180-1, 180-2 to the conductive polymer layers 130-1, 130-2 serving as the second electrode of the capacitor. It is noted that the ABF or other insulating material into which the vias 172-1, 172-2, 182, 184-1, 184-2 are drilled (prior to being filled with a conductive via fill) may remain and may serve to fill in all the remaining space of the IPD 100 to prevent shorting of the electrodes (though for ease of illustration the insulating material is not shown). The metal contacts 170-1, 170-2, 180-1, 180-2 may then be formed on the outermost surfaces 102, 104 of the IPD 100 (e.g., on the insulating material) in contact with the vias 172-1, 172-2, 182, 184-1, 184-2, thus establishing the electrical connections described above. In this way, the resulting IPD 100 may advantageously utilize the area of the existing isolation trenches 160-1, 160-2 for connection of the capacitor to external devices, thus avoiding any additional removal of the layer buildup representing the domain area of the capacitor.
Exemplary capacitor cells are shown in Tables 1 and 2, below, with Table 1 showing layout measurements for three types of cells A, B, and C for the via-in-trench design and Table 2 showing layout measurements for three corresponding types of cells A, B, and C for an alternative design in which the blind and through vias are formed outside of the isolation trenches:
In Tables 1 and 2, “BS” stands for “blind slot” and refers to the dimensions of the area containing the blind vias 172-1, 172-2, “TS” stands for “through slot” and refers to the dimensions of the through via region 183 containing the through vias 182, and “TSBS” refers to “through slot blind slot” and refers to a blind feature cut prior to the through via region 183 to ensure the stack is not shorted when creating the through via region 183. The effective area of each cell is the original domain area (e.g., 4 mm2 in the case of the A cell) minus the BS area and the TSBS area (without additionally subtracting the TS area because it is defined within the TSBS area). The effective area refers to that area of a single side of the capacitor (and would effectively be doubled for double-sided capacitors as described herein. As can be seen, the via-in-trench structure of Table 1 supports an 82% increase in TS size for A cells, a 58% increase in TS size for B cells, and a 13% increase in TS size for C cells relative to the alternative structure, resulting in effective area increases of 6%, 8.4%, and 8.7%, respectively. In this example, the A, B, and C cells of Table 1 have the same footprint as the A, B, and C cells of Table 2: 2.2 mm by 2.2 mm for an A cell, 2.2 mm by 4.2 mm for a B cell, and 2.7125 by 13.2 mm for a C cell.
The above description is given by way of example, and not limitation. Given the above disclosure, one skilled in the art could devise variations that are within the scope and spirit of the invention disclosed herein. Further, the various features of the embodiments disclosed herein can be used alone, or in varying combinations with each other and are not intended to be limited to the specific combination described herein. Thus, the scope of the claims is not to be limited by the illustrated embodiments.
This application relates to and claims the benefit of U.S. Provisional Application No. 63/376,688, filed Sep. 22, 2022 and entitled “VIA SLOTS IN ISOLATION TRENCH TO IMPROVE SERIES RESISTANCE, CAPACITANCE, AND ISOLATION AND METHODS OF MAKING THE SAME,” the entire contents of which is incorporated by reference herein.
| Number | Date | Country | |
|---|---|---|---|
| 63376688 | Sep 2022 | US |
