Patent Application
20250096082
Many applications such as automotive and industrial applications utilize semiconductor packages to accommodate high voltage loads. These semiconductor packages can be configured as discrete components or may be configured as power converter circuits such as single and multi-phase half-wave rectifiers, single and multi-phase full-wave rectifiers, voltage regulators, etc. These semiconductor packages can include power devices such as diodes, IGBTs (insulated gate bipolar transistors), MOSFETs (metal oxide semiconductor field effect transistors), HEMTs (high electron mobility transistors), etc. Thermal and electrical performance play an increasing role in the advancement of semiconductor packages. Many power semiconductor packages require electrical connections with low electrical resistance and high current capacity that can be formed reliably and inexpensively.
An electrical interconnect clip is disclosed. According to an embodiment, the electrical interconnect clip comprises a die interface portion that is adapted for mating in between two vertically stacked semiconductor dies, and a carrier connection portion that is configured to electrically connect the two vertically stacked semiconductor dies with a carrier, wherein the die interface portion comprises a lower mating surface, an upper mating surface opposite from the lower mating surface, and a solder retention feature formed by one or more grooves in the upper mating surface that are spaced apart from the outer edge sides of the electrical interconnect clip and form a border surrounding a die attach area of the upper mating surface.
A method of forming a semiconductor package is disclosed. According to an embodiment, the method comprises providing a carrier comprising a die pad and a plurality of leads, providing first and second semiconductor dies, each being configured as vertical power devices, providing a electrical interconnect clip that comprises a die interface portion and a carrier connection portion, proving a stacked die arrangement on the die pad that comprises the die interface portion of the electrical interconnect clip arranged between the first and second semiconductor dies and the carrier connection portion contacting the carrier, providing solder material in between the second semiconductor die and the die interface portion of the electrical interconnect clip, and performing a soldering process that liquifies the solder material, wherein the electrical interconnect clip comprises a solder retention feature that forms a border at least partially surrounding the second semiconductor die, and wherein the solder retention feature interacts with liquified solder during the soldering process by retaining the solder material within a confined space that surrounds the second semiconductor die, thereby preventing floating movement of the second semiconductor die.
Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings.
The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts. The features of the various illustrated embodiments can be combined unless they exclude each other. Embodiments are depicted in the drawings and are detailed in the description which follows.
Embodiments of an electrical interconnect clip, a method of forming a semiconductor package using the electrical interconnect clip, and a corresponding semiconductor package are disclosed herein. The semiconductor package includes a stacked die arrangement with two semiconductor dies stacked on top of one another and mounted on a carrier. The electrical interconnect clip is inserted between the two semiconductor dies and forms an electrical connection with terminals from both of the dies and the carrier. The electrical interconnect clip advantageously comprises a solder retention feature formed by a groove or set of grooves that surround the die attach area of the upper semiconductor die. The solder retention feature receives and retains excess solder that flows out from the upper semiconductor die during a soldering process. This retention of the excess solder material prohibits floating moment of the upper semiconductor die while the solder material is in a liquified state, thereby maintaining the position of the upper semiconductor die in its desired location. The provision of the solder retention feature may eliminate the need for providing a special plating on the electrical interconnect clip and thus reduce cost.
Referring to
The electrical interconnect clip 100 comprises a die interface portion 102 and a carrier connection portion 104. The die interface portion 102 is adapted for mating in between two vertically stacked semiconductor dies. That is, the die interface portion 102 is configured to interface with one semiconductor die below it and one semiconductor die above it. To this end, the die interface portion 102 comprises a lower mating surface 106 and an upper mating surface 107 opposite from the lower mating surface 106. The lower mating surface 106 and the upper mating surface 107 are each substantially planar surfaces that can be arranged to be flush against a semiconductor die. The carrier connection portion 104 corresponds to an outer part of the electrical interconnect clip 100 that facilitates an electrical connection with an external carrier. The carrier connection portion 104 forms a vertical transition between the die interface portion 102 and an outer end of the carrier connection portion 104 that is below the die interface portion 102 and used to contact the external carrier. As shown, the carrier connection portion 104 comprises a perpendicular transition which may correspond to a punch in the metal. More generally, the carrier connection portion 104 may comprise different geometries such as curved transitions, rounded corners, etc.
The die interface portion 102 of the electrical interconnect clip 100 comprises a solder retention feature 108 formed by a groove 110 in the upper mating surface 107. The groove 110 is an intentionally formed trench-like structure that extends inward from the upper mating surface 107 of the electrical interconnect clip 100 towards the lower mating surface 106. The groove 110 can be created by processing an initially planar metal surface using a metal processing technique, e.g., coining, etching, cutting, stamping, etc. to remove metal or other otherwise disturb the planarity of the surface. The groove 110 is spaced apart from the outer edge sides of the electrical interconnect clip 100. That is, the groove 110 is fully confined within an interior region of the upper mating surface 107. A separation distance between the groove 110 and the outer edge sides of the electrical interconnect clip 100 may be between 25 μm and 100 μm, for example. The groove 110 surrounds a die attach area of the upper mating surface 107.
According to an embodiment, the solder retention feature 108 is formed by a continuous groove 110 that forms an enclosed shape around the die attach area 112 in the upper mating surface 107. That is, the solder retention feature 108 completely surrounds the die attach area 112 on the upper mating surface 107.
According to an embodiment, the groove 110 has a depth of between 10 μm and 50 μm. In a particular embodiment, the depth of the groove 110 is about 20-25 μm. The depth refers to the distance between the upper mating surface 107 and the lowest point of the groove 110 that is closest to the lower mating surface 106.
According to an embodiment, the groove 110 has v-shaped cross-sectional geometry.
Referring to
The assembly 200 comprises a plurality of semiconductor dies mounted on the die pad portion of the carrier. The semiconductor dies include pairs of vertical power device dies 206 mounted in vertically stacked arrangements. The vertical power device dies 206 are discrete power devices that are rated to accommodate voltages of at least 100 V (volts), e.g., voltages of 600 V, 1200 V or more and/or are rated to accommodate currents of at least 1A, e.g., currents of 10A, 50A, 100A or more. Examples of vertical power device dies 206 include diodes, transistors, thyristors, junction field effect transistors, etc. In a particular example, the vertical power device dies 206 are configured as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), IGBTs (Insulated Gate Bipolar Transistors), or HEMTs (High Electron Mobility Transistors). The term vertical refers to the fact that the power device dies conduct current in a vertical direction between a first load terminal disposed on a main surface and a second load terminal disposed on the rear surface opposite from the main surface. The first and second load terminals may respectively correspond to the source and drain terminals (or vice-versa) in the case of a MOSFET and may respectively correspond to the emitter and collector terminals (or vice-versa) in the case of an IGBT, and so forth. The assembly 200 additionally comprises an additional logic device die 208 mounted on a low voltage plane separate from the vertically stacked arrangements. The logic device die 208 may be an integrated circuit, such as a silicon logic die, for example.
According to an embodiment, the vertically stacked arrangements of semiconductor dies are each configured as a half bridge circuit. A half-bridge circuit refers to one type of circuit topology that is used in a power conversion circuit, such as a DC to DC converter, DC to AC converter, etc. In a half bridge circuit, one load terminal of the high-side switch (e.g., the source/emitter) is connected to a first DC voltage (e.g., a positive potential), one load terminal of the low-side switch (e.g., the drain/collector) is connected to a second DC voltage (e.g., negative potential or ground), and the remaining two load terminals (e.g., the drain/collector of the high-side switch and the source/emitter of the low-side switch) are connected together to form the output or switch (‘SW’) of the half-bridge circuit. The control (gate) terminals of the high-side and low-side switch can be switched according to a power control scheme (e.g., pulse width modulation) to produce a desired voltage and frequency at the output of the half-bridge circuit. For example, a first one of the vertical power device dies 206 mounted directly on the die pad 202 may correspond to a high-side switch of the half bridge circuit, and a second one of the vertical power device dies 206 mounted above the first one of the vertical power device dies 206 may correspond to the low-side switch of the half bridge circuit. The logic device die 208 may be configured to provide the switching signal to the control terminals of the high-side and low-side switch. Electrical interconnection between the logic device die 208 and the vertically stacked arrangements of semiconductor dies may be provided by additional electrical interconnect elements, e.g., bond wires, clips, ribbons, etc., that are not shown in the figure. As shown, the semiconductor package assembly 200 comprises three of the vertically stacked arrangements of semiconductor dies. This configuration may be used to create a full-bridge arrangement, wherein each of the vertically stacked arrangements of semiconductor forms one phase of the full-bridge arrangement.
Each of the vertically stacked arrangements are mounted in the following way. A first one of the vertical power device dies 206 is mounted on the die pad 202 with a first load terminal (e.g., a source terminal) facing the die pad 202 and a second load terminal (e.g., a drain terminal) facing away from the die pad 202. The die interface portion 102 of the electrical interconnect clip is arranged over the first one of the vertical power device dies 206 with the lower mating surface 106 facing the second load terminal of the first vertical power device die 206. A second one of the vertical power device dies 206 is mounted on the die interface portion 102 of the electrical interconnect clip 100 with a first load terminal facing (e.g., a drain terminal) the electrical interconnect clip 100 and a second load terminal (e.g., a source terminal) facing away from the electrical interconnect clip 100. A second electrical interconnect clip 210 is provided above the second vertical power device die 206 and mated with the second load terminal of the second vertical power device die 206. In this arrangement, the first load terminal of the first vertical power device die 206 is electrically connected to the die pad 202, which in turn is connected to the leads 204, the second load terminal of the second vertical power device die 206 is electrically connected to the leads 204 via the second electrical interconnect clip 210, and the second load terminal of the first vertical power device die 206 and the first load terminal of the second vertical power device die 206 are each electrically connected to the leads 204 via the electrical interconnect clip 100. In the half-bridge configuration, the connection provided by the die pad 202 to the first vertical power device die 206 may correspond to the first DC voltage connection, the connection provided by the second electrical interconnect clip 210 to the second vertical power device die 206 may correspond to the second DC voltage connection, and the connection provided between the first and second vertical power device dies 206 and the electrical interconnect clip 100 may correspond to the phase connection.
Forming the semiconductor package may comprise one or more soldering processes. These soldering processes include a soldering process that solders the first load terminal of the second vertical power device die 206 with the die interface portion 102 of the electrical interconnect clip 100 and thus electrically connects the two together. According to this process, a solder material is provided between the upper mating surface 107 of the electrical interconnect clip 100 and the load terminal of the second vertical power device die 206. This solder material may be a solder paste comprising a tin based and/or lead-free solder material, for example. The solder material may be initially applied on one or both of the upper mating surface 107 of the electrical interconnect clip 100 and the second vertical power device die 206, e.g., as a preform, solder ball, etc. With the second vertical power device die 206 intact and positioned in a desired location on the electrical interconnect clip 100, a heating process is performed whereby the temperature of the solder material is elevated to melt the material and induce a reaction whereby a stable soldered joint is formed. A peak temperature of this heating process occurs at a reflow phase of this heating process. Reflow temperatures for this soldering process may be in the range of 200° C. to 300° C., for example. This heating process may form additional soldered joints as well, including any of the soldered joints necessary to form the above-described electrical connections.
During the above-described soldering step, the solder retention feature 108 advantageously maintains the position of the second vertical power device die 206. In more detail, the solder retention feature 108 forms a border around the second vertical power device die 206 and interacts with liquified solder during the heating process by retaining the solder material within a confined space that surrounds the second vertical power device die 206. As a result, the liquified solder material gathers at the border around the perimeter of the second vertical power device die 206 and prevents floating movement of the second vertical power device die 206 during the reflow process. The gathering of the liquified solder material in the solder retention feature 108 forms a meniscus that prevents the second vertical power device die 206 from freely moving (floating) on the liquified solder material. In particular, the second vertical power device die 206 is prevented from moving rotationally from a plan-view perspective. By way of comparison, a rotational movement of 5 degrees or more has been observed in electrical interconnect clips that do not include the solder retention feature 108 described herein, which can potentially lead to problematic failure and/or semiconductor dies extending over the edge side of the electrical interconnect clip.
Advantageously, the solder retention feature 108 may eliminate the need for special plating on the electrical interconnect clip, such as Ag plating layers, that may be used to prevent floating movement of a semiconductor die but add cost and complexity. Thus, according to an embodiment, the surfaces of the electrical interconnect clip 100, and in particular the die attach area 112 may be surfaces of exposed base material metal, such as a bare copper, bare aluminum, and alloys thereof.
After mounting the dies and forming the electrical interconnections, an encapsulation process may be formed to cover the carrier, the semiconductor dies and associated electrical connections. Meanwhile, outer ends of the leads 204 remain exposed from the electrically insulating encapsulant body forming externally accessible package terminals. The encapsulation process may include forming an electrically insulating mold compound, e.g., by injection molding, transfer molding, compression molding, etc. A dicing process may be performed to form a complete semiconductor package.
Referring to
As used herein, the term surround incudes completely continuous geometries that form an enclosed shape and non-continuous geometries that form an enclosed shape with interruptions. For instance, a rectangle with localized interruptions is a geometry that surrounds an interior area, provided that at least part of the interior area borders the rectangle on all four sides.
The semiconductor die disclosed herein can be formed in a wide variety of device technologies that utilize a wide variety of semiconductor materials. Examples of such materials include, but are not limited to, elementary semiconductor materials such as silicon (Si) or germanium (Ge), group IV compound semiconductor materials such as silicon carbide (SIC) or silicon germanium (SiGe), binary, ternary or quaternary III-V semiconductor materials such as gallium nitride (GaN), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium gallium phosphide (InGaPa), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), aluminum gallium indium nitride (AlGaInN) or indium gallium arsenide phosphide (InGaAsP), etc.
The semiconductor die disclosed herein may be configured as a vertical device, which refers to a device that conducts a load current between opposite facing main and rear surfaces of the die. Alternatively, the semiconductor die may be configured as a lateral device, which refers to a device that conducts a load current parallel to a main surface of the die.
Spatially relative terms such as “under,” “below,” “lower,” “over,” “upper” and the like, are used for ease of description to explain the positioning of one element relative to a second element. These terms are intended to encompass different orientations of the device in addition to different orientations than those depicted in the figures. Further, terms such as “first,” “second,” and the like, are also used to describe various elements, regions, sections, etc. and are also not intended to be limiting. Like terms refer to like elements throughout the description.
As used herein, the terms “having,” “containing,” “including,” “comprising” and the like are open-ended terms that indicate the presence of stated elements or features, but do not preclude additional elements or features. The articles “a,” “an” and “the” are intended to include the plural as well as the singular, unless the context clearly indicates otherwise.
Although the present disclosure is not so limited, the following numbered examples demonstrate one or more aspects of the disclosure.
Example 1. An electrical interconnect clip, comprising: a die interface portion that is adapted for mating in between two vertically stacked semiconductor dies; and a carrier connection portion that is configured to electrically connect the two vertically stacked semiconductor dies with a carrier, wherein the die interface portion comprises: a lower mating surface; an upper mating surface opposite from the lower mating surface; and a solder retention feature formed by one or more grooves in the upper mating surface that are spaced apart from outer edge sides of the electrical interconnect clip and surround a die attach area of the upper mating surface.
Example 2. The electrical interconnect clip of example 1, wherein the solder retention feature is formed by a continuous one of the grooves that forms an enclosed shape around the die attach area of the upper mating surface.
Example 3. The electrical interconnect clip of example 2, wherein the continuous one the grooves forms a rectangle around the die attach area of the upper mating surface.
Example 4. The electrical interconnect clip of example 1, wherein the one or more grooves have v-shaped cross-sectional geometry.
Example 5. The electrical interconnect clip of example 4, wherein an intersection angle between sidewalls of the one or more grooves is between 50° and 70°.
Example 6. The electrical interconnect clip of example 1, wherein the one or more grooves have a depth of between 20 μm and 50 μm.
Example 7. The electrical interconnect clip of example 1, wherein the electrical interconnect clip is formed from a base metal of copper, aluminum, or alloys thereof, and wherein the die attach area of the upper mating surface is a bare surface of the base metal.
Example 8. A semiconductor package, comprising the electrical interconnect clip of claim 1.
Example 9. The semiconductor package of example 8, wherein the semiconductor package comprises first and second semiconductor dies mounted in a stacked die arrangement with the interface portion of the electrical interconnect clip arranged between the first and second semiconductor dies, and wherein the one or more grooves of the solder retention feature surround the second semiconductor die.
Example 10. The semiconductor package of example 9, wherein the first and second semiconductor dies are each configured as discrete transistor dies, wherein the first and second semiconductor dies are arranged in a half-bridge configuration, and wherein the electrical interconnect clip forms a phase terminal connection that electrically connects load terminals from the first and second semiconductor dies to one or more leads of the semiconductor package.
Example 11. A method of forming a semiconductor package, the method comprising: providing a carrier comprising a die pad and a plurality of leads; providing first and second semiconductor dies, each being configured as vertical power devices, providing an electrical interconnect clip that comprises a die interface portion and a carrier connection portion; proving a stacked die arrangement on the die pad that comprises the die interface portion of the electrical interconnect clip arranged between the first and second semiconductor dies and the carrier connection portion contacting the carrier; providing solder material in between the second semiconductor die and the die interface portion of the electrical interconnect clip; and performing a soldering process that liquifies the solder material, wherein the electrical interconnect clip comprises a solder retention feature that forms a border surrounding the second semiconductor die, and wherein the solder retention feature interacts with liquified solder during the soldering process by retaining the solder material within a confined space that surrounds the second semiconductor die, thereby preventing floating movement of the second semiconductor die.
Example 12. The method of example 11, wherein the solder retention feature is formed by one or more grooves in an upper mating surface of the die interface portion that are spaced apart from outer edge sides of the electrical interconnect clip and form a border surrounding a die attach area of the upper mating surface, and wherein the one or more grooves become at least partially filled by the liquified solder material during the soldering process.
Example 13. The method of example 12, wherein the liquified solder material that fills the one or more grooves during the soldering process forms a meniscus that prevents the floating movement of the second semiconductor die during the soldering process.
Example 14. The method of example 12, wherein the solder retention feature is formed by a continuous one of the grooves that forms an enclosed shape around the upper mating surface.
Example 15. The method of example 12, wherein the one or more grooves have v-shaped cross-sectional geometry.
Example 16. The method of example 15, wherein an intersection angle between sidewalls of the one or more grooves is between 50° and 70°.
Example 17. The method of example 12, wherein the one or more grooves have a depth of between 20 μm and 50 μm.
Example 18. The method of example 12, wherein the electrical interconnect clip is formed from a base metal of copper, aluminum, or alloys thereof, and wherein the die attach area of the upper mating surface is a bare surface of the base metal.
Example 19. The method of example 11, wherein the first and second semiconductor dies are each configured as discrete transistor dies, wherein the first and second semiconductor dies are arranged in a half-bridge configuration, and wherein the electrical interconnect clip forms a phase terminal connection that electrically connects load terminals from the first and second semiconductor dies to one or more of the leads.
Example 20. The method of example 19, further comprising providing a second electrical interconnect clip and electrically connecting a second load terminal of the second semiconductor die with the carrier via the second electrical interconnect clip.
With the above range of variations and applications in mind, it should be understood that the present invention is not limited by the foregoing description, nor is it limited by the accompanying drawings. Instead, the present invention is limited only by the following claims and their legal equivalents.
