Patent Application
20120261165
The present disclosure relates to a interconnect devices and processes for fabricating interconnect devices, such as flexible printed circuits, and more particularly to a print and plate process for producing interconnect devices for use in electronic systems, in particular imaging systems, such as, for example, magnetic resonance imaging systems.
It is known to create electrical interconnection layers. Printed circuit boards are such an example of fabricating electrical interconnect layers between electrical insulating layers to form rigid electrical interconnect systems. It is also known to create electrical interconnections between layers of electrical insulating layers to form flexible interconnect systems, such as, for example, flexible printed circuits. The rigidity or flexibility of the resulting circuits is dependent on the choice of design, features, materials and processes used.
Flexible printed circuits have found applicability in numerous applications. One such application is in magnetic resonance imaging equipment. Magnetic resonance imaging (MRI) equipment uses radio frequency coils to scan a body. The coils include a conductive loop and in-series capacitors. It often is necessary to form the radio frequency coils of an MRI device on a flexible substrate, due to the many varied applications in which such a device is used and the desire to maximize performance by conforming the device to the non-planar patient anatomy.
It is known to provide such radio frequency coils on a flexible substrate. Prior methods for doing so generally include providing traditionally applied circuitry on relatively expensive polymeric substrates and utilizing a subtractive process to arrive at a finished coil. Such prior methods are wasteful and environmentally troubling. Specifically, such prior methods subtract away copper applied on the substrate. The cost of copper is increasing, which has led to an increase in the cost to manufacture MRI coils. Further, chemicals that can adversely impact the environment are utilized in the known fabrication processes.
With particular attention to
At step 505, vias are formed in the substrate through known means, such as, for example, through a mechanical drill, a chemical etching process, or a laser punch. Typically, the vias are 11-22 mil size. Further, any one of known printing methods is then utilized to make electrically conductive the vias thus formed. Examples of such printing methods include crossed conductive traces or filling a via sufficiently to connect to an underlying conductor/trace, and dispensing a conductive material such as paste or ink to create a partially or completely filled via. The latter is sufficient in two metal layer structures. However, that method has limited or no application in multi-layer (three, or more, metal layers). The vias are then, at step 510, de-smeared and cleaned.
At step 515, copper is deposited in an electroless deposition process and baked to cure. For the case where the device is a two metal layer device, the metal layers are connected and then the metal is baked. At step 520, copper plating is provided through an electrolytic plating process. For a two layer device, both sides of the substrate are copper plated. Some devices will be used in certain applications that will require a relatively thicker layer of copper. For example, some applications will require thicknesses of approximately 18 μm, 35 μm, or 75 μm. To achieve such thicknesses, industry standard is to use a starting copper thickness or apply, respectively, one-half an ounce, one ounce, or two ounces of copper.
Next, at step 525, a subtractive portion of the known process begins. Specifically, photolithography patterns are created on both metal layers using resistive material. At step 530, the copper layers are subtractively etched along the patterns. At step 535, remaining photoresist material is removed. This stripping step may require a pH adjustment. Most photoresist removers or stripping agents are basic in nature, i.e., have a pH greater than 7. These photoresist removers or stripping agents can require that the resultant materials on the substrate are further treated with chemistry to neutralize the pH. Thus, for example, if the surface were left with a basic pH, then a mild acid neutralization process may be used.
Step 540, a post-resist stripping and cleaning process step, is followed by lamination step 545. Specifically, a covering material is laminated into place over the substrate. Then, at step 550, any needed finish metal is applied along with laminate stiffeners. The finish metal—metal applied to the copper interconnect for next level assembly or capping of the copper interconnect to prevent oxidation—may be applied through any conventional process, such as, for example, by way of an organic surface protectant (OSP) process, a tinning process, or by way of a hot air solder level (HASL) process. The laminate stiffeners are used to support the substrate. They are typically placed on the backside of the substrate where one would join components to the active side of the substrate metal.
Finally, at step 555, the panel is singulated and required relief and openings are created. Singulation is the process of removing the active circuit from the substrate panel from which it is built. Often multiple circuits can be built in a single panel and they need to be de-panelized.
Although circuits with three, or more layers are produced, most flexible printed circuits include either one metal layer (1ML) or two metal layers (2ML). Most printed circuits that include electrically conductive traces that have been printed to a substrate have an electrical conductivity substantially less than that of copper, e.g., one half to one third the electrical conductivity of copper. Best-in-class flexible printed circuits claim up to one-half the electrical conductivity of copper.
Lower cost and/or large area electric circuits, with electrical performance equivalent to existing commercially available products are desired. These circuits include low cost, high volumes applications, e.g., RFID, smart labling, and sensor patches. As well, these circuits include large area circuits, e.g., lighting, display, and antenna or sensor arrays. Drop-on-demand, screen/stencil, gravure, and other like methods have been developed, utilized, or optimized to satisfy the need for low cost, large area printed electric interconnect, circuits and systems. These printing methods are compatible with producing either rigid or flexible electrical interconnect systems. However, due to limitations of the electrical properties of the materials used in these printed circuits, electrical performance parity with circuits fabricated using conventional methods and materials has not been achieved.
What is desired are improved interconnect devices, such as flexible printed circuits, and methods of fabricating the same. Such improved interconnect devices would include electrical interconnections having electrical conductivity greater than half that of copper. Such improved methods would desirably address the waste inherent in known methods as well as the adverse environmental impact of known methods.
An embodiment of the system provides an interconnect device that includes a substrate having at least one via therethrough, a patterned conductive seed layer printed on opposing sides of the substrate, a portion of the patterned conductive seed layer extending into the at least one via, and a primary conductor layer joined to the patterned conductive seed layer and extending into the at least one via.
An embodiment provides a method for fabricating an interconnect device. The method includes the sequential steps of providing a substrate, then forming vias through the substrate, then printing a patterned conductive seed layer onto the substrate, and then joining a primary conductor layer to the substrate.
A further embodiment provides an RF antenna that includes a receiver coil. The receiver coil includes a substrate having at least one via therethrough, a patterned conductive seed layer printed on opposing sides of the substrate, a portion of the patterned conductive seed layer extending into the at least one via, and a primary conductor layer joined to the patterned conductive seed layer and extending into the at least one via.
These and other features, aspects and advantages of the present invention may be further understood and/or illustrated when the following detailed description is considered along with the attached drawings.
a)-5(c) are cross-sectional views illustrating various metallized vias in accordance with one embodiment.
The present specification provides certain definitions and methods to better define the embodiments and aspects of the invention and to guide those of ordinary skill in the art in the practice of its fabrication. Provision, or lack of the provision, of a definition for a particular term or phrase is not meant to imply any particular importance, or lack thereof; rather, and unless otherwise noted, terms are to be understood according to conventional usage by those of ordinary skill in the relevant art.
Unless defined otherwise, technical and scientific terms used herein have the same meaning as is commonly understood by one of skill in the art to which this invention belongs. The terms “first”, “second”, and the like, as used herein do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. Also, the terms “a” and “an” do not denote a limitation of quantity, but rather denote the presence of at least one of the referenced item, and the terms “front”, “back”, “bottom”, and/or “top”, unless otherwise noted, are merely used for convenience of description, and are not limited to any one position or spatial orientation. If ranges are disclosed, the endpoints of all ranges directed to the same component or property are inclusive and independently combinable (e.g., ranges of “up to about 25 wt. %, or, more specifically, about 5 wt. % to about 20 wt. %,” is inclusive of the endpoints and all intermediate values of the ranges of “about 5 wt. % to about 25 wt. %,” etc.).
The modifier “about” used in connection with a quantity is inclusive of the stated value and has the meaning dictated by the context (e.g., includes the degree of error associated with measurement of the particular quantity). Reference throughout the specification to “one embodiment”, “another embodiment”, “an embodiment”, and so forth, means that a particular element (e.g., feature, structure, and/or characteristic) described in connection with the embodiment is included in at least one embodiment described herein, and may or may not be present in other embodiments. In addition, it is to be understood that the described inventive features may be combined in any suitable manner in the various embodiments.
As illustrated in
As more particularly illustrated in
Vias 12 may then be formed in the substrate 10. The vias 12 may be formed through any known conventional methodology, such as, for example, mechanically (mechanical drill or router or punch tools), chemically (etchant), or electrically (laser). Importantly, the chosen via construction method needs to be compatible with two, or more, metal layer interconnect structures. Further, the via construction method chosen should support smaller diameter vias than the print-dispense/fill via construction method. Smaller vias and land pads translate to finer interconnect features, e.g., conductor width and spacing between conductors. In addition, the print and plate vias 12 can be filled or open. Vias created with a print-dispense/fill via construction can only be created filled.
Additionally, fiducial marks 14 may be placed on the substrate 10. The fiducial marks 14 are used to ensure that the metal, to be later positioned on the substrate, is positioned in the proper location.
The substrate 10 is then cleaned with a solvent, acid, base, or plasma. This is done to ensure good adherence of a seed layer. As shown in
The via portions 16 are positioned in the vias 12. The via portions 16 may be positioned such that they adhere to walls 13 of the vias (
The patterned conductive seed layer may be applied through numerous known application processes, such as, for example, screen printing, dispensing, flexographic printing, gravure printing, and inkjet printing. The typical layer thicknesses can range from about 0.1 μm to about 5 μm. Of importance is the achievement of desired electrical performance and/or mechanical reliability. To achieve the former, one needs materials with superior electrical conductivity, compared to what is widely used in printing today. With respect to the latter, one needs sufficient adhesion and thickness to maintain the integrity of the interconnect during stress within the use environment, for example twisting, bending, etc. Typical screen printing results in thicknesses between 5 and 20 μm, rotary printing results in a thickness of about 2 μm, and gravure and inkjet printing results in thicknesses between about 0.2 to 2 μm. The thickness ranges depend in part on the viscosity and composition of the materials used and in part on the application process chosen for the application of the materials.
As shown in
a)-5(c) illustrate three types of vias 12, in accordance with an embodiment of the invention. As shown, the vias 12 are filled with an electrically conductive material. Specifically,
Finally, a cover layer 26 is applied to protect the electrically conductive metal traces and to serve as a mask for any required second level assembly operations. Openings in the cover layer 26 are pre-routed, punched or laser profiled, and then aligned to the substrate and laminated thereto. Any needed finish metal can be applied in panel format prior to final excising or routing. Specifically, circuits may be processed in a panel, usually with multiple circuits per panel. While in panel form it is easier to metalize 10 pads with the desired pad metal, prior to removal of the buses (if electroplating is required) and/or singulation. Finish metals may be applied by, for example, a tin process, an electroless nickel immersion gold process (ENIG), an electroless nickel immersion palladium immersion gold process (ENIPIG), an organic surface protectant process (OSP) or any other non-electrolytic materials process.
An electrolytic plating step is then performed at step 110. The electrolytic plating step is required to ensure that the finished product, for example, an MRI receiver coil, has a sufficient quality, or Q value. To have a sufficiently robust Q value requires a metallization process that will apply the conductor material to affect high conductivity. In the case of copper, the thickness of the conductor would need to be relatively thick. By relatively thick is meant at a thickness greater than is currently practical by use of typical materials used in printing methods. For MR applications the typical thickness range for received coils would be 10 μm-80 μm. The thickness of the seed ink or paste conductor will impact the required amount of bulk copper. The thickness of the copper plating depends on the amount of copper plating used. To obtain a thickness of copper in the range of from 10 μm to 80 μm, one-half to two ounces of copper will be necessary in the plating process.
At step 115, bussing structures are removed, or de-bussed. These portions are not required for the proper working of the finished device. Further, their continued presence within the finished device may lead to those portions acting as antennas, especially in applications at high frequencies, ultimately leading to a deteriorated performance of product.
A covering is provided at step 120 and laminated onto the substrate. The covering may have had openings pre-formed therein. The laminated covering may be used as a substrate for a second layer of metallization, as well as a protective covering for the copper metallization laid down on the substrate.
Finish metal may be applied at step 125. The finish metal is applied to the IO pads to make them ready for joining to components or other circuit elements. The finish metal may be applied through tin, OSP, ENIG, or other like processes to prepare the IO pads for soldering. Finally, at step 130 the circuit is singulated to remove it from the multiple circuits that may be in the process panel.
The print and plate process described with reference to
While the invention has been described in detail in connection with only a limited number of embodiments, it should be readily understood that the invention is not limited to such disclosed embodiments. Rather, the invention can be modified to incorporate any number of variations, alterations, substitutions or equivalent arrangements not heretofore described, but which are commensurate with the spirit and scope of the invention. For example, while embodiments have been described in terms that may initially connote singularity, it should be appreciated that multiple components may be utilized. Additionally, while various embodiments of the invention have been described, it is to be understood that aspects of the invention may include only some of the described embodiments. Accordingly, the invention is not to be seen as limited by the foregoing description, but is only limited by the scope of the appended claims.
