The present application relates to manufacturing of semiconductor integrated circuits. More particularly, it relates to method of forming metal lines of an interconnect structure with line width profile and the structure formed thereby.
A semiconductor integrated circuit such as a semiconductor chip generally includes a front-end-of-line (FEOL) region, where active device such as transistors are formed, and a back-end-of-line (BEOL) region, where power supplies and interconnect are provided to the active devices formed in the FEOL region. In instances, a middle-of-line (MOL) region may exist between the FEOL region and the BEOL region where contacts and/or local interconnects may be formed for the active devices in the FEOL region.
The BEOL region generally includes multiple metal lines such as metal level-1 (M1), metal level-2 (M2), . . . metal level-N (MN) and different metal levels may be inter-connected through various types of via structures between the metal lines. Generally, performance of lower metal levels such as, for example, M1 and M2 with a tight pitch such as a sub-36 nm pitch are resistance-dominated. On the other hand, upper metal lines such as those metal levels with a pitch equal to or larger than 80 nm are capacitance-dominated. In other words, resistance of the upper metal lines are usually not a concern, but it is the capacitance of those upper metal lines that often affect the performance of the semiconductor chip. Therefore, there is a need to improve the device performance by reducing the capacitance of upper metal lines.
Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a metal level that includes a metal line, the metal line includes a bottom section having a first width, a middle section having a second width, and a top section having a third width, where the second width of the middle section is narrower than the first width of the bottom section and is narrower than the third width of the top section.
In one embodiment, the semiconductor structure further includes a liner conformally lining sidewalls of the top section, sidewalls of the middle section, sidewalls of the bottom section, and a bottom surface of the bottom section.
In one embodiment, the metal line includes copper and the liner includes titanium-nitride (TiN).
In another embodiment, the bottom section is embedded in a first dielectric layer, the middle section is embedded in a second dielectric layer, and the top section is embedded in a third dielectric layer, where the second dielectric layer has a material composition that is different from material compositions of the first and the third dielectric layer.
In yet another embodiment, the second dielectric layer has an etch selectivity that is different from etch selectivity of the first and the third dielectric layer.
According to one embodiment, the metal line is a first metal line, and the semiconductor structure further includes a second metal line parallel to the first metal line, where a first horizontal distance between the middle section of the first metal line and a middle section of the second meta line is larger than a second horizontal distance between the top section of the first metal line and a top section of the second metal line.
In one embodiment, the second metal line, from a top to a bottom thereof, has a substantially uniform width.
In another embodiment, the middle section of the second metal line is narrower than the top section of the second metal line.
Embodiments of present invention further provide an interconnect structure. The interconnect structure includes a metal level including a metal line, the metal line includes a first section having a first width and a second section having a second width, the second section being directly on top of the first section; and a liner lining a bottom surface and sidewalls of the first section and lining sidewalls of the second section, where the first width of the first section is narrower than the second width of the second section.
In one embodiment, the metal line is a first metal line, the interconnect structure further includes a second metal line parallel to the first metal line, the second metal line having a first section and a second section, the second section of the second metal line being directly on top of the first section of the second metal line, where a first horizontal distance between the first section of the first metal line and the first section of the second meta line is larger than a second horizontal distance between the second section of the first metal line and the second section of the second metal line.
Embodiments of present invention provide a method of forming a semiconductor structure. The method includes forming a first dielectric layer on top of a supporting structure; forming a second dielectric layer on top of the first dielectric layer; forming a third dielectric layer on top of the second dielectric; creating an opening that has a first area in the first dielectric layer, a second area in the second dielectric layer, and a third area in the third dielectric layer; selectively etching the first and the third dielectric layer, relative to the second dielectric layer, thereby horizontally expanding the first area and the third area of the opening respectively to create an expanded opening; and filling the expanded opening with a conductive material to form a metal line, where the metal line has a bottom section with a first width, a middle section with a second width, and a top section with a third width, the second width being smaller than the first width and the third width.
The present invention will be understood and appreciated more fully from the following detailed description of embodiments of present invention, taken in conjunction with accompanying drawings of which:
It will be appreciated that for simplicity and clarity purpose, elements shown in the drawings have not necessarily been drawn to scale. Further, and if applicable, in various functional block diagrams, two connected devices and/or elements may not necessarily be illustrated as being connected. In some other instances, grouping of certain elements in a functional block diagram may be solely for the purpose of description and may not necessarily imply that they are in a single physical entity, or they are embodied in a single physical entity.
In the below detailed description and the accompanying drawings, it is to be understood that various layers, structures, and regions shown in the drawings are both demonstrative and schematic illustrations thereof that are not drawn to scale. In addition, for the ease of explanation, one or more layers, structures, and regions of a type commonly used to form semiconductor devices or structures may not be explicitly shown in a given illustration or drawing. This does not imply that any layers, structures, and regions not explicitly shown are omitted from the actual semiconductor structures. Furthermore, it is to be understood that the embodiments discussed herein are not limited to the particular materials, features, and processing steps shown and described herein. In particular, with respect to semiconductor processing steps, it is to be emphasized that the descriptions provided herein are not intended to encompass all of the processing steps that may be required to form a functional semiconductor integrated circuit device. Rather, certain processing steps that are commonly used in forming semiconductor devices, such as, for example, wet cleaning and annealing steps, are purposefully not described herein for economy of description.
It is to be understood that the terms “about” or “substantially” as used herein with regard to thicknesses, widths, percentages, ranges, etc., are meant to denote being close or approximate to, but not exactly. For example, the term “about” or “substantially” as used herein implies that a small margin of error may be present such as, by way of example only, 1% or less than the stated amount. Likewise, the terms “on”, “over”, or “on top of” that are used herein to describe a positional relationship between two layers or structures are intended to be broadly construed and should not be interpreted as precluding the presence of one or more intervening layers or structures.
Moreover, although various reference numerals may be used across different drawings, the same or similar reference numbers are used throughout the drawings to denote the same or similar features, elements, or structures, and thus detailed explanations of the same or similar features, elements, or structures may not be repeated for each of the drawings for economy of description. Labelling for the same or similar elements in some drawings may be omitted as well in order not to overcrowd the drawings.
The first, second, and third dielectric layers 121, 122, and 123 may be made of, for example, silicon-oxide (SiO2), silicon-nitride (SiN), silicoboron-carbonitride (SiBCN), silicon-oxycarbonitride (SiOCN), or other low-k dielectric materials. More particularly, the second dielectric layer 122 may have a material composition that is different from material composition of the first dielectric layer 121 and the third dielectric layer 123 such that they have different etch selectivity or exhibit different etch selectivity during a selective etch process. For example, the second dielectric layer 122 may be SiN, and the first and the third dielectric layer 121 and 123 may be SiBCN. The SiBCN material of the first and the third dielectric layer 121 and 123 may be etched selective to the SiN material of the second dielectric layer 122. Further for example, the second dielectric layer 122 may be SiN and the first and the third dielectric layer may be SiO2. The first, the second, and the third dielectric layers 121, 122, and 123 may be formed through deposition by a physical-vapor-deposition (PVD) process, a chemical-vapor-deposition (CVD) process, an atomic-layer-deposition (ALD) process, or other currently existing or future developed processes.
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Similarly, a first and a third area of the second opening 132 may be horizontally expanded to form the expanded second opening 142 having an expanded first area 1421, a second area 1422, and an expanded third area 1423.
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Similarly, a second liner 152 may be conformally formed to line the expanded second opening 142 at sidewalls of the first, the second, and the third dielectric layer 121, 122, and 123 and the exposed top surface of the supporting structure 110.
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In one embodiment, the conductive material may include Co, Ru, tungsten (W), copper (Cu) or other suitable materials including alloyed material such as CoSi and CuAl. The conductive material may first be deposited into the expanded first and second openings 141 and 142 through, for example, a PVD process, a CVD process, an ALD process or a combination of the processes. Embodiments of present invention further provide subjecting the deposited conductive material to a metal reflow process to cause the conductive material to, for example, horizontally expand to substantially fill up the expanded first area 1411 of the expanded first opening 141, thereby forming a bottom section 1611 of the first metal line 161. The filled conductive material may also form a middle section 1612 and a top section 1613 of the first metal line 161.
Similarly, filling the conductive material in the expanded second opening 142, and subjecting the conductive material to a metal reflow process, may form the second metal line 162 that has a bottom section 1621, a middle section 1622, and a top section 1623.
In one embodiment, the bottom section 1611 of the first metal line 161 may have a first width, the middle section 1612 may have a second width, and the top section 1613 may have a third width and the second width may be narrower than the first width and the third width. For example, the bottom section and the top section may have a width W1 and the middle section may have a width W2. W2 may be smaller than W1 and, in one embodiment, W2 may be between about 25% and about 50% of W1. In another embodiment, the first width of the bottom section may be smaller than the third width of the top section due to the nature of etch process and/or difference in etch selectivity in material between the first and the third dielectric layer.
In another embodiment, the middle section 1612 of the first metal line 161 and the middle section 1622 of the second metal line 162 may be separated by a first horizontal distance D1. The top section 1613 of the first metal line 161 and the top section 1623 of the second metal line 162 may be separated by a second horizontal distance D2. D1 is larger than D2 and, in one embodiment, D1 may be between about 120% and about 140% of D2. By increasing the horizontal distance between the middle sections of the first and the second metal line 161 and 162, embodiments of present invention may be able to reduce a capacitance formed by the first and the second metal line 161 and 162 by up to 50%, depending upon a ratio of thicknesses of the middle section 1612 versus the bottom section 1611 and the top section 1613. In the meantime, a reduction in width of the middle section 1612 may increase resistance of the first metal line 161 but according to embodiments of present invention the increase would be acceptable when the reduction, expressed by the ratio W2/W1, is within 25% to 50%.
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The sidewall spacers 241 and 242 may be made of a dielectric material, which may have a material composition that is different from a material composition of the second dielectric layer 222 and may be different from a material composition of the third dielectric layer 223. The difference in material compositions of the sidewall spacers 241 and 242 and the second and the third dielectric layers 222 and 223 enables a selective etch process that may be strategically applied to create openings for forming metal lines. The sidewall spacer 241 may have a sufficient thickness such that they form or create a modified first opening 251 that has a reduced width than the first opening 231. Similarly, the sidewall spacer 242 may have a sufficient thickness as well, thereby forming or creating a modified second opening 252 that has a reduced width than the second opening 232 as well.
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In one embodiment, for example, the second section 2613 of the first metal line 261 may have a first width W1 and the first section 2612 of the first metal line 261 may have a second width W2. W2 may be smaller than W1 and in one embodiment may be between about 25% and about 50% of W1. The third section 2611 and 2621 may have a third width that is wider than the first width W1 of the first section 2612 and 2622 and are in contact with the first section 2612 and 2622 through the first and the second liner 291 and 292 respectively.
The first section 2612 of the first metal line 261 may be separated from a nearby metal line, such as the first section 2622 of the second metal line 262, by a first horizontal distance D1. The second section 2613 of the first metal line 261 may be separated from this nearby metal line, such as the second section 2623 of the second metal line 262, by a second horizontal distance D2. D1 may be larger than D2 and in one embodiment may be between about 120% and about 140% of D2. Overall, the first metal line 261 and the second metal line 262 may be centrally separated by a distance DO, here distance DO refers to a distance between a mid-point of the width of the top section 2613 of the first metal line 261 and a mid-point of the width of the top section 2623 of the second metal line 262, and distance DO may be at least 10 nm. The increase in horizontal distance D1, compared with D2, helps reduce a capacitance which otherwise would be formed by the first metal line 261 and the nearby metal line. In one embodiment, the nearby metal line may be the second metal line 262. In another embodiment, the nearby metal line may be a metal line having a substantially uniform width albeit a slightly slanted sidewall, such as a metal line 563 illustrated in
The first metal level 560 may include a first and a second dielectric layer 521 and 522, with a first, a second, and a third metal lines 561, 562, and 563 formed therein. The second metal level 580 may include at least one metal line 581 formed in a dielectric layer 541. In one embodiment, the metal line 581 in the second metal level 580 may be connected to a metal line such as the second metal line 562 in the first metal level 560 through a conductive via 570. The conductive via 570 may be formed in the ILD layer 531.
It is to be understood that the exemplary methods discussed herein may be readily incorporated with other semiconductor processing flows, semiconductor devices, and integrated circuits with various analog and digital circuitry or mixed-signal circuitry. In particular, integrated circuit dies can be fabricated with various devices such as field-effect transistors, bipolar transistors, metal-oxide-semiconductor transistors, diodes, capacitors, inductors, etc. An integrated circuit in accordance with the present invention can be employed in applications, hardware, and/or electronic systems. Suitable hardware and systems for implementing the invention may include, but are not limited to, personal computers, communication networks, electronic commerce systems, portable communications devices (e.g., cell phones), solid-state media storage devices, functional circuitry, etc. Systems and hardware incorporating such integrated circuits are considered part of the embodiments described herein. Given the teachings of the invention provided herein, one of ordinary skill in the art will be able to contemplate other implementations and applications of the techniques of the invention.
Accordingly, at least portions of one or more of the semiconductor structures described herein may be implemented in integrated circuits. The resulting integrated circuit chips may be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip may be mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other high-level carrier) or in a multichip package (such as a ceramic carrier that has surface interconnections and/or buried interconnections). In any case the chip may then be integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either an intermediate product, such as a motherboard, or an end product. The end product may be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
The descriptions of various embodiments of present invention have been presented for the purposes of illustration and they are not intended to be exhaustive and present invention are not limited to the embodiments disclosed. The terminology used herein was chosen to best explain the principles of the embodiments, practical application or technical improvement over technologies found in the marketplace, and to enable others of ordinary skill in the art to understand the embodiments disclosed herein. Many modifications, substitutions, changes, and equivalents will now occur to those of ordinary skill in the art. Such changes, modification, and/or alternative embodiments may be made without departing from the spirit of present invention and are hereby all contemplated and considered within the scope of present invention. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the spirit of the invention.