Claims
- 1. A ferroelectric memory cell, comprising:
a control gate formed overlying a ferroelectric layer; a first source/drain region having a first conductivity type; a second source/drain region having the first conductivity type; a channel region interposed between the first and second source/drain regions and having the first conductivity type; and a well coupled to the second source/drain region and having a second conductivity type, wherein the second conductivity type is opposite the first conductivity type and wherein the well is isolated from the control gate.
- 2. The ferroelectric memory cell of claim 1, further comprising:
a gate dielectric layer interposed between the channel region and the ferroelectric layer; and a floating gate interposed between the gate dielectric layer and the ferroelectric layer.
- 3. The ferroelectric memory cell of claim 2, wherein the floating gate comprises a conductive material.
- 4. The ferroelectric memory cell of claim 3, wherein the conductive material includes at least one material selected from the group consisting of conductively-doped polysilicon, metal silicides, metals and metal alloys.
- 5. The ferroelectric memory cell of claim 4, wherein the floating gate comprises a metal layer overlying a conductively-doped polysilicon layer.
- 6. The ferroelectric memory cell of claim 1, wherein the ferroelectric layer comprises a material selected from the group consisting of strontium bismuth tantalite, lead zirconium titanate, lanthanum-doped lead zirconium titanate, lithium niobate and metal oxides having a perovskite crystalline structure.
- 7. The ferroelectric memory cell of claim 1, further comprising:
a gate dielectric layer interposed between the channel region and the ferroelectric layer; wherein the ferroelectric layer is overlying and adjoining the gate dielectric layer.
- 8. The ferroelectric memory cell of claim 1, wherein the ferroelectric layer is overlying and adjoining the channel region.
- 9. A ferroelectric memory cell, comprising:
a control gate formed overlying a ferroelectric layer; a first source/drain region having a first conductivity type; a second source/drain region having the first conductivity type; a channel region interposed between the first and second source/drain regions and having the first conductivity type; and a well having a second conductivity type formed in the second source/drain region, wherein the second conductivity type is opposite the first conductivity type and wherein the well is isolated from the control gate.
- 10. The ferroelectric memory cell of claim 9, further comprising:
a gate dielectric layer interposed between the channel region and the ferroelectric layer; and a conductive floating gate interposed between the gate dielectric layer and the ferroelectric layer.
- 11. The ferroelectric memory cell of claim 9, wherein the ferroelectric layer comprises a material selected from the group consisting of strontium bismuth tantalite, lead zirconium titanate, lanthanum-doped lead zirconium titanate, lithium niobate and metal oxides having a perovskite crystalline structure.
- 12. The ferroelectric memory cell of claim 9, further comprising:
a gate dielectric layer interposed between the channel region and the ferroelectric layer; wherein the ferroelectric layer is overlying and adjoining the gate dielectric layer.
- 13. The ferroelectric memory cell of claim 9, wherein the ferroelectric layer is overlying and adjoining the channel region.
- 14. The ferroelectric memory cell of claim 9, wherein the ferroelectric memory cell is formed on a silicon-on-insulator substrate.
- 15. The ferroelectric memory cell of claim 9, wherein the well is interposed between the second source/drain region and a bit line coupled to the memory cell.
- 16. A memory cell, comprising:
a conductively-doped polysilicon layer having a first conductivity type formed overlying a substrate having the first conductivity type; a ferroelectric transistor formed overlying the polysilicon layer, wherein the transistor has a control gate, a ferroelectric layer interposed between the polysilicon layer and the control gate, a first source/drain region having the first conductivity type formed in the polysilicon layer, a second source/drain region having the first conductivity type formed in the polysilicon layer, and a channel having the first conductivity type formed in the polysilicon layer interposed between the first and second source/drain regions; and a well region having a second conductivity type opposite the first conductivity type, wherein the well region is interposed between the second source/drain region and the substrate.
- 17. The memory cell of claim 16, wherein the well region is formed in the substrate and is coupled to the second source/drain region by a conductive plug.
- 18. The ferroelectric memory cell of claim 16, further comprising:
a gate dielectric layer interposed between the conductively-doped polysilicon layer and the ferroelectric layer; and a floating gate interposed between the gate dielectric layer and the ferroelectric layer.
- 19. The ferroelectric memory cell of claim 18, wherein the floating gate comprises a conductive material.
- 20. The ferroelectric memory cell of claim 16, further comprising:
a gate dielectric layer interposed between the conductively-doped polysilicon layer and the ferroelectric layer; wherein the ferroelectric layer is overlying and adjoining the gate dielectric layer.
- 21. The ferroelectric memory cell of claim 16, wherein the ferroelectric layer is overlying and adjoining the conductively-doped polysilicon layer.
- 22. A memory cell, comprising:
a conductively-doped polysilicon layer having a first conductivity type formed overlying a substrate having the first conductivity type; a ferroelectric transistor formed overlying the polysilicon layer, wherein the transistor has a control gate coupled to a word line, a ferroelectric layer interposed between the polysilicon layer and the control gate, a first source/drain region having the first conductivity type formed in the polysilicon layer and coupled to a program line, a second source/drain region having the first conductivity type formed in the polysilicon layer, and a channel having the first conductivity type formed in the polysilicon layer interposed between the first and second source/drain regions; and a well region having a second conductivity type opposite the first conductivity type, wherein the well region is formed in the substrate and wherein the well region is interposed between the second source/drain region and a bit line.
- 23. A memory cell, comprising:
a ferroelectric layer formed overlying a well region having a first conductivity type, wherein the well region is formed in a substrate having a second conductivity type opposite the first conductivity type; a control gate formed overlying the ferroelectric layer and coupled to a word line; a first source/drain region having the first conductivity type formed in the well region and coupled to a program line; a second source/drain region having the first conductivity type formed in the well region; a channel region having the first conductivity type formed in the well region and interposed between the first and second source/drain regions; and a diode interposed between the second source/drain region and a bit line.
- 24. The memory cell of claim 23, wherein the diode is a well region having the second conductivity type formed in the second source/drain region.
- 25. A memory cell, comprising:
a ferroelectric layer formed overlying a first well region having a first conductivity type, wherein the first well region is formed in a substrate having a second conductivity type opposite the first conductivity type; a control gate formed overlying the ferroelectric layer and coupled to a word line; a first source/drain region having the first conductivity type formed in the first well region and coupled to a program line; a second source/drain region having the first conductivity type formed in the first well region; a channel region having the first conductivity type formed in the first well region and interposed between the first and second source/drain regions; and a second well region having the second conductivity type formed in the first well region and coupled to the second source/drain region, wherein the second well region is isolated from the control gate.
- 26. A memory cell, comprising:
a ferroelectric layer formed overlying a well region having a first conductivity type, wherein the well region is formed overlying a substrate and wherein a layer of dielectric material is interposed between the well region and the substrate; a control gate formed overlying the ferroelectric layer and coupled to a word line; a first source/drain region having the first conductivity type formed in the well region and coupled to a program line; a second source/drain region having the first conductivity type formed in the well region; a channel region having the first conductivity type formed in the well region and interposed between the first and second source/drain regions; and a diode interposed between the second source/drain region and a bit line.
- 27. The memory cell of claim 26, wherein the ferroelectric layer is formed overlying and adjoining the well region having the first conductivity type and wherein the diode is a well region having the second conductivity type formed in the second source/drain region.
- 28. A memory cell, comprising:
a ferroelectric layer formed overlying a first well region having a first conductivity type, wherein the first well region is formed overlying a substrate and wherein a layer of dielectric material is interposed between the first well region and the substrate; a control gate formed overlying the ferroelectric layer and coupled to a word line; a first source/drain region having the first conductivity type formed in the first well region and coupled to a program line; a second source/drain region having the first conductivity type formed in the first well region; a channel region having the first conductivity type formed in the first well region and interposed between the first and second source/drain regions; and a second well region having the second conductivity type formed in the first well region and coupled to the second source/drain region, wherein the second well region is isolated from the control gate.
- 29. A memory device, comprising:
an array of memory cells, wherein each memory cell comprises:
a control gate formed overlying a ferroelectric layer; a first source/drain region having a first conductivity type; a second source/drain region having the first conductivity type; a channel region interposed between the first and second source/drain regions and having the first conductivity type; and a well coupled to the second source/drain region and having a second conductivity type, wherein the second conductivity type is opposite the first conductivity type and wherein the well is isolated from the control gate; a plurality of word lines coupled to rows of memory cells of the array of memory cells through their control gates; a plurality of program lines coupled to columns of memory cells of the array of memory cells through their first source/drain regions; a plurality of bit lines coupled to columns of memory cells of the array of memory cells through their wells; a row decoder coupled to the array of memory cells; and a column decoder coupled to the array of memory cells.
- 30. A memory device, comprising:
an array of memory cells, wherein each memory cell comprises:
a control gate formed overlying a ferroelectric layer; a first source/drain region having a first conductivity type; a second source/drain region having the first conductivity type; a channel region interposed between the first and second source/drain regions and having the first conductivity type; and a well having a second conductivity type formed in the second source/drain region, wherein the second conductivity type is opposite the first conductivity type and wherein the well is isolated from the control gate; a plurality of word lines coupled to rows of memory cells of the array of memory cells through their control gates; a plurality of program lines coupled to columns of memory cells of the array of memory cells through their first source/drain regions; a plurality of bit lines coupled to columns of memory cells of the array of memory cells through their wells; a row decoder coupled to the array of memory cells; and a column decoder coupled to the array of memory cells.
- 31. An electronic system, comprising:
a processor; and a memory device coupled to the processor, wherein the memory device comprises:
an array of memory cells, wherein each memory cell comprises:
a control gate formed overlying a ferroelectric layer; a first source/drain region having a first conductivity type; a second source/drain region having the first conductivity type; a channel region interposed between the first and second source/drain regions and having the first conductivity type; and a well coupled to the second source/drain region and having a second conductivity type, wherein the second conductivity type is opposite the first conductivity type and wherein the well is isolated from the control gate; a plurality of word lines coupled to rows of memory cells of the array of memory cells through their control gates; a plurality of program lines coupled to columns of memory cells of the array of memory cells through their first source/drain regions; a plurality of bit lines coupled to columns of memory cells of the array of memory cells through their wells; a row decoder coupled to the array of memory cells; and a column decoder coupled to the array of memory cells.
RELATED APPLICATIONS
[0001] This is a divisional application of U.S. patent application Ser. No. 09/652,557 (allowed), filed Aug. 31, 2000, titled “JUNCTION-ISOLATED DEPLETION MODE FERROELECTRIC MEMORY DEVICES, USES AND OPERATION,” which is commonly assigned, the entire contents of which are incorporated herein by reference.
[0002] This application is further related to U.S. patent application Ser. No. 09/653,074 filed Aug. 31, 2000 and titled, “Array Architecture for Depletion Mode Ferroelectric Memory Devices,” which is commonly assigned.
Divisions (1)
|
Number |
Date |
Country |
Parent |
09652557 |
Aug 2000 |
US |
Child |
10306592 |
Nov 2002 |
US |