This application claims the priority of Chinese patent application number 201210264945.5, filed on Jul. 27, 2012, the entire contents of which are incorporated herein by reference.
The present invention relates in general to laterally diffused metal oxide semiconductor (LDMOS) devices, and more particularly, to an LDMOS device with a step-like drift region and a fabrication method thereof.
Laterally diffused metal oxide semiconductor (LDMOS) transistors are often used as power switch devices.
a is a schematic illustration of an existing n-type LDMOS device. The device includes a p-type doped region 11 and an n-type drift region 12, laterally neighboring each other and both formed in a p-type substrate (or epitaxial layer) 10. The n-type drift region 12 has a planar top surface. A heavily doped n-type source region 19 is formed in a central portion of the p-type doped region 11. A gate oxide layer 13 has its one end on the n-type drift region 12, the other end on the heavily doped n-type source region 19, and the rest portion on the p-type doped region 11. A gate 14 is located on the gate oxide layer 13. Sidewalls 15 are formed on both sides of the gate oxide layer 13 and the gate 14. A heavily doped n-type drain region 20 is formed at one end of the n-type drift region 12 farther from the p-type doped region 11. A p-type heavily doped pick-up region 21 is formed at one end of the p-type doped region 11 farther from the n-type drift region 12. A channel of the LDMOS device is formed in a portion of the p-type doped region 11 under the gate oxide layer 13. A p-type LDMOS device has a similar architecture to the n-type LDMOS device discussed above expect that all components of the p-type LDMOS device have conductivity types opposite to their counterparts in the n-type LDMOS device.
When a high voltage is applied to the drain region 20 of the existing n-type LDMOS device shown in
The above-mentioned device is a non-channel-isolated LDMOS transistor, which may be modified into a channel-isolated n-type LDMOS transistor by including an n-type well in the p-type substrate 10, encircling both the p-type doped region 11 and the n-type drift region 12. Similarly, a channel-isolated p-type LDMOS device can be obtained by converting the conductivity types of all components of the channel-isolated n-type LDMOS device to respective opposite types of conductivity.
In order to reduce power consumption, an LDMOS device is typically required to have an on-resistance as low as possible. Thus, during the design of the device, it is contemplated to reduce the physical length of the drift region (i.e., the length A shown in
The present invention is directed to the provision of an LDMOS device with a completely novel structure, which is capable of having both a low on-resistance and a high breakdown voltage.
To achieve the above objective, the present invention provides an LDMOS device including: a substrate having a first type of conductivity; a drift region having a second type of conductivity and being formed in the substrate; a doped region having the first type of conductivity and being formed in the substrate, the doped region being located at a first end of the drift region and laterally adjacent to the drift region; and a heavily doped drain region having the second type of conductivity and being formed in the substrate, the heavily doped drain region being located at a second end of the drift region, wherein the drift region has a step-like top surface with at least two step portions, and wherein a height of the at least two step portions decreases progressively in a direction from the doped region to the drain region.
Optionally, the first and second types of conductivity are p-type and n-type, respectively, or n-type and p-type, respectively.
Optionally, an outer edge of a lowest step portion of the drift region is aligned with an inner side of the drain region, wherein a top surface of a highest step portion of the drift region is at a same level with a top surface of the drain region, and wherein a top surface of the lowest step portion of the drift region is at a same level with or at a higher level than a bottom surface of the drain region.
Optionally, an outer edge of a lowest step portion of the drift region is aligned with an outer side of the drain region, and wherein a top surface of the lowest step portion of the drift region is at a same level with a top surface of the drain region.
Optionally, the LDMOS device further includes: a gate oxide layer and a gate both on a top surface of the substrate, the gate oxide layer covering a portion of the drift region and a portion of the doped region; sidewalls on both sides of the gate oxide layer and the gate; and a heavily doped source region having the second type of conductivity and a heavily doped channel pick-up region having the first type of conductivity both formed in the doped region, the heavily doped channel pick-up region being located at an end of the source region farther from the drift region.
Optionally, a border line between the highest and the second highest step portions of the drift region may be aligned with, or a certain distance away from, an outer side face of the sidewall closer to the drift region.
Optionally, in the LDMOS device, a doping concentration of the drift region is proportional to a distance from a border line between a highest and a second highest step portions of the drift region to the drain region and is also proportional to a height difference between the highest and a lowest step portions of the drift region.
The present invention also provides a method of fabricating an LDMOS device, including the steps of: providing a substrate having a first type of conductivity; forming a drift region having a second type of conductivity in the substrate; forming a doped region having the first type of conductivity in the substrate, the doped region being located at a first end of the drift region and laterally adjacent to the drift region; and forming a heavily doped drain region having the second type of conductivity in the substrate, the heavily doped drain region being located at a second end of the drift region, wherein the drift region has a step-like top surface with at least two step portions, and wherein a height of the at least two step portions decreases progressively in a direction from the doped region to the drain region.
Optionally, the method may include the steps of: 1) forming, in a substrate having the first type of conductivity, a doped region having the first type of conductivity and a drift region having the second type of conductivity which are laterally adjacent to each other; 2) successively forming a gate oxide layer and a polysilicon gate on a top surface of the substrate, the gate oxide layer covering a portion of the drift region and a portion of the doped region; 3) performing at least one etching process on the drift region to make the drift region have a step-like top surface; 4) forming a heavily doped source region having the second type of conductivity in a central portion of the doped region; 5) forming a heavily doped drain region having the second type of conductivity at an end of the drift region farther from the gate oxide layer; and 6) forming a heavily doped channel pick-up region having the first type of conductivity at an end of the doped region farther from the gate oxide layer.
Optionally, in the method, the first and second types of conductivity are p-type and n-type, respectively, or n-type and p-type, respectively.
Optionally, in the step 1), multiple ion implantation and annealing processes may be carried out to create a dopant concentration gradient in the drift region decreasing from the top down.
Optionally, the method may further include forming a well having the second type of conductivity in the substrate before the step 1), and in the step 1), the doped region having the first type of conductivity and the drift region having the second type of conductivity are both formed in the well.
Optionally, the drift region may have a dopant concentration ranged from 1×1016 atoms/cm3 to 1×1018 atoms/cm3, and both the heavily doped source region and the heavily doped drain region have a dopant concentration of greater than 1×1020 atoms/cm3.
Optionally, the method may further include, between the steps 2) and 3), forming sidewalls on both sides of the gate oxide layer and the polysilicon gate.
Optionally, a border line between a highest and a second highest step portions of the drift region formed by the at least one etching process in the step 3) is aligned with an outer side face of the sidewall closer to the drift region.
Optionally, the method may further include, between the steps 3) and 4), forming sidewalls on both sides of the gate oxide layer and the polysilicon gate such that an outer side face of the sidewall closer to the drift region is aligned with, or a certain distance away from, a border line between a highest and a second highest step portions of the drift region.
As the step-like drift region of the LDMOS device of the present invention has a thickness progressively decreasing from the channel towards the drain region, the drift region is easier to be completely depleted and hence can withstand a higher breakdown voltage. Meanwhile, the progressively decreasing thickness also allows an increase of the doping concentration of the drift region, thereby greatly reducing its on-resistance. Thus, the LDMOS device of the present invention can have both a low on-resistance and a high breakdown voltage, and therefore has an improved performance compared with the existing device.
a shows a schematic illustration of a vertical cross section of an existing n-type LDMOS device.
b shows a diagram schematically illustrating the charge distribution in a depletion region of the LDMOS device of
a shows a schematic illustration of a vertical cross section of an n-type LDMOS device embodying the present invention.
b shows a diagram schematically illustrating the charge distribution in a depletion region of the LDMOS device of
a to 3f show schematic illustrations of device structures after steps of a method for fabricating an n-type LDMOS device (non-channel-isolated) in accordance with an embodiment of the present invention.
a and 4b show schematic illustrations of embodiments of step-like drift regions of LDMOS devices constructed in accordance with the present invention.
a schematically illustrates an LDMOS device with a step-like drift region embodying the present invention. It differs from an existing LDMOS device in that a drift region 12 of the LDMOS device of the present invention has a step-like top surface and a thickness progressively decreasing from a channel towards a drain region 12. Such design enables the drift region 12 to be completely depleted during the operation of the LDMOS device of the present invention. The above-mentioned channel refers to a portion of a p-type doped region 11 that is under and in close proximity to a gate oxide layer 13, as shown in
The LDMOS device shown in
Moreover, the above-mentioned non-channel-isolated n-type LDMOS device of
In one embodiment, as shown in
In one embodiment, with further reference to
Moreover, in specific embodiments of the present invention, the higher a doping concentration of the drift region 12, the greater the distance from the border line between the highest and the second highest step portions of the drift region 12 to the drain region 20 and the greater the difference between the greatest thickness T1 and the smallest thickness Tn of the drift region 12, and vice versa.
The progressively decreasing thickness from the channel towards the drain region of the step-like drift region of the LDMOS device of the present invention enables a portion of the drift region, which is more proximate to the channel and is hence easier to be depleted, to have a greater thickness and a portion, which is farther from the channel and is thus more difficult to be depleted, to have a smaller thickness. As such, regardless of how high the doping concentration of the drift region is, the drift region may be always completely depleted, as shown in
In one exemplary embodiment, the non-channel-isolated n-type LDMOS device shown in
Turning now to
In a second step, as shown in
In a third step, as shown in
In a fourth step, as shown in
In a fifth step, as shown in
In a sixth step, as shown in
With further reference to
After that, an ion implantation process is performed at an end of the n-type drift region 12 that is farther from the gate oxide layer 13 to form a heavily doped n-type drain region 20 therein.
Moreover, an ion implantation process is performed at an end of the p-type doped region 11 that is farther from the gate oxide layer 13 to form a heavily doped p-type channel pick-up region 21 therein.
Preferably, both the heavily doped source region 19 and the heavily doped drain region 20 have a dopant concentration of greater than 1×1020 atoms/cm3. Moreover, the heavily doped channel pick-up region 21 may have the same dopant concentration with the above two regions 19, 20.
The three etching processes in the above fourth to sixth steps of the method have shaped the top surface of the drift region into a step-like shape. However, the present invention is not limited to this. A step-like top surface with a different number of step portions may also be formed by using a different number of etching processes.
Although the sidewalls are formed in the third step before the fourth to sixth steps in this embodiment, the present invention may also be employed with the sidewalls formed after, or even among, the fourth to sixth steps.
As described above, each implantation process in the first step and the implantation process in the seventh step are both followed by an annealing process. Preferably, each annealing process in the first step is a high-temperature oven annealing process and the annealing process in the seventh step is a rapid thermal annealing (RTA) process.
In one embodiment, a non-channel-isolated p-type LDMOS device in accordance with the present invention is fabricated by using and forming components and implanting ions, with types of conductivity opposite to their counterparts in the method described above. In another embodiment, a channel-isolated p-type LDMOS device in accordance with the present invention is fabricated by forming an n-well (not shown) in a p-type substrate 10 by ion implantation before the first step of the method for fabricating the non-channel-isolated p-type LDMOS device in the previous embodiment, forming an n-type doped region 11 and a p-type drift region 12 neighboring each other both in the p-well, and following all subsequent steps of the method.
In yet another embodiment, a channel-isolated n-type LDMOS device in accordance with the present invention is fabricated by forming an n-well (not shown) in the p-type substrate 10 by ion implantation before the first step of the method for fabricating the non-channel-isolated n-type LDMOS device described above, forming the p-type doped region 11 and the n-type drift region 12 neighboring each other both in the n-well, and following all subsequent steps of the method. In still yet another embodiment, a channel-isolated p-type LDMOS device in accordance with the present invention is fabricated by using and forming components and implanting ions, with types of conductivity opposite to their counterparts in the method for fabricating the channel-isolated n-type LDMOS device in the previous embodiment.
While preferred embodiments are described and illustrated above, they are not intended to limit the invention in any way. Those skilled in the art can make various alternatives, modifications and variations without departing from the scope of the invention. Thus, it is intended that the present invention embrace all such alternatives, modifications and variations as fall within the true scope of the invention.
Number | Date | Country | Kind |
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2012 1 0264945 | Jul 2012 | CN | national |
Number | Name | Date | Kind |
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7531875 | Udrea et al. | May 2009 | B2 |
Number | Date | Country | |
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20140027850 A1 | Jan 2014 | US |