Patent Application
20250105164
This description relates to semiconductor device assemblies. More specifically, this description relates to leadframe-less power semiconductor device assemblies, that provide for dual-sided cooling.
Semiconductor device assemblies, such as assemblies including power semiconductor devices (which can be referred to as power modules, multi-chip power modules, etc.), can be implemented using semiconductor die, substrates (e.g., direct-bonded metal substrates, ceramic substrates, and so forth), wire bonds, etc., and include a leadframe.
In a general aspect, a semiconductor device assembly includes a first substrate including a first dielectric layer, and a first patterned metal layer disposed on a surface of the first dielectric layer. The assembly also includes a pre-molded semiconductor device module having a first side disposed on and electrically coupled with the first patterned metal layer, and a second substrate including a second dielectric layer, a second patterned metal layer disposed on a first surface of the second dielectric layer. The second patterned metal layer being disposed on and electrically coupled with a second side of the pre-molded semiconductor device module opposite the first side. The second substrate also includes a conductive via defined through the second dielectric layer. The conductive via electrically couples a signal terminal of the pre-molded semiconductor device module with a third patterned metal layer disposed on a second surface of the second dielectric layer opposite the first surface.
Implementations can include one or more of the following features or aspects, alone or in combination. For example, the assembly can include at least one power terminal that is welded to the first patterned metal layer. The assembly can include an output signal terminal that is welded to the first patterned metal layer.
The assembly can include a plurality of electrically conductive spacers that are respectively coupled with the first patterned metal layer; and respectively coupled with the second patterned metal layer.
The conductive via can be a first conductive via of a plurality of conductive vias defined through the second dielectric layer. The plurality of conductive vias can electrically couple respective signal terminals of the pre-molded semiconductor device module with respective portions of the third patterned metal layer.
The pre-molded semiconductor device module can be a first pre-molded semiconductor device module. The assembly can include a second pre-molded semiconductor device module having a first side disposed on and electrically coupled with the first patterned metal layer, and a second side opposite the first side disposed on and electrically coupled with the second patterned metal layer.
The conductive via can be a first conductive via. The second substrate can include a second conductive via electrically coupling a signal terminal of the second pre-molded semiconductor device module with the third patterned metal layer disposed on the second surface of the second dielectric layer.
The first conductive via can be included in a first plurality of conductive vias defined through the second dielectric layer. The second conductive via can be included in a second plurality of conductive vias defined through the second dielectric layer. The first plurality of conductive vias can electrically couple respective signal terminals of the first pre-molded semiconductor device module with respective portions of the third patterned metal layer. The second plurality of conductive vias can electrically couple respective signal terminals of the second pre-molded semiconductor device module with respective portions of the third patterned metal layer.
The assembly can include a molding compound that encapsulates the first pre-molded semiconductor device module, the second pre-molded semiconductor device module, and a plurality of electrically conductive spacers respectively coupled with the first patterned metal layer and the second patterned metal layer. The molding compound can partially encapsulate the first substrate, the second substrate, an output signal terminal that is welded to the first patterned metal layer, and a plurality of power supply terminals that are respectively welded to the first patterned metal layer.
A surface of the patterned metal layer disposed on the second surface of the second dielectric layer can be exposed through the molding compound.
An area of the surface of the first dielectric layer of the first substrate can be greater than an area of the first surface of the second dielectric layer of the second substrate.
In another general aspect, a semiconductor device assembly includes a first substrate including a first dielectric layer; and a first patterned metal layer. The first patterned metal layer includes a first portion disposed on a surface of the first dielectric layer, and a second portion that extends off the surface of the first dielectric layer. The assembly also includes a pre-molded semiconductor device module having a first side disposed on and electrically coupled with the first portion of the first patterned metal layer. The second portion of the first patterned metal layer is electrically coupled with a signal terminal of the pre-molded semiconductor device module via the first portion of the first patterned metal layer. The assembly further includes a second substrate including a second dielectric layer, and a second patterned metal layer disposed on a surface of the second dielectric layer. The second patterned metal layer is disposed on and electrically coupled with a second side of the pre-molded semiconductor device module opposite the first side.
Implementations can include one or more of the following features or aspects, alone or in combination. For example, the assembly can include at least one power terminal that is welded to the second patterned metal layer. The assembly can include an output signal terminal that is welded to the second patterned metal layer.
The assembly can include an electrically conductive spacer that is coupled with the pre-molded semiconductor device module and the second patterned metal layer.
The assembly can include a plurality of electrically conductive spacers being respectively coupled with the first portion of the first patterned metal layer; and respectively coupled with the second patterned metal layer.
The second portion of the first patterned metal layer can include a plurality of extensions that are electrically coupled with respective signal terminals of the pre-molded semiconductor device module.
The pre-molded semiconductor device module can be a first pre-molded semiconductor device module. The semiconductor device assembly can include a second pre-molded semiconductor device module having a first side disposed on and electrically coupled with the first patterned metal layer; and a second side opposite the first side disposed on and electrically coupled with the second patterned metal layer.
The second portion of the first patterned metal layer can include a first plurality of extensions that are electrically coupled with respective signal terminals of the first pre-molded semiconductor device module, and a second plurality of extensions that are electrically coupled with respective signal terminals of the second pre-molded semiconductor device module.
The assembly can include molding compound that encapsulates the first pre-molded semiconductor device module, the second pre-molded semiconductor device module, and a plurality of electrically conductive spacers respectively coupled with the first patterned metal layer and the second patterned metal layer. The molding compound can partially encapsulate the first substrate, the second substrate, an output signal terminal that is welded to the second patterned metal layer, and a plurality of power supply terminals that are respectively welded to the second patterned metal layer.
The molding compound can encapsulate the first portion of the first patterned metal layer. The molding compound can be excluded from the second portion of the first patterned metal layer.
An area of the surface of the first dielectric layer of the first substrate can be greater than an area of the surface of the second dielectric layer of the second substrate.
In another general aspect, a method for producing a semiconductor device assembly includes coupling at least one pre-molded semiconductor device module with a first patterned metal layer disposed on a surface of a first dielectric layer of a first substrate, and coupling an output terminal and at least one power supply terminal with a second patterned metal layer disposed on a first surface of a second dielectric layer of a second substrate. The second substrate has a plurality of conductive vias disposed through the second dielectric layer. The plurality of conductive vias electrically couple respective signal terminals of the at least one pre-molded semiconductor device module with respective portions of a patterned metal layer disposed on a second surface of the second dielectric layer opposite the first surface. The method further includes coupling the second patterned metal layer with the at least one pre-molded semiconductor device module; and with the first patterned metal layer via a plurality of conductive spacers.
In the drawings, which are not necessarily drawn to scale, like reference symbols may indicate like and/or similar components (elements, structures, etc.) in different views. The drawings illustrate generally, by way of example, but not by way of limitation, various implementations discussed in the present disclosure. Reference symbols shown in one drawing may not be repeated for the same, and/or similar elements in related views. Reference symbols that are repeated in multiple drawings may not be specifically discussed with respect to each of those drawings, but are provided for context between related views. Also, not all like elements in the drawings are specifically referenced with a reference symbol when multiple instances of an element are illustrated.
This disclosure relates to implementations of electronic device assemblies, e.g., power semiconductor device assemblies, such as multichip modules (MCMs) that facilitate dual-sided cooling. Such assemblies can be used in, e.g., automotive applications, industrial applications, etc. For instance, the implementations described herein can implement (include) high-power semiconductor device modules, such as power converters, ignition circuits, power transistor pairs, half-bridge circuits, etc. For purposes of illustration, and by way of example, disclosed implementations are described as implementing half-bridge circuits. In some implementations, other circuits can be implemented using the approaches described herein.
In prior implementations, semiconductor device assemblies (assemblies) with dual-sided cooling can include, in addition to a plurality of semiconductor die, multiple substrates, such as direct-bonded metal (DBM) substrates, and a leadframe, e.g., a single body leadframe including signal leads, and power and/or output terminals. The DBM substrates, e.g., direct-bonded copper (DBC) substrates, are used, e.g., in combination with a heatsink, fluidic cooling jacket, etc., to dissipate thermal energy generated during electrical operation of the assembly. In such implementations, a size of an associated assembly, e.g., size of the associated substrates, can be limited by its leadframe. In other words, use of a leadframe can prevent, or limit, reducing a size of a corresponding assembly, such as a size (or respective sizes) of DBM substrates included in the assembly. This limitation can, in turn, prevent reduction of material costs and associated manufacturing costs.
Also, tooling used for producing such prior assemblies including leadframe structures can limit manufacturing throughput, e.g., can be a factor that limits a number of assemblies that can be produced in a given time period, such as a number of units per hour (uph). Furthermore, use of a leadframe can contribute to parasitic impedance, e.g., stray inductance, associated with overall length (in a direction of current conduction) and size of power terminals of a leadframe structure that are included in an associated power semiconductor device assembly.
Prior implementations can also include electrically conductive spacers for providing interconnections between semiconductor die (e.g., bare semiconductor die) and associated substrates (e.g., DBM substrates, such as direct-bonded copper (DBC) substrates). Suitable materials for such spacers in prior implementations may be limited to materials with appropriate coefficients of thermal expansion, e.g., to prevent reliability issues related to thermal cycling, such as die cracking. For example, such materials include copper molybdenum (CuMo), or aluminum silicon carbide (AlSiC). Use of such spacer materials can increase associated product costs, as their cost is relatively high as compared to other electrically conductive spacer materials, such as pure copper, for example.
In comparison to prior semiconductor device assemblies, implementations described herein are leadframe-less semiconductor device assemblies that facilitate dual side cooling. That is, example implementations described herein exclude a leadframe. Accordingly, such implementations can provide for reduction in substrate sizes not achievable in prior implementations. Such size reductions can, in turn, reduce material and overall product costs.
The implementations described herein can be referred to as having a package-in-package configuration. That is, in example implementations, at least one pre-molded semiconductor device module can be included in a semiconductor device assembly. For instance, the at least one pre-molded semiconductor device module can be disposed between, and coupled with, a first (top) DBM substrate and a second (bottom) DBM substrate, which can then be molded using an epoxy molding compound. In example implementations described herein, a first pre-molded semiconductor device module of an assembly can include one more low-side transistors of a corresponding half-bridge circuit implemented in the assembly, while a second pre-molded semiconductor device module can include one more high-side transistors of the half-bridge circuit.
Also in the example implementations described herein, power terminals (and output terminals) that are shorter (along a direction of current flow), as compared to those of prior implementations can be used. Accordingly, parasitic impedance (stray inductance) associated with power terminals can be reduced in the example implementations, as compared to prior implementations having longer power terminals that are included in a single-body leadframe structure.
The semiconductor device assembly 100 also includes pre-molded semiconductor modules 130a and 130b, e.g., packaged semiconductor device modules that are included in the package-in-package arrangement of the semiconductor device assembly 100. In this example, the pre-molded semiconductor module 130a can include one or more low-side transistors of a half-bridge circuit that is implemented by the semiconductor device assembly 100, while the pre-molded semiconductor module 130b can include one or more high-side transistors of the half-bridge circuit. Though not specifically shown in
As shown in
The semiconductor device assembly 100 also includes a molding compound 170, such as an epoxy molding compound, that can encapsulate portions of the other elements of the semiconductor device assembly 100. For instance the molding compound 170 can encapsulate the pre-molded semiconductor modules 130a and 130b (and any conductive spacers included in the semiconductor device assembly 100). Further, the molding compound 170 can at least partially encapsulate the top substrate 110, the bottom substate 120, the one or more power supply terminals 140, the output terminal 150 and the signal terminals 160. That is respective portions of each of the top substrate 110, the bottom substate 120, the one or more power supply terminals 140, and the output terminal 150 can be encapsulated in the molding compound 170, while other respective portions are accessible and/or disposed outside of (exposed through, etc.) the molding compound 170. In some implementations, exposed portions (e.g., metal layers) of the top substrate 110 and the bottom substate 120 can be coupled with respective thermal dissipation devices, such as0 heatsinks or fluidic cooling jackets, which can provide for efficient dual-sided cooling of the semiconductor device assembly 100 during operation.
In the semiconductor device assembly 100 (and other example implementations described herein), the signal terminals 160 are implemented without use of signal leads of a leadframe, such as using the approaches described hereinbelow. Briefly, in some implementations, the signal terminals 160 can be implemented using at least one of respective portions of a patterned metal layer of the top substrate 110, respective portions of a patterned metal layer of the bottom substate 120, and/or respective conductive vias formed (e.g., defined, etc.) through the top substrate 110 and/or the bottom substate 120. Such approaches are provided by way of example, and other approaches for implementing the signal terminals 160 in the semiconductor device assembly 100 are possible.
In some implementations, as noted above, the semiconductor device assembly 100 can include additional elements other than those shown in
Referring to
In the example of
As further shown in
In this example, the pre-molded semiconductor module 230a includes a first low-side transistor and a second low-side transistor of a half-bridge circuit of the semiconductor device assembly of
Also in this example, the pre-molded semiconductor module 230b includes a first high-side transistor and a second high-side transistor of the half-bridge circuit of the semiconductor device assembly of
As also shown in
In this example, the conductive spacers 222 are used to electrically couple, as well as physically couple (e.g. via solder connections), the substrate 220 with a corresponding substrate (top substrate), such as a substrate 210 shown in
As shown in
Referring to
In this example, as illustrated in
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As shown in
In this example, the pre-molded semiconductor module 230a, and the conductive spacers 222 are encapsulated in the molding compound 270. Further, the substrate 210, the substrate 220, the power terminal 240a, and the output terminal 250 are partially encapsulated in the molding compound 270. For instance, the signal metal portion 218 is partially encapsulated, e.g., a surface of the signal metal portions 218 is exposed through the molding compound 270. Likewise, surfaces of metal layers of the substrate 210 (e.g., the patterned metal layer 217) and the substrate 220 (e.g., a metal layer 219) are exposed through the molding compound, e.g., to facilitate attachment of thermal dissipations devices (e.g., heatsinks and/or fluidically cooled jackets). Other elements of the semiconductor device assembly 200 that are not shown in the cross-sectional view of
Referring to
In the example of
Also in this example, the pre-molded semiconductor module 330b includes at least one low-side transistor of the half-bridge circuit, where multiple low-side transistors can be connected in parallel with each other in the pre-molded semiconductor module 330b, and a common drain connection 335b (e.g., a die attach paddle of the pre-molded semiconductor module 330b) is facing out of the page. Source connections of the pre-molded semiconductor module 330b (not shown) are coupled with the portion 324a of the patterned metal layer 324, and signal connections 334b are coupled with respective portions (patterned metal layer extensions) of the portion 324b of the patterned metal layer 324. In this example, as with the signal connections 334a, the signal connections 334b are shown in a through-view in
Referring to
As shown in
As shown in
As also shown in
Referring to
As with
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Further, as shown in
The method 400 includes, at block 410, performing a solder print operation on a first substrate, e.g., the (bottom) substrate 220. The solder print operation of block 410 can dispose solder on the substrate 220 (e.g., on the patterned metal layer 224) for attachment of the pre-molded semiconductor modules 230a and 230b and/or the conductive spacers 222. In some implementations, the conductive spacers 222 can be coupled with the substrate 210 prior to the solder print operation of block 410. At block 420, the method 400 includes attaching the pre-molded semiconductor modules 230a and 230b and/or the conductive spacers 222 to the solder of the print operation at block 410. For instance, the operation at block 420 of the method 400 can include disposing the pre-molded semiconductor modules 230a and 230b and/or the conductive spacers 222 on the solder applied at block 410 using automated placement equipment (e.g., pick and place equipment). At block 430, the method 400 includes performing a reflow operation to physically and electrically couple the pre-molded semiconductor modules 230a and 230b and/or the conductive spacers 222 with the patterned metal layer 224 of the substrate 220.
At block 440, the method 400 includes coupling the output terminal 250, and the power terminals 240a and 240b to the patterned metal layer 224 of the substrate 220. As discussed above, in some implementations, the output terminal 250, and the power terminals 240a and 240b can be coupled with the patterned metal layer 224 using laser welding. In other implementations, the output terminal 250 and the power terminals 240a and 240b can be coupled with the patterned metal layer 224 using solder (e.g., as part of operations of blocks 410, 420 and 430, with the operation of block 440 being omitted).
At block 450, the method 400 includes performing a solder print operation on a second substrate, e.g., the (top) substrate 210. The solder print of block 450 can dispose solder on the substrate 210 (e.g., on the patterned metal layer 214) for attachment of the substrate 210 to the substrate 220, e.g., to the conductive spacers 222 and the pre-molded semiconductor modules 230a and 230b. At block 460, the method 400 includes attaching the substrate 210 to the substrate 220. For instance, the substrate 210 can be automatically placed, e.g., using automated pick and placement equipment. on the substrate 220, e.g. vice versa, such that the patterned metal layer 214 is disposed on the conductive spacers 222 and the pre-molded semiconductor modules 230a and 230b, e.g., as shown in
At block 480, a molding operation and a post-mold cure operation can be performed to encapsulate the semiconductor device assembly 200, such as shown in
The method 500 includes, at block 510, performing a solder print operation on a first substrate, e.g., the substrate 320. The solder print operation of block 510 can dispose solder on the substrate 320 (e.g., on the portions 324a and 324b of the patterned metal layer 324) for attachment of the pre-molded semiconductor modules 330a and 330b. At block 520, the method 500 includes attaching the pre-molded semiconductor modules 330a and 330b to the solder of the print operation at block 510. For instance, the operation at block 520 of the method 500 can include disposing the pre-molded semiconductor modules 330a and 330b on the solder applied by the solder print operation of block 510 using automated placement equipment (e.g., pick and place equipment). At block 530, the method 500 includes performing a reflow operation to physically and electrically couple the pre-molded semiconductor modules 330a and 330b with the patterned metal layer 324 of the substrate 320.
At block 540, the method 400 includes coupling the output terminal 350, the power terminals 340a and 340b, the conductive spacers 322, and/or the conductive spacers to the patterned metal layer 314 of the substrate 210. As discussed above, in some implementations, the output terminal 350, and the power terminals 340a and 340b can be coupled with the patterned metal layer 314 using laser welding. In other implementations, the output terminal 350 and the power terminals 340a and 340b can be coupled with the patterned metal layer 324, along with the conductive spacers 322 and the conductive spacers 322 using solder (e.g., including a solder print operation, an attach (placement) operation, and a reflow operation at block 540).
At block 550, the method 500 includes performing a solder print operation on a second substrate, e.g., the substrate 310. The solder print of block 550 can dispose solder on the conductive spacers 322 and the conductive spacers 323 for attachment of the substrate 210 to the substrate 220, e.g., to the portion 324a of the patterned metal layer 324, and to the pre-molded semiconductor modules 330a and 330b. At block 560, the method 500 includes attaching the substrate 310 to the substrate 320. For instance, the substrate 310 (e.g., as shown in
At block 580, a molding operation and a post-mold cure operation can be performed to encapsulate the semiconductor device assembly 300, such as shown in
It will be understood that, in the foregoing description, when an element, such as a layer, a region, or a substrate, is referred to as being on, connected to, electrically connected to, coupled to, or electrically coupled to another element, it may be directly on, connected or coupled to the other element, or one or more intervening elements may be present. In contrast, when an element is referred to as being directly on, directly connected to or directly coupled to another element or layer, there are no intervening elements or layers present. Although the terms directly on, directly connected to, or directly coupled to may not be used throughout the detailed description, elements that are shown as being directly on, directly connected or directly coupled can be referred to as such. The claims of the application may be amended to recite exemplary relationships described in the specification or shown in the figures.
As used in this specification, a singular form may, unless definitely indicating a particular case in terms of the context, include a plural form. Spatially relative terms (e.g., over, above, upper, under, beneath, below, lower, top, bottom, and so forth) are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. In some implementations, the relative terms above and below can, respectively, include vertically above and vertically below. In some implementations, the term adjacent can include laterally adjacent to or horizontally adjacent to.
Some implementations may be implemented using various semiconductor processing and/or packaging techniques. Some implementations may be implemented using various types of semiconductor processing techniques associated with semiconductor substrates including, but not limited to, for example, Silicon (Si), Silicon Carbide (SiC), Gallium Arsenide (GaAs), Gallium Nitride (GaN), and/or so forth.
While certain features of the described implementations have been illustrated as described herein, many modifications, substitutions, changes and equivalents will now occur to those skilled in the art. For instance, features illustrated and/or aspects described with respect to one implementation can, where appropriate, also be included in, and/or apply to other implementations. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the scope of the implementations. It should be understood that they have been presented by way of example only, not limitation, and various changes in form and details may be made. Any portion of the apparatus and/or methods described herein may be combined in any combination, except mutually exclusive combinations. The implementations described herein can include various combinations and/or sub-combinations of the functions, components and/or features of the different implementations described.
