Patent Application
20160336172
The present invention relates to semiconductor devices and methods of fabricating semiconductor devices, and more particularly, to methods of forming lithography stacks during the lithography processes of fabrication, intermediate semiconductor devices with a lithography stack, and lithography stacks.
Semiconductor devices, such as integrated circuits, are typically fabricated using one or more lithography processes. The lithography processes are generally performed after application of a lithography stack over the semiconductor device. Many currently available lithography stacks may experience defects from rework which result in poor yield and advanced nodes may have high risks for defects that were not present in earlier nodes. In addition, currently available lithography stacks use materials that are chemically unstable or materials that require additional processing steps resulting in higher manufacturing costs.
The shortcomings of the prior art are overcome and additional advantages are provided through the provision, in one aspect, of a method which includes, for instance: obtaining an intermediate semiconductor device with a substrate; applying a spin on carbon layer over the substrate; and applying a hardmask layer over the spin on carbon layer.
In another aspect, an intermediate semiconductor device is presented which includes, for instance: a substrate; a spin on carbon layer over the substrate; and a hardmask layer over the spin on carbon layer.
In yet another aspect, a lithography stack is presented which includes, for instance: a spin on carbon layer; an invisible hardmask layer over the spin on carbon layer; and a photoresist layer over the invisible hardmask layer.
Additional features and advantages are realized through the techniques of the present invention. Other embodiments and aspects of the invention are described in detail herein and are considered a part of the claimed invention.
One or more aspects of the present invention are particularly pointed out and distinctly claimed as examples in the claims at the conclusion of the specification. The foregoing and other objects, features, and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which:
Aspects of the present invention and certain features, advantages, and details thereof, are explained more fully below with reference to the non-limiting embodiments illustrated in the accompanying drawings. Descriptions of well-known materials, fabrication tools, processing techniques, etc., are omitted so as to not unnecessarily obscure the invention in detail. It should be understood, however, that the detailed description and the specific examples, while indicating embodiments of the invention, are given by way of illustration only, and are not by way of limitation. Various substitutions, modifications, additions and/or arrangements within the spirit and/or scope of the underlying inventive concepts will be apparent to those skilled in the art from this disclosure. Note also that reference is made below to the drawings, which are not drawn to scale for ease of understanding, wherein the same reference numbers used throughout different figures designate the same or similar components.
The present disclosure addresses and enhances, inter alia, lithography processing, more specifically, the lithography stack for use during semiconductor fabrication. Lithography processing typically includes applying a lithography stack over an intermediate semiconductor device which includes at least a substrate and may include additional fabrication topography. The lithography stacks have generally included at least a substrate and a photoresist layer applied over the substrate in order to transfer the pattern onto the substrate during lithography. As the size of technology nodes of semiconductor devices has decreased additional layers have been added to the lithography stack to account for substrate reflection and/or topography on the surface of the devices. For example, when the size of technology nodes decreased, devices started to experience defects due to substrate reflection created during the lithography processing. In order to account for the substrate reflection a bottom anti-reflection coating (BARC) layer was added between the substrate and photoresist layers.
As the size of the technology nodes continued to decrease and node technology advanced, the topography of some semiconductor devices changed and the topography of the semiconductor devices started to be negatively affected by the lithography processing. Devices may have added topography due to, for example, design specifications that result in raised features on the semiconductor devices, such as, fins, as well as other more complicated layering patterns. With the topography of semiconductor device designs becoming more important, the BARC layer was no longer able to account for the substrate reflection and the substrate topography. Thus, a planarization layer was added and applied over the substrate before application of the BARC layer. The planarization layer may account for the device topography to provide a planar surface for application of the BARC layer, whether or not the underlying topography is planar. The planarization layer may be, for example, a second BARC layer, and may have properties that enable it to be used for both planarization of the device and optimization of the substrate reflection. The BARC layer that is applied over the planarization layer may also serve as a hardmask layer for etching the planarization layer. In one embodiment, the second BARC layer is an organic material which is applied over the intermediate semiconductor device, then the first BARC layer which is an inorganic material is applied over the second BARC layer, and finally the photoresist layer, which is also an organic material, is applied over the first BARC layer to form a lithography stack. The inorganic first BARC layer is applied between the organic second BARC layer and organic photoresist layer to provide the selectivity necessary to transfer the photoresist pattern to the substrate. The first BARC layer being inorganic provides the necessary etch selectivity to enable the photoresist pattern to be transferred.
In one embodiment of a two BARC lithography stack, the lithography stack includes a first BARC layer that may be, for example, a silicon containing antireflection coating (SiARC) and a second BARC layer that may be, for example, an optical planarization layer (OPL). Thus, the lithography stack includes a substrate with an OPL layer applied over the substrate, then a SiARC layer applied over the OPL layer, and finally the photoresist layer applied over the SiARC layer. Since SiARC is chemically unstable, if rework is required due to overlay failures or the critical dimension not meeting the specifications, then the entire lithography stack must be removed and reapplied. In addition, SiARC can cause defects in the resulting semiconductor devices if rework is performed due to failure to remove all the silicon particles from the substrate. If additional silicon particles remain on the substrate after rework they will cause defects and be a yield detractor in the resulting semiconductor device.
Generally stated, disclosed herein are certain novel lithography processing methods and lithography stacks, which provide significant advantages over the above noted, existing lithography processing methods and lithography stacks. Advantageously, the lithography processing methods and lithography stacks disclosed herein may prevent defects and improve the yield of resulting semiconductor devices. Additionally, as explained herein, the lithography processing methods and lithography stacks disclosed herein may reduce production costs by decreasing the number of materials needed in the lithography stack and reducing the materials which need to be removed and reapplied during rework. By reducing the number of materials used and the number of reworks, the number of etch processes is also reduced which in turn may reduce process variation to lower the rework rate and result in lower cost and better yield.
During fabrication a substrate or wafer will be processed through numerous procedures to create the semiconductor device. One such procedure is lithography processing of the substrate. In order for the substrate to undergo lithography processing, a lithograph stack must be applied over the substrate.
As shown in
In one aspect, in one embodiment, as shown in
With continued reference to the fabrication processes of
The invisible hardmask layer 108 is applied over the SOC layer 104 and acts as a capping layer to allow for the photoresist layer 110 to be removed without removing the entire lithography stack 114. The invisible hardmask layer 108 is invisible to the imager at the imaging wavelength, which may be, for example, 193 nm. Thus, if rework is required on a semiconductor device 100 with a lithography stack 114 the rework path will be cleaner because only the organic photoresist layer 110 will need to be removed and reapplied. The material of the hardmask layer 108 may include optical properties that include a refractive index (n) value and an extinction coefficient (k) value. The values of the refractive index (n) and extinction coefficient (k) of the hardmask layer 108 may be adjusted to match the refractive index (n) and extinction coefficient (k) values of the photoresist layer 110 at the imaging wavelength. When the refractive index (n) and extinction coefficient (k) values of the hardmask layer 108 match the n and k values of the photoresist 110 at the imaging wavelength the hardmask layer 108 is invisible to the imager. The hardmask layer 108 may be, for example, physical vapor deposition (PVD) SiOxNy. The PVD SiOxNy may be applied without hydrogen, thus, enabling a lower extinction coefficient (k) value for the hardmask layer 108 that cannot be achieved when using chemical vapor deposition to apply SiOxNy. Thus, using PVD SiOxNy enables the extinction coefficient (k) of the hardmask layer 108 to be matched to the extinction coefficient (k) of the photoresist layer. Alternative deposition processes, for example, spin coating and the like, that maintain the optical properties of the hardmask layer 108 and are able to match the optical properties of the hardmask layer 108 to the photoresist layer 110 are also contemplated. Since PVD can be performed without hydrogen, this enables deposition of a SiOxNy hardmask with a refractive index (n) and extinction coefficient (k) matched to the photoresist layer 110. A SiOxNy hardmask layer 108 allows for direct etching on the SiOxNy layer which enables process induced variations to be minimized providing better process control which reduces the need for rework and therefore reduces defects which lowers costs and produces higher yield. In addition, the hardmask layer 108 provides a chemically stable inorganic base for the photoresist layer 110 to be applied. The chemically stable inorganic hardmask layer 108 prevents scumming or poisoning, thus, the resultant semiconductor devices may have improved critical dimension uniformity, improved line edge roughness, and improved line width roughness.
By way of specific example only, one detailed embodiment of the lithography stack may include, for example, a substrate 102, at least one raised structure 104 on the substrate 102, a SOC layer 106 over the substrate 102, an invisible hardmask layer 108 over the SOC layer 106, a photoresist layer 110 over the invisible hardmask layer 108, and an optional top coat (not shown) over the photoresist layer 110. The substrate 102 may have refractive index (n) and extinction coefficient (k) values of, for example, approximately 0.88 and 2.78. The at least one raised structure 104 may be for example, TiN which may have n and k values of, for example, approximately 2.10 and 1.51. The SOC layer 106 may have n and k values of, for example, approximately 1.60 and 0.35. The invisible hardmask layer and the photoresist layer may each have n and k values of, for example, approximately 1.68 and 0.03. Finally, the topcoat (not shown) may have n and k values of, for example, approximately 1.54 and 0.006. The refractive index (n) and extinction coefficient (k) values will be dependent on the materials being used for each layer.
The lithography stack 114 and method of forming the lithography stack 114 as described in greater detail above may, for example, reduce rework costs because only the photoresist layer 110 needs to be removed and reapplied if there are overlay failures or the critical dimensions do not meeting the specifications of the semiconductor device. In addition, since only the organic photoresist layer 110 needs to be removed and reapplied the opportunities for defect creation are decreased compared to those seen with other lithography stacks and methods. The lithography stack 114 may be used, for example, for single patterning or multiple patterning and may also be used on any size technology node. The lithography stack 114 may also simplify patterning and reduce process variation because there are less layers and steps in forming the lithography stack 114 and patterning after etching. With the decrease in defects caused by rework when using the lithography stack 114, the yield of the resultant semiconductor device may be enhanced.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprise” (and any form of comprise, such as “comprises” and “comprising”), “have” (and any form of have, such as “has” and “having”), “include” (and any form of include, such as “includes” and “including”), and “contain” (and any form contain, such as “contains” and “containing”) are open-ended linking verbs. As a result, a method or device that “comprises”, “has”, “includes” or “contains” one or more steps or elements possesses those one or more steps or elements, but is not limited to possessing only those one or more steps or elements. Likewise, a step of a method or an element of a device that “comprises”, “has”, “includes” or “contains” one or more features possesses those one or more features, but is not limited to possessing only those one or more features. Furthermore, a device or structure that is configured in a certain way is configured in at least that way, but may also be configured in ways that are not listed.
The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below, if any, are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain the principles of one or more aspects of the invention and the practical application, and to enable others of ordinary skill in the art to understand one or more aspects of the invention for various embodiments with various modifications as are suited to the particular use contemplated.
