Patent Application
20100221867
The present invention relates to semiconductor structures and a method of fabricating the same. More particularly, the present invention relates to a low cost semiconductor-on-insulator (SOI) substrate that can be used in a variety of semiconductor applications including, for example, as a substrate for a solar or photovoltaic cell. The present invention also provides a method of fabricating a solar cell utilizing the inventive SOI substrate as well as a solar cell including the same.
A solar cell or photovoltaic cell is a device that converts sunlight directly into electricity by the photovoltaic effect. Sometimes the term “solar cell” is reserved for devices intended specifically to capture energy from sunlight, while the term “photovoltaic cell” is used when the source is unspecified. Assemblies of cells are used to make solar panels, solar modules, or photovoltaic arrays.
The out voltage of a solar cell is limited by the band energy structure of its semiconductor structure, such that it is less than one volt for silicon based cells. Photovoltaic generators of higher voltages can be obtained by series association of cells. Each cell has to be individually electrically isolated from the others. When individual cells are associated they are typically mounted on an electrical insulator material and interconnected by external wiring.
Semiconductor-on-insulator (SOI) substrates provide a material that typically consists of a single crystalline silicon film (typically, but not necessarily always, thinner than 100 nm) isolated from a bulk substrate by an interposed oxide, e.g., a buried oxide, BOX. An SOI substrate allows the realization of monolithic and electrically isolated solar cells. Furthermore, it is possible to realize parallel association of identical arrays of series connected cells to provide higher current at a same voltage. These photovoltaic generators can be used in battery charge systems or to feed power to any other system in which the input voltage matches its output voltage.
One fundamental problem associated with the monolithic integration of solar cells is the cost of the SOI substrate. Two major processes are known and are presently employed to fabricate SOI substrates. One of the known processes of fabricating SOI substrates is an implantation process refer to as Separation by Implantation of Oxygen, e.g., SIMOX. The other major process known for fabricating SOI substrates is by bonding and layer transfer. Both of these known processes of fabricating SOI substrates provide a SOI material of excellent quality however, they are both relatively costly.
A simpler process of fabricating SOI substrates at a lower cost as compared with the known processes described above is disclosed, for example, in U.S. Ser. No. 12/170,459, filed Jul. 10, 2008, entitled “Formation of SOI by Oxidation of Silicon with Engineered Porosity Gradient”. In this prior art method, an SOI substrate is formed by anodization of stacked epitaxial grown layers of different p-type dopant concentration in order to obtain a depth distribution of the porosity. Subsequent oxidation followed by a high temperature anneal (on the order of 1100° C.) converts the buried layer of highest porosity (i.e., the buried layer of highest doping concentration) into a buried oxide layer. In this prior art method, the layer closest to the surface where the porosity is the lowest, is converted to a crystalline silicon layer, e.g., the SOI layer, of a now formed SOI substrate.
The present invention provides an alternative method of fabricating low cost SOI substrates that can be used in a variety of semiconductor applications including, but not limited to, as a substrate for a solar cell or photovoltaic cell. It should be noted that the structure of the solar cell and the photovoltaic cell provided by the invention are the same; the difference in terminology being the type of source impinging upon the cell.
In particular, the present invention provides a method in which a stack containing a plurality of amorphous Si-containing layers is formed on a major surface of a semiconductor substrate, rather than a stack of epitaxial Si-containing layers as disclosed in U.S. Ser. No. 12/170,459, filed Jul. 10, 2008. In the present invention, the amorphous Si-containing layers within the stack can be formed by utilizing an evaporation deposition process. The evaporation deposition process used in the present invention may include, for example, e-beam deposition, co-evaporation deposition, plasma enhanced chemical vapor deposition (PECVD) and sputtering. Doping of the amorphous Si-containing layers can be performed in-situ or ex-situ by ion implantation, gas phase doping, gas phase immersion and/or outdiffusion from a sacrificial dopant source layer. In a highly preferred embodiment of the present invention, the p-type doped amorphous Si-containing layers are formed by a co-evaporation method wherein simultaneous evaporation of a Si-containing source material and p-type dopant atoms (e.g., boron, gallium, indium, with boron being preferred) is employed. Solid phase recrystallization of the amorphous Si-containing layers is then performed using the underlying semiconductor substrate as a recrystallization template. During this step of the present invention, the p-type doped amorphous Si-containing layers are converted into p-type doped single crystalline Si-containing layers. After recrystallization, the single crystalline Si-containing layers are subjected to anodization and at least an oxidation step to form an SOI substrate.
The SOI substrate fabricated in accordance with the present invention can be directly used as a substrate for a semiconductor device, such as a thin film solar cell or a photovoltaic cell, or it can be used as a template for growth of silicon or different crystalline semiconductor materials for thicker film cells or multi-junction cells.
In general terms, the method of the present invention includes:
The inventive process provides an SOI substrate including a silicon-containing monocrystalline semiconductor layer separated from an underlying semiconductor region by a buried oxide layer having a thickness less than or equal to about 100 nm, the buried oxide layer having a surface roughness having a root mean square value of less than about one nanometer.
In one embodiment of the present invention, the processing includes a step of subjecting the substrate including the stack of single crystalline Si-containing layers to anodization to selectively form a porous Si-containing layer of higher porosity from the first p-type doped single crystalline layer and a porous Si-containing layer of a lower porosity from the second p-type doped Si-containing layer prior to oxidizing the porous Si-containing layers to form a buried oxide layer and a monocrystalline semiconductor layer. Porosity is defined herein as the ratio of the specific weight of the porous Si-containing material and the specific weight of the original ‘non-porous’ Si-containing material. In this embodiment of the invention, the buried oxide layer is formed by fully oxidizing the layer of higher porosity and then annealing is performed at a high temperature to convert the layer of lower porosity to the monocrystalline semiconductor layer.
In another embodiment of the present invention, the stack of amorphous Si-containing layers includes a non-highly p-type doped amorphous Si-containing layer having a dopant concentration less than the first p-type doped amorphous Si-containing layer interposed between the semiconductor region of the underlying substrate and the first p-type doped amorphous Si-containing layer. In yet a further embodiment of the present invention, a highly p-type doped amorphous Si-containing layer is formed onto a major surface of the second p-type doped amorphous Si-containing layer. When the highly p-type doped amorphous Si-containing layer is present, it is converted into an overlying oxide layer, which can be removed in a subsequent processing step. It is observed that the presence of the highly p-type doped amorphous Si-containing layer atop the second p-type doped amorphous Si-containing layer protects the second p-type doped amorphous Si-containing layer from pitting during anodization and reduces the defect density in the monocrystalline semiconductor layer which results from the second p-type doped Si-containing layer.
In an even further embodiment of the present invention, the stack of p-type doped amorphous Si-containing layers includes a plurality of alternating layers of the first and second p-type doped amorphous Si-containing layers located atop each other. In this embodiment, it is possible to form an SOI substrate including a plurality of alternating layers of buried oxide and monocrystalline semiconductor material vertically stacked upon each other.
The present invention also provides a semiconductor structure including the SOI substrate produced using the inventive process and at least one semiconductor device located on a surface thereof. In one embodiment of the invention, the at least one semiconductor device is a solar cell or a photovoltaic cell. The inventive structures including at least a solar cell or at least one photovoltaic cell atop the inventive SOI substrate have a voltage output ranging from 0.5 to 120 V.
The solar cell or photovoltaic cell of the present invention includes alternating layers of doped Si-containing materials stacked vertically upon an uppermost monocrystalline semiconductor layer of the inventive SOI substrate. The doped Si-containing layers may all be crystalline, all be amorphous or be a mixture of amorphous and crystalline Si-containing materials. The alternating layers of Si-containing materials typically include a p+ Si-containing material located on a surface of the monocrystalline semiconductor layer, a p− Si-containing material located on a surface of the p+ Si-containing material, and an n+Si-containing material located on a surface of the p− Si-containing material.
The present invention, which provides a simple and low cost method of fabricating SOI substrates that can be used in various semiconductor applications, including in solar cell or photovoltaic cell fabrication, will now be described in greater detail by referring to the following discussion and drawings that accompany the present application. It is noted that the drawings of the present application are provided for illustrative purposes only and, as such, the drawings are not drawn to scale.
In the following description, numerous specific details are set forth, such as particular structures, components, materials, dimensions, processing steps and techniques, in order to provide a thorough understanding of the present invention. However, it will be appreciated by one of ordinary skill in the art that the invention may be practiced without these specific details. In other instances, well-known structures or processing steps have not been described in detail in order to avoid obscuring the invention.
It will be understood that when an element as a layer, region or substrate is referred to as being “on” or “over” another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.
Reference is first made to
Reference is first made to
Doping can be achieved utilizing any conventional process including, for example, ion implantation, gas phase doping and outdiffusion from a p-type dopant surface material which is selectively removed following the outdiffusion process.
Next, and as shown in
In
Notwithstanding the number of p-type dopant layers within stack 18 each p-type dopant layer is amorphous and includes a Si-containing semiconductor material selected from Si, SiGe, SiC, SGeC and other like semiconductor materials that include silicon. Preferably, each of the Si-containing layers within stack 18 is composed of silicon.
Stack 18, e.g., the plurality of p-type doped amorphous Si-containing layers, is formed utilizing an evaporation deposition process selected from the group consisting of e-beam, co-evaporation deposition, plasma enhanced chemical vapor deposition, and sputtering. In order to ensure that amorphous Si-containing layers are formed, the deposition is performed at a temperature of about 500° C. or less. Preferably, the amorphous Si-containing layers of stack 18 are formed by high vacuum e-beam deposition. In the evaporation deposition processes mentioned above, deposition is performed at a pressure of less than about 1×10−7 Torr, with a deposition pressure of from 1×10−8 Torr to 1×10−10 Torr being more preferred. In a highly preferred embodiment of the present invention, the p-type doped amorphous Si-containing layers are formed by a co-evaporation method wherein simultaneous evaporation of a Si-containing source material and p-type dopant atoms (e.g., boron, gallium, indium, with boron being preferred) is employed.
Each amorphous Si-containing layer present in stack 18 is doped in-situ or ex-situ, with in-situ doping being preferred. Examples of doping processes that can be used in the present invention include, but are not limited to ion implantation, gas phase in-situ doping, gas phase immersion and/or outdiffusion from a sacrificial dopant source layer. When ex-situ doping is used, doping occurs after depositing each amorphous Si-containing layer within stack 18.
When ion implantation is used in creating the p-type doped layers, p-type dopant ions are implanted using an energy of greater than 1 keV, with an energy from 10 keV to 30 keV being more typical. The ion implantation may occur at nominal room temperature (i.e., 20°-30° C.) or at a substrate temperature greater than 35° C. with a temperature from 100° C. to 300° C. being more typical. The p-type dopant is performed to a proper dose and energy after each individual layer is formed.
When plasma immersion is used to introduce the p-type dopants, the plasma immersion is performed by first providing a plasma that includes the p-type dopant. The introduction of the p-type dopant is then performed utilizing plasma immersion conditions that are capable of forming the p-type dopant Si-containing layer. Typically, the plasma immersion is performed utilizing standard operating conditions to achieve similar ion concentrations as stated above in connection with each of the amorphous Si-containing layers within stack 18.
When a sacrificial dopant source material containing a p-type dopant is used in forming the p-type amorphous Si-containing layers of stack 18, a sacrificial material containing the p-type dopants is first deposited on the surface of a deposited amorphous Si-containing layer of stack IS. The sacrificial dopant source material including the p-type dopant may comprise a boron doped silicate glass, for example. The p-type dopant is present in the sacrificial material in amounts that achieve desired concentrations of the p-type dopants in the amorphous Si-containing layer of stack 18. The sacrificial dopant source material can be deposited by any conventional deposition process such as, for example, chemical vapor deposition, plasma enhanced chemical vapor deposition, evaporation, spin-on coating, and physical vapor deposition. The thickness of the sacrificial dopant source material containing the p-type dopants may vary. After depositing the sacrificial dopant source material, the material layer including the p-type dopants is then annealed under conditions that are effective for causing diffusion of the dopants from the sacrificial material layer into the underlying Si-containing layer. The annealing may be performed in a furnace or in a chamber in which the dopant source material layer was initially deposited. The anneal step is performed at a temperature of greater than about 550° C. with a temperature from 900° C. to 1100° C. being more typical. In addition to the specific types of annealing mentioned above, the present invention also contemplates rapid thermal annealing, spike annealing, laser annealing and other like annealing processes that are capable of performing dopant diffusion. After diffusion, the dopant source material layer is typically stripped from the surface of the structure utilizing a conventional stripping process.
Another technique that can be used in forming the p-type dopant amorphous Si-containing layers is to introduce the p-type dopant into the layer by in-situ gas phase doping. In such a process, the doping may occur after forming a particular amorphous Si-containing layer by changing the precursors used in formation of layer Si-containing layer to include p-type dopants.
The thickness of each amorphous Si-containing layer within stack 18 may vary depending on the desired thickness of the buried oxide layer and monocrystalline semiconductor layer to be subsequently formed. When present, amorphous Si-containing layer 19 has a thickness from 10 nm to 1000 nm, amorphous Si-containing layer 20 has a thickness from 5 nm to 200 nm, amorphous Si-containing layer 22 has a thickness from 40 nm to 500 nm, and amorphous Si-containing layer 23, if present, has a thickness from 10 nm to 50 nm. It is observed that the thickness of amorphous Si-containing layer 20 will determine the thickness of the buried oxide layer to be subsequently formed, while the thickness of the amorphous Si-containing layer 22 determines the thickness of the monocrystalline semiconductor layer to be subsequently formed.
It is further observed that in the following drawings and description, the processing steps are described utilizing the structure shown in
After providing stack 18 atop substrate 12, a solid phase epitaxy process is performed which converts stack 18 of p-type doped amorphous Si-containing layers into a stack 24 of single crystalline Si-containing layers. The resultant structure, including stack 24 is shown, for example, in
The solid phase epitaxy process of the present invention converts the amorphous Si-containing layers within stack 18 into a stack in which each of the layers is a single crystalline Si-containing material. The solid phase epitaxy process may be performed by furnace annealing, rapid thermal annealing, laser annealing, electron beam annealing and other like annealing processes that are capable of recrystallization. In addition to performing the aforementioned function, the solid phase epitaxy also activates the p-type dopant atoms within each of the Si-containing layers. Specifically, solid phase epitaxy is performed in the present invention at a recrystallization temperature of greater than 450° C. utilizing the underlying semiconductor region 14 of substrate 12 as a recrystallization template, with a recrystallization temperature from 550° C. to 700° C. being more preferred. In one embodiment, a preferred recrystallization temperature is 650° C. In addition to being performed at a recrystallization temperature, the solid phase epitaxy is carried out in an inert gas. The term “inert gas” as used throughout the present application denotes an ambient including at least one of helium, argon, neon, krypton, xenon and nitrogen. Preferably, the solid phase epitaxy is performed in nitrogen or argon. The duration of the solid phase epitaxy may vary depending on the number of amorphous Si-containing layers within stack 18. Typically, the solid phase epitaxy is performed for a duration of time of greater than 30 minutes, with a duration of time of greater than 1 hour being even more typical. It is observed that the solid phase epitaxy process described above maintains the dopant profile in each of the amorphous Si-containing layers. The maintenance of dopant profile in each of the layers is critical to guarantee reproducibility of the SOI layer (e.g., the monocrystalline semiconductor layer to be subsequently formed) and the buried oxide (BOX also to be subsequently formed).
After performing the solid phase epitaxy, the structure shown in
Specifically,
Porous Si can be formed by electrolytic anodization in a solution containing HF. An HF-resistant electrode, such as one made of platinum, is biased negatively, and the Si substrate is biased positively. The porosity, measured in terms of the mass loss, of the resulting porous Si layer formed in the surface of a Si wafer is proportional to the electrical current density and inversely proportional to the HF concentration. The depth of a porous Si layer formed within a region of silicon can be proportional to the anodization time for a given dopant concentration and current density. The actual structure of the porous Si, however, is a very complicated function of the type and concentration of dopants and defects, in addition to the above-mentioned parameters. A common characteristic of porous Si materials is the enormous surface area associated with high-density pores: The surface area per unit volume is estimated to be 100-200 m2 cm3, i.e., 100-200 square meters of surface area per each cubic centimeter in volume. The presence of this large surface area makes porous Si very susceptible to chemical reaction with an ambient gas such as oxygen. The oxidation rate of porous Si is found to be an order of magnitude higher than that of bulk Si. This makes porous Si a good candidate for oxide isolation.
In an example of an anodization process, anodization can be performed at room temperature or below room temperature in the dark, or with exposure to light by immersing the substrate with the series of single crystalline layers thereon in an electrolyte formed by hydrogen fluoride (HF) (which can be used from a typical commercial solution at a weight concentration of 49%, for example. The electrolyte can be prepared by dilution of the commercial HF solution in water to a lower concentration). The substrate (anode) is then connected to the positive electrode (anode) of a voltage source in order to hold the substrate at a constant potential and another electrode (cathode) of the voltage source is immersed in the electrolyte, the cathode typically including a material which is resistant to HF, such as platinum (Pt) or graphite, for example. Alternatively, the electrolyte can have a different composition, such as a mixture of HF with water, alcohol or ethylene glycol, for example, which can have a range of concentrations.
In one embodiment, the anodization process can be implemented by a constant current process at room temperature or below room temperature in HF at concentration of 49% in weight. Current density during anodization can range from one to 20 milliamperes per centimeter squared (mAcm−2). Typically anodization times can range between 10 seconds and 100 seconds. The amount of time required to perform the anodization depends upon a variety of factors, such as the dopant concentration within the Si-containing layers of stack 24, the thickness of the layers within stack 24 and the current density selected to perform the anodization. When present, the highly p-typed doped amorphous Si-containing layer 23 which is converted to a single crystalline Si-containing layer during solid phase epitaxy, aids in eliminating the formation of etch pits during anodization of the stack 24. Such pits can consume a part of the vertical height of the Si-containing layer 28 and result in structural imperfections in the SOI layer to be formed after the subsequent thermal treatment.
Following anodization, and as shown in
The oxidation step of the present invention is a dry thermal oxidation process that is performed at a temperature from 400+ C. to 1150° C., with a temperature from 800° C. to 1050° C. being more highly preferred. Moreover, the oxidation step of the present invention is carried out in an oxidizing ambient which includes at least one oxygen-containing gas such as O2, NO, N2O, ozone, air and other like oxygen-containing gases. The oxygen-containing gas may be admixed with each other (such as an admixture of O2 and NO), or the gas may be diluted with an inert gas such as He, Ar, N2, Ex, Kr, or Ne. When a diluted ambient is employed, the diluted ambient contains from 0.5% to 100% of oxygen-containing gas, the remainder, up to 100%, being inert gas. The oxidation step may be carried out for a variable period of time that typically ranges from 10 minutes to 180 minutes at 800° C. to 1050° C., with a time period from 30 minutes to 180 minutes being more highly preferred. The oxidation step may be carried out at a single targeted temperature, or various ramp and soak cycles using various ramp rates and soak times can be employed.
In some embodiments of the present invention, an inert gas carrying water vapor, O2 carrying water vapor, or steam can be used in place of the dry oxidation process mentioned above. When such “wet” oxidations are performed, they are typically performed at a temperature from 400° C. to 1000° C., with a temperature from 400° C. to 800° C. being more highly preferred. The “wet” oxidation step using the aforementioned alternative gases is advantageous in that it converts the porous Si into an oxide at an accelerated rate before it coalesces into large Si grains.
The oxidized product is then annealed at a temperature of greater than 1200° C., preferably from 1250° C. to 1325° C., in an atmosphere of inert gas (e.g., N2, Ar, Hie and other noble gases and mixtures thereof) mixed with oxygen in a concentration in the range from 2% to 20%. A chlorine-containing compound such as, for example, HCl, 1-1-1 trichloroethane (TCA) and trans-1,2 dichloroethylene (TransLC), can also be added. In one embodiment of the invention, the annealing step is performed at 1320° C. for 5 hours in Ar mixed with 2% oxygen.
During the oxidation and annealing steps, the course porous Si-containing layer 30 is converted into a buried oxide 50, while the fine porous Si-containing layer 32 is converted to a monocrystalline semiconductor layer 52. At this point of the present invention any surface oxide (not shown) that is formed during the inventive process can be removed utilizing a conventional etching process that selectively removes oxide.
The resultant SOI (see
The thickness of the BOX layer 50 can also be controlled very well. Using the techniques described herein, the BOX layer 50 can have a thickness ranging upwardly from about 10 nm. Large thicknesses are achievable by the techniques described herein, such that a BOX layer 50 having a thickness of 200 nm or more can be achieved. The thickness of the final BOX layer 50 is determined primarily by the thickness of the first p-type doped amorphous Si-containing layer prior to being made single crystalline and porous. The thickness of the final BOX layer 50 is also determined in part by the density of the porous semiconductor layer 30 from which it is formed by oxidation. Semiconductor oxide material, e.g., silicon dioxide, formed by oxidizing semiconductor material such as silicon, occupies a greater volume than the volume occupied by pure semiconductor material, since in each molecule of the semiconductor oxide material two oxygen atoms join each silicon atom of the original semiconductor material. Therefore, a layer of semiconductor material of normal density expands during oxidation to a greater volume and becomes a thicker oxide layer than the initial semiconductor layer. However, when the semiconductor material begins as a relatively porous layer, the expansion during oxidation occurs internally within the voids of the porous semiconductor layer, such that the thickness of the semiconductor oxide layer may not be much greater than the thickness of the initial semiconductor layer. In fact, the thickness of the semiconductor oxide layer may be the same as or less than the thickness of the initial semiconductor layer.
The volume occupied by pure silicon dioxide is greater than the volume occupied by pure silicon by a ratio of 2.25:1. Thus, when the proportion of silicon that remains within each porous silicon region is greater than 1/2.25 (i.e., the remaining silicon mass within the volume of the porous silicon region is greater than about 44% of the original mass), the resulting silicon dioxide expands. Another way that this can be stated is the following: the resulting silicon dioxide expands to occupy a larger volume than an original layer of silicon when porosity is less than 56%, that is, when the amount of mass removed from the defined volume of the porous silicon region is less than 56% of the starting mass. In general, the degree of porosity is higher when the boron concentration is higher, and the degree of porosity is lower when the boron concentration is lower. Also, in general, higher porosity can be achieved when the current density of the anodization process is higher. Conversely, lower porosity is achieved when the current density is lower.
As the upper and lower boundaries of the first p-type doped Si-containing layer are generally better controlled than, i.e., generally sharper than those which can defined by implantation over the surface of a wafer, the depths of the major surfaces of the buried oxide (“BOX”) layer 50 below the exposed major surface of layer 52 are also controlled well. Moreover, the major surfaces of the BOX layer 50 have surface roughness that compares to that of a BOX layer formed by implantation of oxygen and annealing. Thus, the major surfaces of the BOX layer 50 can have a root mean square surface roughness of as little as one nm or less. The amplitude of the roughness of the BOX layer 50 can be less than 3.5 nm. With appropriate process control, the surface roughness can reach a root mean square value of 0.40 nm.
The more precise control over the locations of the surfaces of the BOX layer allows processing tolerances for the thickness of the BOX layer 50 to be tightened. With the thickness of the BOX layer 50 more precisely controlled, the nominal thickness of the BOX layer can be reduced. Thus, in one embodiment, the thickness of the BOX layer 50 can be as small as 10 nm or less. The distance separating the overlying monocrystalline semiconductor layer 52 from the underlying semiconductor region 14 can be controlled to 10 nm or less.
However, the relatively small thickness of the BOX layer does not impact the dielectric strength of the BOX layer. Given a BOX layer thickness of 50 nm or less, the high quality of the BOX layer makes it possible to attain a dielectric strength of at least one megavolt per centimeter (MV cm−1). When the fabrication process is appropriately controlled, a dielectric strength of greater than eight megavolts per centimeter can be achieved and reduce the density of electrical shorts between the SOI layer and the underlying semiconductor region 100 across the BOX layer to less than about 5 cm−2 or even less than 2 cm−2, despite the BOX layer being thin at less than or equal to about 50 nanometers in thickness.
Reference is now made to
The doped Si-containing materials shown in
The doped Si-containing materials shown in
The thickness of the various doped Si-containing materials may vary depending upon the type of device being fabricated. In one embodiment of the present invention, and in solar cell production, p+ Si-containing material 60 has a thickness from 0.5 μm to 5 μm, the p− Si-containing material 62 has a thickness from 0.5 μm to 20 μm, and the n+ Si-containing material 64 has a thickness from 0.2 μm to 2 μm.
The structures shown in
While the present invention has been particularly shown and described with respect to preferred embodiments thereof it will be understood by those skilled in the art that the foregoing and other changes in forms and details may be made without departing from the spirit and scope of the present invention. It is therefore intended that the present invention not be limited to the exact forms and details described and illustrated, but fall within the scope of the appended claims.
