This application claims priority to Chinese Patent Application No. 202011280137.9 filed with the China National Intellectual Property Administration (CNIPA) on Nov. 16, 2020, the disclosure of which is incorporated herein by reference in its entirety.
The present application belongs to the technical field of semiconductor devices, for example, relates to a manufacturing method of a semiconductor device.
Silicon carbide has many characteristics that are different from traditional silicon semiconductor materials. The band gap of silicon carbide is 2.8 times that of silicon, and the insulation breakdown field strength of silicon carbide is 5.3 times that of silicon. Therefore, in a field of high-voltage power devices, compared with silicon materials, a thinner epitaxial layer may be used in a silicon carbide device so that while the silicon carbide device has the same voltage withstand level as a traditional silicon device, the silicon carbide device has a lower on-resistance. At present, the main problem of using silicon carbide to prepare a trench power device is that a large electric field is applied to a gate dielectric layer in a gate trench when the trench power device is in operation so that the gate is easily broken down and thus a voltage withstand level of the trench power device is affected.
The present application provides a manufacturing method of a semiconductor device so that a risk of breakdown of a gate of the semiconductor device can be reduced and a voltage withstand level of the semiconductor device can be improved.
The present application provides a manufacturing method of a semiconductor device. The method includes steps described below.
A semiconductor substrate is provided, where the semiconductor substrate includes a first n-type semiconductor layer, a second n-type semiconductor layer, a p-type semiconductor layer and a third n-type semiconductor layer which are stacked in turn.
Photolithography and etching are performed so that a gate trench and a source trench are formed simultaneously in the semiconductor substrate, where the gate trench and the source trench are alternately spaced apart, a bottom of the gate trench and a bottom of the source trench are both disposed in the second n-type semiconductor layer, and a width of the source trench is greater than a width of the gate trench.
A first insulating layer covering an inner wall of the gate trench and covering an inner wall of the source trench is formed.
A first conductive layer is formed and etched back, where a remaining first conductive layer after etching forms a first gate in the gate trench.
Anisotropic etching is performed on the first insulating layer so that the second n-type semiconductor layer under the source trench is exposed.
P-type ion implantation is performed so that a p-type doped region under the source trench is formed in the second n-type semiconductor layer.
The first insulating layer in the gate trench is etched so that an upper surface of the first insulating layer in the gate trench is not higher than a lower surface of the p-type semiconductor layer.
A second insulating layer is formed and etched so that a part of the second insulating layer is removed, where the part of the second insulating layer is disposed in the source trench.
A second conductive layer is formed and etched so that a remaining part of the second conductive layer after etching forms a second gate in the gate trench and forms a source in the source trench.
Optionally, the first n-type semiconductor layer, the second n-type semiconductor layer, the p-type semiconductor layer and the third n-type semiconductor layer are all silicon carbide layers.
Optionally, when the first conductive layer is formed, the first conductive layer fills the gate trench but not the source trench.
Optionally, the first gate in the gate trench is etched off before the second insulating layer is formed.
Optionally, after the part of the second insulating layer in the source trench is removed, the anisotropic etching is performed on the first insulating layer in the source trench so that the p-type semiconductor layer is exposed at a sidewall position of the source trench.
Optionally, a thickness of the first insulating layer is greater than a thickness of the second insulating layer.
Optionally, a material of the first insulating layer is silicon oxide.
Optionally, a material of the second insulating layer is at least one of silicon oxide, silicon nitride, silicon oxynitride or hafnium oxide.
Optionally, a material of the first insulating layer is conductive polysilicon.
Optionally, a material of the second conductive layer is at least one of titanium, nickel, copper, aluminum, silver, gold, titanium nitride or tungsten.
The present application provides a manufacturing method of a semiconductor device. Firstly, a gate trench and a source trench are formed simultaneously in the same etching process, a p-type semiconductor layer and a p-type doped region can be contacted in a self-aligned manner in the source trench, and the process is simple. Secondly, a first insulating layer and a first gate are formed in a lower part of the gate trench, and a second insulating layer and a second gate are formed in an upper part of the gate trench so that the thick first insulating layer can protect the second gate from being easily broken down, the first gate can increase an electric field near a bottom of the gate trench, and thus a voltage withstand level of the semiconductor device can be improved. Thirdly, a bottom of the source trench can penetrate deep into a second n-type semiconductor layer, and the p-type doped region under the source trench can increase an electric field near the bottom of the source trench, limit the highest electric field in the semiconductor device to near the bottom of the source trench, protect the second gate in the gate trench from being easily broken down, and improve the voltage withstand level of the semiconductor device.
Technical solutions of the present application are described completely hereinafter in conjunction with the drawings in embodiments of the present application. It is to be understood that the terms used in the present application such as “provided”, “comprising” and “including” do not exclude the presence of one or more other components or combinations thereof. Meanwhile, to illustrate the embodiments of the present application clearly, in the schematic views illustrated in the DRAWINGS, thicknesses of layers and regions described in the present application are enlarged, and dimensions illustrated in the views do not represent the actual dimensions.
Next, as shown in
The p-type semiconductor layer 22 between the gate trench 51 and the source trench 52 is used as a p-type body region of the semiconductor device, and the third n-type semiconductor layer 23 between the gate trench 51 and the source trench 52 is used as an n-type source region of the semiconductor device.
Next, as shown in
Next, as shown in
Next, as shown in
Next, as shown in
Next, as shown in
In the manufacturing method of a semiconductor device provided in the present application, before the second insulating layer 27 is formed, the first gate in the gate trench may be etched off, then the second insulating layer 27 is formed, finally, the second conductive layer 28 is formed. The structure of the semiconductor device formed by these steps is shown in
Number | Date | Country | Kind |
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202011280137.9 | Nov 2020 | CN | national |
Filing Document | Filing Date | Country | Kind |
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PCT/CN2020/130600 | 11/20/2020 | WO |