Patent Application
20250043460
This application claims the priority benefit of Italian patent application number 102023000016734, filed on Aug. 4, 2023, entitled “PROCESSO DI FABBRICAZIONE PER DISPOSITIVI DI POTENZA IN CARBURO DI SILICIO CON CONCENTRAZIONE DI DROGANTE VARIABILE”, which hereby incorporated by reference to the maximum extent allowable by law.
Example embodiments of the present disclosure relate to a manufacturing process for silicon carbide power devices with variable dopant concentration.
As is known, semiconductor materials having a wide bandgap, for example, greater than 1.1 eV, low ON-state resistance, high thermal conductivity, high operating frequency, and high charge-carrier saturation velocity make it possible to obtain electronic devices, such as diodes and transistors, having a higher performance than electronic devices of silicon, in particular for power applications (i.e., for operating voltages, for example, comprised between 600 V and 1300 V, or in specific operating conditions, such as high temperature).
In detail, it is known to obtain such electronic devices starting from a wafer of silicon carbide (SiC) in one of its polytypes, for example, 3C-SiC, 4H-SiC and 6H-SiC, which are distinguished by the characteristics listed above. Electronic power devices that may be obtained using semiconductors of the SiC type may, for example, be vertical-conduction MOSFETs or JFETs.
Ion implantation is today a consolidated technique for introduction of dopants into the silicon carbide. On account, in fact, of the low diffusiveness of SiC as compared to other semiconductor materials (such as silicon), diffusion of dopants may not be a convenient technique to use. Epitaxial growth might further not be an effective alternative, in particular for locally confined dopings.
As is known, in addition to the energy and the type of ions used, the crystalline structure of SiC has an effect, during implantation, on the depth distribution obtained. In fact, the so-called channelling may considerably increase the depth of penetration of f the dopant ions in the crystalline material as compared to an amorphous target. This phenomenon may occur if the direction of the incident ion beam is substantially to parallel the main crystallographic axes or planes, within ranges that are well defined and contained (i.e., within the so-called “critical channelling angle”). In these directions, the reduction of the loss of energy per length of path of the ions is smaller, with the benefit that the ions may move in greater depth in the target. In fact, when the implantation is carried out along a crystallographic axis using SiC technology, the deepest channelling ions may penetrate for a distance that is many times greater than the range expected for the corresponding random implantation, given the same implantation energy used.
In order to form implanted regions that are locally confined, both in terms of shape and in terms of doping profiles, it is known to use hard implantation masks, for example, of silicon oxide (SiO2), configured to locally shield a SiC die or chip during implantation. However, the present applicant has found that the use of hard masks may cause problems of planarity of the layer to which the mask is applied, after removal of the mask itself. The hard masks may, in fact, cause lattice stress on the SiC substrates.
Furthermore, the use of hard masks may not be compatible, i.e., may be difficult to scale, with progressive increase in the density of elementary cells that may be obtained in a same die, consequent to a decrease in the dimensions thereof (in technical jargon, “shrinkage”), i.e., consequent to a reduction of the “pitch” of the device, with the aim of increasing the current that may be extracted, in use, from the power device. In fact, in view of shrinkage of the elementary cells and of their consequent mutual approach, the processes based upon use of masks may present problems of alignment between regions belonging to layers arranged on top of one another of the die, with the possible onset of undesired electrical phenomena on account of layouts that do not correspond to the design specifications. Not least, the definition of regions of the SiC die with variable doping profiles, for the purposes of a parameterization of the electrical characteristics of the device (such as ON-state resistance, shielding from high electrical fields of the gate areas, etc.), may prove complex using implantation masks.
Consequently, the aim of various embodiments of the present disclosure is to overcome or at least mitigate the disadvantages and limitations of the prior art.
According to the various embodiments of the present disclosure, a manufacturing process for silicon carbide power devices with variable dopant concentration is provided, as defined in the annexed claims.
For a better understanding of various embodiments of the present disclosure preferred embodiments thereof are provided, by way of non-limiting example, with reference to the attached drawings, wherein:
A power device manufactured according to one embodiment of the present disclosure is illustrated in a part thereof in
The MOSFET 1 comprises a plurality of elementary cells—just one of which is illustrated in the attached figures—that are the same as one another and arranged in a same die so as to share a drain terminal D, a gate terminal G, and a source terminal S; i.e., the elementary cells are electrically connected in parallel to one another.
The MOSFET 1 is formed in a body 2 of semiconductor material. The body 2 is delimited at the top by a front side 2a and at the bottom by a back side 2b, opposite to one another in the direction of the axis Z. The body 2 may comprise a substrate or else a substrate on which one or more epitaxial layers are grown and is made of silicon carbide, in one of its polytypes, here the 4H-SiC polytype.
In one embodiment, in particular, the body 2 comprises a substrate 10, which is delimited at the bottom by the back side 2b, a first epitaxial layer 12 on the substrate 10 and a second epitaxial layer 22, which extends over the first epitaxial layer 12 and is delimited at the top by the front side 2a.
The substrate 10 is made of monocrystalline semiconductor material, for example, silicon carbide in one of its polytypes, here the polytype 4H-SiC, and has a lattice structure with spatial symmetry; the first and second epitaxial layers 12, 22 are made of the same material and preserve the same crystalline structure.
A drift region 101, a first current-spreading layer (hereafter, simply “first CSL”) 30 and a plurality of deep body regions 15 (two of which are illustrated in
The body 2 of semiconductor material of
In the first epitaxial layer 12, adjacent deep body regions 15 are separated, along the axis X, by portions of the first CSL 30 and, in the second epitaxial layer 22, adjacent shallow body regions 20 are separated, along the axis X, by portions of the second CSL 40. Further, each shallow body region 20 at least partially overlies respective deep body regions 15, being in contact therewith, and the second CSL 40 at least partially overlies the first CSL 30, being in contact therewith.
Each source region 25 extends from the front side 2a and is at least partially contained in respective shallow body regions 20. At least one of the source regions 25 of each elementary cell comprises a body-contact region 28, which extends from the front side 2a as far as the respective shallow body region 20. Further, each source region 25 and the second CSL 40 laterally delimit a channel region 27 in a respective shallow body region 20.
The deep body regions 15, the shallow body regions 20, the source regions 25, and the body-contact regions 28 extend in a direction parallel to the axis Y in the form of strips.
The superposition of the first and second epitaxial layers 12, 22 is such that, in use, i.e., when the voltage between the gate terminal G and the source terminal S (VGS) is greater than a conduction threshold voltage (VTH) of the elementary cell, a current may flow between the source terminal S and the drain terminal D, through each channel region 27, the second CSL 40 and the first CSL 30 and the drift region 101. The first and second CSLs 30, 40 form in fact enrichment layers having the function of modulating locally the resistance encountered by the charge carriers (and, more in general, of improving the value of ON-state resistance of the MOSFET 1), and the drift region 101 forms, in use, the drift layer of the charge carriers.
The body 2, and more in general the MOSFET 1 of
The deep body regions 15 and, subsequently, the first CSL 30 are formed by channelling ion implantation. Channelling implantation is obtained when the ion beam during implantation is aligned with the channelling directions: for example, in SiC, the 000-1 direction or the 11-23 direction. Typically, the substrates are cut from ingots grown in the 000-1 direction, with a surface inclined (due to cutting of the wafers) by 4° for substrates of 150 mm or 200 mm in diameter. To make channelling implantations on a 000-1 wafer the ion beam during implantation is oriented with a tilt of 4°, and for a wafer grown in the 11-23 direction with a tilt of 13° or 21°.
With reference to
According to one embodiment, the wafer 100 subsequently undergoes a step of annealing for activation of the dopant ions and for reduction of defects in the crystal lattice that may be caused by implantation.
During a third step S3 (
The present applicant has in fact found that the effect of channelling is altered by intentional damage of a surface region of the wafer 100. Said damage may be obtained, for example, by a first random ion implantation (i.e., a non-channelled one) of non-reactive or non-dopant species (indicated by arrows 120 in
Thus, according to an aspect of the present disclosure, the first damaged regions 50 are formed at the first surface 100a and are aligned with (along the axes X and Y) and defined in the respective deep body regions 15, as to alter or inhibit locally channelling in the so subsequent implantation step to form the first CSL 30. Each first damaged region 50 extends to a maximum depth, in the wafer 100 starting from the first surface 100a, comprised, for example, between 0.05 and 0.2 μm (extremes included). The thickness (depth along the axis Z) of each first damaged region 50 may be uniform or else may vary between a minimum value of 0.05 μm and a maximum value of 0.2 μm. As illustrated in
To form the first damaged regions 50 there may be used implantation doses higher than 1013 atoms/cm2 and energies sufficient to cause a displacement of the atoms from the crystalline edifice for the desired depth (for example, energy in the 30-300 keV range). The implantation that causes damage is carried out in the absence of channeling conditions, and annealing of the wafer 100 during the process is avoided so as not to remove the damage produced.
According to a further embodiment, the first damaged regions 50 are obtained by one or more steps of localized etching of the first surface 100a through the deep-body mask 105, at the deep body regions 15. For instance, a RIE (Reactive Ion Etching) process may be used with characteristics of physical etching, i.e., a plasma ion bombardment, with Ar ions. The depths that may be obtained are, for example, equal to 0.1 μm.
The lattice structure of the wafer 100 in the first damaged regions 50 is different from the lattice structure of the undamaged regions of the wafer 100. In particular, the wafer 100, in the case where it is damaged, has an amorphous structure or a disorderly crystalline structure or a lattice structure without the spatial symmetry of the portions of the wafer 100 in which the intentional damage is absent.
Once the deep-body mask 105 has been removed, the first damaged regions 50 extend over portions of the first epitaxial layer 12, where the first CSL 30 of the MOSFET 1 of
In detail, the entire wafer 100 is exposed to the second channeling ion implantation, but the first CSL 30 is obtained practically exclusively in the portions of the wafer 100 without surface damage, i.e., outside the deep body regions 15. In this way, the deep body regions 15 are shielded from the second channeling ion implantation, and, simultaneously, the first CSL 30 is defined in a self-aligned way with respect to the deep body regions 15 within the first epitaxial layer 12, as far as a desired depth determined by the implantation conditions.
The second channeling ion implantation (arrows 130) is carried out using, for example, ions of phosphorus (P) or nitrogen (N) and an implantation energy comprised between 20 keV and 2000 keV. These parameters define: the second doping level N1 between the plurality of deep body regions 15, for example, of the order of 1017 atoms/cm3 or else between 2 and 20 times the doping level of the portion of the semiconductor wafer that houses it; and a depth along the axis Z, starting from the first surface 100a, which in the MOSFET 1 is, for example, equal to the first thickness T1 of the deep body regions 15. In particular, the first doping level P1 of the deep body regions 15 and the second doping level N1 of the first CSL 30 are selected, in relation also to the total volume of the deep body regions 15 and of the first CSL 30, so that the first overall charge QP1 in the deep body regions 15 is at least five times greater than the second overall charge QN1 in the first CSL 30.
In this step, thin implanted layers with a maximum thickness of 0.3 μm may be formed in the first damaged regions 50. In other words, CSLs may be confined superficially in the damaged regions. The present applicant has found that the presence of such thin CSLs, in relation to the overlying layers formed in subsequent steps, does not affect operation of the MOSFET 1. However, as described also hereinafter, and as applied in the manufacturing process forming the subject of various embodiments of the present disclosure, to prevent possible crystallographic defects in the layers overlying the damaged regions, the first damaged regions 50 are selectively removed before the subsequent machining steps, for example, by etching of the wafer 100 in a hydrogen (H2) environment.
Processing of the first epitaxial layer 12 of the MOSFET 1 of
Next (
The wafer 100 and the second epitaxial layer 22 form a work wafer 118, which basically corresponds to the body 2 and extends between the front side 2a and the back side 2b of the body 2. The work wafer 118 is processed, as described for the steps subsequent to the fifth step S5, so as to define the structures of the MOSFET 1 present in the second epitaxial layer 22.
With reference to
In the work wafer 118 of
The first and second dimensions L1, L2 are design parameters of the MOSFET 1 corresponding to the electrical performance of the latter, as described in greater detail hereinafter. The first and second dimensions L1, L2 may thus be selected, adjusting the respective deep-body masks 105 and shallow-body masks 125, so that each deep body region 15 will alternatively have a dimension along the axis X greater than (
During a seventh step S7 (
The above damage may be obtained, for example, by a second random (i.e., non-channeled) ion implantation of non-reactive or non-dopant species (in
To form the second damaged regions 70 there may be used implantation doses higher than 1013 atoms/cm2 and energies sufficient to cause a displacement of the atoms from the crystalline edifice for the desired depth (for example, energy in the 30-300 keV range). Each second damaged region 70 extends to a maximum depth, in the second epitaxial layer 22 starting from the front side 2a, comprised, for example, between 0.05 and 0.2 μm (extremes included).
Once the shallow-body mask 125 has been removed, the damaged regions 70 extend over portions of the second epitaxial layer 22 where the second CSL 40 of the MOSFET 1 of
In detail, the entire second epitaxial layer 22 is exposed to the fourth channeling ion implantation, but formation of the second CSL 40 by channeling is obtained practically exclusively in the portions of the epitaxial layer 22 without surface damage, i.e., outside the shallow body regions 20. In this way, the shallow body regions 20 are shielded from the fourth channeling ion implantation, and, simultaneously, the second CSL 40 is defined in a self-aligned way within the second epitaxial layer 22 and with respect to the plurality of shallow body regions 20.
The fourth channeling ion implantation (arrows 160) is carried out using, for example, nitrogen or phosphorus ions and an implantation energy comprised between 20 keV and 2000 keV. Said parameters define: the fourth doping level N2 between the plurality of shallow body regions 20, for example, of the order of 1017 atoms/cm3 or else comprised between 2 and 20 times the doping level of the portion of the semiconductor layer that houses it; and a depth along the axis Z, starting from the front side 2a, that in the MOSFET 1 is, for example, equal to the second thickness T2 of the shallow body regions 20.
At the end of the fourth channeling ion implantation, the second CSL 40 of the MOSFET 1 overlies, in contact, the first CSL 30 and at least partially overlies, in contact, the deep body regions 15.
The second damaged regions 70 are then selectively removed, for example, by etching in a hydrogen environment (H2) of the work wafer 118.
In one embodiment, illustrated in
The process then proceeds with the steps S5-S8 already described.
The elementary cells of the MOSFET 1 are formed following upon the eighth step S8 of the process of manufacture of the body 2. In detail, with reference to
Each source region 25 and each body-contact region 28 extend, starting from the front side 2a of the epitaxial layer 22, in respective shallow body regions 20 and for respective depths of, for example, 0.2 μm and 2 μm. The source regions 25 have a doping level, denoted by N+, typically greater than the N doping level of the drift region 101 and of the order of 1×1018 to 1×1020 atoms/cm3, each with an extension along the axis X, for example, of 2 μm. The body-contact regions 28 have a doping, denoted by P+, of the order of 1×1018 to 1×1020 atoms/cm3.
The second layer 22 of the MOSFET 1 of
The MOSFET 1 further comprises a source-metallization region 26, for example, of metal material and/or metal silicide, which forms the source terminal S of the MOSFET 1 and extends over the front side 2a of the body 2, in direct electrical contact with the source regions 25 and the body-contact regions 28. The body-contact regions 28 are in fact used for biasing, at the electrical potential of the source terminal S, the shallow body regions 20 and thus the deep body regions 15.
Finally, the MOSFET 1 comprises a drain-metallization region 11, of conductive material, for example, a metal or a silicide, which extends over the back side 2b of the body 2 (in a direction opposite to the source-metallization region 26), in direct electrical contact with the substrate 10, and forms the drain terminal D of the MOSFET 1.
The MOSFET 1 manufactured according to the process various embodiments of the present disclosure exhibits improved electrical performance. The use of contained implantation energies, possibly thanks to the channeling phenomenon, makes it possible to obtain a reduced lateral dispersion of dopant ions and thus a profile of concentration of the dopant ions in the body 2 that may be controlled and is in conformance with what is established in the design stage. Furthermore, given that the first and second layers 12, 22 are defined using contained implantation energies, it is possible to use thin masks, for which it is easier to obtain a greater lateral definition.
The technique of resorting to intentionally damaged regions (IDRs), carried out in random implantation conditions (i.e., in the absence of channeling) on already implanted regions (here, for example, obtained with channeled implantation), makes it possible to improve further the lateral definition, in particular because regions formed in steps subsequent to the damage may be self-aligned with respect to regions already present, which present, for example, different doping levels or opposite doping levels. By altering or inhibiting channeling locally by means of the damage it is possible, in fact, to select at will the extension of the regions to be formed in subsequent steps (by means of channeling) and protect the regions already present from the subsequent channeled implantations, preserving the desired doping level thereof. The superficially damaged regions act, in fact, as implantation masks in regard to subsequent channeled implantations.
In this way, it is possible to define precisely and with lower production costs (contained implantation energies, self-alignment) doping levels, within layers (here of silicon carbide) grown epitaxially, with profiles that may be variable along the dimension of the layer itself (here, for example, in planes XY) and in the direction of the superposition of the layers (here along the axis Z).
In the MOSFET 1, this leads to a greater flexibility in defining the junction between the body regions and the drain region and in controlling the concentration of the conductive channel, with an overall benefit in terms of scalability of the MOSFET 1 in the shrinkage direction, and thus in terms of increase of the number of elementary cells.
The first and second dimensions L1, L2, like the first and second thicknesses T1, T2 and the first and third doping levels P1, P2 are in fact design parameters of the MOSFET 1 corresponding to the electrical performance of the latter. In detail, the deep body regions 15 and the shallow body regions 20 form an overall body structure that has the function of shielding the layers overlying the body 2—in particular, the gate insulating layers 36—in regard to the intense electrical fields of the body 2. An improved shielding may consequently lead to reduced switching-on voltages of the power device.
The presence of the deep body regions 15 means that, when the MOSFET 1 is in an off state and the voltage between the source terminal S and the drain terminal D (VDs) is high, for example, even higher than 400 V, the higher values of electrical field are obtained in depth in the body 2, at a distance from the front side 2a. This causes the electrical field to assume lower values in the shallower portions of the body 2 (here in the second CSL 40), in particular in the proximity of the gate insulating layers 36. Consequently, the MOSFET 1 exhibits reliable performance.
The first and second dimensions L1, L2 and, simultaneously, the first and second thicknesses T1, T2 and the first and third doping levels P1, P2 are selected so as to provide a shape to the body structure (in the MOSFET 1, for example, the shape of an upside-down T) and a doping profile that are functional to obtaining the desired electrical parameters (such as, precisely, shielding in regard to fields), also in relation to the dimensions of the individual elementary cell.
At the same time, also the first and second CSLs 30, 40 form a current-spreading structure, the dimensions of which (in relation to the shape and dimensions of the body structure) and the doping profile of which may be selected in a flexible way by means of the process according to various embodiments of the present disclosure. In particular, different dopant concentrations between the different CSLs enable effective modulation of the channel concentrations and thus of the electrical parameters of the device, further countering undesired phenomena, such as pinching, in use, of the body regions and uncontrolled variations of the ON-state resistance.
Finally, it is clear that modifications and variations may be made to what has been described and illustrated herein, without thereby departing from the scope of the present disclosure, as defined in the annexed claims.
For instance, the body structure may have shapes different from the one illustrated. The deep body regions may be less extensive (along the axis X) than the shallow body regions; in this case, the shallow body regions at least partially overlie the first CSL, in contact therewith. Alternatively, the deep body regions and the shallow body regions may have identical extension (along the axis X).
In a variant of the manufacturing process (not illustrated), the channeling ion implantations of the first and second CSLs 30, 40 are such as to define respective depths that are less or greater than the aforementioned first and second thicknesses T1, T2.
| Number | Date | Country | Kind |
|---|---|---|---|
| 102023000016734 | Aug 2023 | IT | national |
