Patent Application
20090060317
The subject matter described herein generally relates to mask defect repairs. In one embodiment, some of the techniques described herein may be utilized to repair a mask defect through wafer plane modeling.
When manufacturing integrated circuit (IC) devices, one or more photomasks may be used. Generally, a photomask may be an opaque plate with transparencies (or holes) that allow light to shine through in a defined pattern. In some implementations, photomasks may be fed into a photolithography stepper or scanner and individually selected for exposure, thereby defining one or more pattern layers for an IC device. Hence, photomask defects may result in defects in a corresponding IC device. To this end, photomasks with no detectable defects or limited defects may be essential to manufacturing of operational IC devices.
In accordance with some embodiments, techniques for repairing one or more mask defects are described. In an embodiment, the mask defect repair strategy may be determined based on wafer plane modeling that identifies contours of a corresponding wafer.
In one embodiment, an apparatus may include an image capture device to capture an image of a photomask. The apparatus may also include logic (e.g., one or more processors) to determine an updated edge location of the photomask based on the photomask image and a contour of a corresponding wafer.
In another embodiment, a method may acquire a photomask image. The method may further determine an updated edge location for the photomask based on the photomask image and a contour of a corresponding wafer.
Additional advantages, objects, and features of embodiments of the invention are set forth in part in the detailed description which follows. It is to be understood that both the foregoing general description and the following detailed description are merely exemplary of embodiments of the invention, and are merely intended to provide an overview or framework for understanding the nature and character of embodiments of the invention.
The accompanying drawings are included to provide further understanding of embodiments of the invention, illustrate various embodiments of the invention, and together with the description serve to explain the principles and operation of the invention. In the figures, the left-most digit(s) of a reference number identifies the figure in which the reference number first appears. The use of the same reference numbers in different figures indicates similar or identical items.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of embodiments of the invention. Embodiments of the invention may be practiced without some or all of these specific details. In other instances, well known process operations have not been described in detail in order not to unnecessarily obscure embodiments of the invention.
Also, reference in the specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least an implementation. The appearances of the phrase “in one embodiment” in various places in the specification may or may not be all referring to the same embodiment.
As shown in
The system 100 may additionally include a computing device 120 to control some or all of the operations of the system 100, as will be further discussed herein, for example, with reference to
Referring to
At an operation 206, it may be determined whether the simulated wafer resist contour matches the target critical dimension (CD) of the IC design (e.g., which corresponds to a physical layout of the IC design, for example, in Graphics Data System (GDS) format or DGS II format). If the simulated wafer resist contour does not match the target CD, then the mask edge contour may be modified (e.g., perturbed and/or re-optimized) at an operation 208. In an embodiment, operation 208 may modify the mask edge placement such that it simulates the resist contour at the correct edge placement or CD. For example, a line on a photomask with a correct CD may have a simulated wafer CD that is smaller than desired compared to the circuit design. The edge(s) of the line on the photomask may be modified so it is appropriated to meet the required CD on the wafer using mask repair methods. In this case the line on the mask may have met the requirement according to the mask specifications, however the simulated results may have identified a weakness in the mask design (possibly the OPC (optical proximity correction)) and calculated the amount of edge movement required to achieve the required CD on the wafer. Once the operation 206 determines that a contour match is reached, the new photomask may be used at operation 210, e.g., to correct any detected mask errors and/or for IC fabrication. For example, after correcting any detected mask defects, photomasks may be fed into a photolithography stepper or scanner and individually selected for exposure, thereby defining one or more pattern layers on a semiconductor wafer.
In an embodiment, at operation 204, software may be utilized to simulate the wafer resist contours using aerial image modeling and resist modeling. The software then may move the edge of the mask from the original position through some number of iterations until the photomask edge placement delivers the desired wafer contour (e.g., as determined at operation 206). In some embodiments, the number of iterations may be predetermined by a user and/or software (which may continue the iterations until the edge moves within a certain range of target). This approach may provide the ability to optimize the correction of these error locations on the mask to achieve the desired target CD on wafer given the lithography conditions. Hence, operations 204-208 may create a new recommended mask pattern edge placement, which may be different from that provided by the original photomask design data. Some embodiments may also take the spatial resolution of the repair system into consideration when computing the optimum edge placement. Using this new mask pattern edge placement, the errors may be corrected on the mask using conventional mask repair tools. The result may be an optimized photomask pattern at the local site of a photomask's defective location, which may be different from the original mask database, but re-optimized for best CD results on final wafer.
Various types of mask repair tools may be utilized at operation 210 such as: (1) laser ablation used for chrome removal; (2) focused ion beam used for gallium liquid metal ion source for deposition; (3) electron beam for deposition and etching; and/or (4) mechanical nano-machining for material removal. The focused ion beam (FIB) mask repair systems perform ion-induced material deposition to add gallium for pattern reconstruction. The resolution of FIB repair systems is typically 10 nm to 30 nm depending on beam energy. This spatial resolution is not as fine as the original pattern generation of the mask. Therefore, the repair is not expected to deliver the same edge placement accuracy as a pattern generator. By knowing the special resolution limits of a repair system an embodiment of the invention may perturb the edge placement under the specific resolution constraints in order to find the optimum edge placement for the repair system to use as the reference for repair.
Furthermore, in an embodiment, mask repair tools (such as system 100 of
In an embodiment, various techniques discussed herein (e.g., with respect to operations 202-208) may allow for compensation of the photomask edge placement by taking the expected transmission and phase of the mask repair into consideration before the mask repair is made (e.g., at operation 210), which may result in higher quality mask repairs, less iterations of repairs, fewer rejected repairs, and/or fewer rejected masks. Moreover, some features provided by embodiments of the invention, such those discussed with reference to method 200, may include: (a) creating repair edge placement target based on desired wafer resist contour; (b) creating repair edge placement target based on resolution limitations of the repair system; and/or (c) creating repair edge placement targets based on predicted transmission or phase errors created by the repair system at the repair location.
Some embodiments may enable the ability to: (1) repair OPC (optical proximity correction) and physical layout errors on IC designs present on the photomask after the photomask has been patterned by a pattern generator; (2) optimize the mask repair to achieve the desired wafer feature CD given the resolution limits of the defect repair system; and/or (3) optimize the mask repair to achieve the desired wafer feature CD given the expected transmission and phase error of the repair. On the contrary, current mask repair may only be capable of repairing mask errors, not OPC or physical layout errors on the mask. Mask repair has less spatial resolution than pattern generators and thus defects are not of the quality desired.
In accordance with an embodiment of the invention, the processor 302 may be a complex instruction set computer (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, a processor implementing a combination of instruction sets, or the like.
Moreover, the network interface 318 may provide communication capability with other computer systems on a same local network, on a different network connected via modems or the like to the present network, or to other computers across the Internet. In various embodiments of the invention, the network interface 318 may be implemented by utilizing technologies including, but not limited to, Ethernet, Fast Ethernet, Gigabit Ethernet (such as that covered by the Institute of Electrical and Electronics Engineers (IEEE) 801.1 standard), wide-area network (WAN), leased line (such as T1, T3, optical carrier 3 (OC3), or the like), analog modem, digital subscriber line (DSL and its varieties such as high bit-rate DSL (HDSL), integrated services digital network DSL (IDSL), or the like), cellular, wireless networks (such as those implemented by utilizing the wireless application protocol (WAP)), time division multiplexing (TDM), universal serial bus (USB and its varieties such as USB II), asynchronous transfer mode (ATM), satellite, cable modem, and/or FireWire.
Moreover, the computer system 300 may utilize operating systems such as Solaris, Windows (and its varieties such as CE, NT, 2000, XP, ME, Vista, or the like), HP-UX, IBM-AIX, PALM, UNIX, Berkeley software distribution (BSD) UNIX, Linux, Apple UNIX (AUX), Macintosh operating system (Mac OS) (including Mac OS X), or the like. Also, in certain embodiments of the invention, the computer system 300 may be a general purpose computer capable of running any number of applications.
In various embodiments of the invention, the operations discussed herein, e.g., with reference to
Additionally, such computer-readable media may be downloaded as a computer program product, wherein the program may be transferred from a remote computer (e.g., a server) to a requesting computer (e.g., a client) by way of data signals embodied in a carrier wave or other propagation medium via a communication link (e.g., a modem or network connection). Accordingly, herein, a carrier wave shall be regarded as comprising a machine-readable medium.
In the description and claims, the terms “coupled” and “connected,” along with their derivatives, may be used. In some embodiments of the invention, “connected” may be used to indicate that two or more elements are in direct physical contact with each other. “Coupled” may mean that two or more elements are in direct physical contact. However, “coupled” may also mean that two or more elements may not be in direct contact with each other, but may still cooperate or interact with each other.
Although embodiments have been described in language specific to structural features and/or methodological acts, it is to be understood that claimed subject matter may not be limited to the specific features or acts described. Rather, the specific features and acts are disclosed as sample forms of implementing various embodiments. While the invention has been described above in conjunction with one or more specific embodiments, it should be understood that the invention is not intended to be limited to one embodiment. The invention is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the invention, such as those defined by the appended claims.
