MASK ROM AND PROCESS FOR FABRICATING THE SAME

Abstract

A Mask ROM is shown, including first resistors as a first part of memory cells, second resistors as a second part of memory cells, and contact plugs. Each first resistor includes: an undoped first poly-Si layer including a convex portion and a step structure with a step height adjacent to the convex portion, a spacer on the sidewall of the step structure, and a first silicide layer on the first poly-Si layer and being divided apart by the spacer. Each second resistor includes an undoped second poly-Si layer, and a contiguous second silicide layer on the second poly-Si layer. The contact plugs are disposed on the first silicide layer on the convex portion of each first poly-Si layer, and on the second silicide layer.

Description

BACKGROUND OF THE INVENTION

Field of Invention

This invention relates to a semiconductor apparatus, and particularly relates to a structure of a Mask ROM (read-only memory) and a process for fabricating the same.

Description of Related Art

A conventional Mask ROM includes MOS transistors as memory cells, where bit-line contact plugs are formed on source/drain (S/D) regions of the MOS transistors. However, current leakage easily occurs if a contact plug is misaligned, and the memory cell constituted of a MOS transistor occupies a large lateral area.

SUMMARY OF THE INVENTION

Accordingly, this invention provides a Mask ROM in which resistors instead of MOS transistors serve as memory cells.

This invention also provides a process for fabricating the Mask ROM.

The Mask ROM of this invention is shown, including first resistors as a first part of memory cells, second resistors as a second part of memory cells, and contact plugs. Each first resistor includes: an undoped first poly-Si layer including a convex portion and a step structure with a step height adjacent to the convex portion, a spacer on the sidewall of the step structure, and a first silicide layer on the first poly-Si layer and being divided apart by the spacer. Each second resistor includes an undoped second poly-Si layer, and a contiguous second silicide layer on the second poly-Si layer. The contact plugs are disposed on the first silicide layer on the convex portion of each first poly-Si layer, and on the second silicide layer.

In an embodiment of the Mask ROM of this invention, each first resistor further includes a material layer that is under the convex portion of the first poly-Si layer and causes the step height. The material layer may include an insulating layer.

The process for fabricating the Mask ROM of this invention includes the steps below. A plurality of undoped first poly-Si layers and a plurality of undoped second poly-Si layers are formed, wherein each first poly-Si layer includes a convex portion and a step structure with a step height adjacent to the convex portion. A spacer is formed on the sidewall of the step structure of each first poly-Si layer. A salicide (self-aligned silicide) process is performed to form a first silicide layer on each first poly-Si layer and a second silicide layer on each second poly-Si layer, wherein the first silicide layer is divided apart by the spacer to be non-contiguous on the first poly-Si layer, and the second silicide layer is contiguous on the second poly-Si layer. A plurality of contact plugs are formed on the first silicide layers on the convex portions of the first poly-Si layers, and on the second silicide layers.

In an embodiment, the process of this invention further includes: forming, before the first and the second poly-Si layers are forming, a patterned material layer for causing the step height. After the first and the second poly-Si layers are formed, the convex portion of each first poly-Si layers is located on the patterned material layer.

Since resistors are utilized as memory cells and the bit-line contact plugs are formed on the resistors in the Mask ROM of this invention, current leakage can be prevented even if a contact plug is misaligned. Moreover, the lateral area occupied by a resistor is remarkably smaller than the lateral area occupied by a MOS transistor in a conventional Mask ROM.

In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, a preferred embodiment accompanied with figures is described in detail below.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1 to 5 illustrate, in a top view as well as a cross-sectional view, a process for fabricating a Mask ROM according to an embodiment of this invention, wherein FIG. 5 also illustrates the structure of the Mask ROM according to the embodiment.

FIG. 2-1 illustrates an alternative for the structure of the substrate of the Mask ROM according to an embodiment of this invention.

DESCRIPTION OF EMBODIMENTS

This invention will be further explained with the following embodiments and the accompanying drawings, which are however not intended to restrict the scope of this invention. For example, though in the embodiments the poly-Si part of the word lines are formed simultaneously with the poly-Si layers of the resistor memory cells and the silicide part of the word lines are faulted simultaneously with the silicide layers of the resistor memory cells, in other embodiments, word lines may alternatively be formed over the silicide layers of the resistor memory cells after the silicide layers are formed.

FIGS. 1 to 5 illustrate, in a top view as well as a cross-sectional view, a process for fabricating a Mask ROM according to an embodiment of this invention, wherein FIG. 5 also illustrates the structure of the Mask ROM according to the embodiment.

Referring to FIG. 1, a patterned material layer 102 is formed over a substrate 100, in order to cause the step structure of each first poly-Si layer in the subsequent process. The substrate 100 may include a field oxide (FOX) layer that is formed on a semiconductor substrate, or include a semiconductor substrate. The material layer 102 may include an insulating layer, for example. The insulating layer may include, for example, a pad oxide layer and an SiN layer on the pad oxide layer.

Referring to FIG. 2, a plurality of undoped first poly-Si layers 104a, a plurality of undoped second poly-Si layers 104b, and a plurality of undoped third poly-Si layers 104c for forming word lines later are formed over the substrate 100 and the material layer 102. Each first poly-Si layer 104a includes a non-convex portion 104a-1 that is connected with a third poly-Si layer 104c that is for forming a word line later, a convex portion 104a-2 on the material layer 102, and a step structure 1041 with a step height “h” adjacent to the convex portion 104a-2, due to presence of the material layer 102. Each second poly-Si layer 104b includes a first portion 104b-1 that is connected with a third poly-Si layer 104c that is for forming a word line later, and a second portion 104b-2.

The first poly-Si layers 104a, the second poly-Si layers 104b and the third poly-Si layers 104c are undoped and do not require doping because a silicide layer will be formed on each of them later for electrical connection. The step height h may range from 300 Å to 500 Å. In addition, the first poly-Si layers 104a, the second poly-Si layers 104b and the third poly-Si layers 104c may possibly be formed simultaneously with the poly-Si gate electrodes of logic devices (not shown).

When the substrate 100 includes include a semiconductor substrate, the first poly-Si layers 104a, the second poly-Si layers 104b and the third poly-Si layers 104c are preferably formed after an insulating layer 106 is formed over the substrate 100, as shown in FIG. 2-1. The insulating layer 106 may be formed simultaneously with the gate dielectric of logic devices (not shown).

Referring to FIG. 3, a spacer 108a is formed on the sidewall of the step structure 1041 of each first poly-Si layer 104a, while spacers 108b are formed on the other sidewalls that are present on the substrate 100.

Referring to FIGS. 3 & 4, a salicide (self-aligned silicide) process is performed to form a first silicide layer 110a on each first poly-Si layer 104a, a second silicide layer 110b on each second poly-Si layer 104b, and a third silicide layer 110c on each third poly-Si layer 104c. The first silicide layer 110a is divided apart by the spacer 108a to be non-contiguous on the first poly-Si layer 104a. The second silicide layer 110b is contiguous on the second poly-Si layer 104b.

Each third silicide layer 110c and the underlying third poly-Si layer 104c serve as a word line. Each first silicide layer 110a includes a first portion 110a-1 that is on the non-convex portion 104a-1 of a first poly-Si layer 104a and is connected with a word line 110c, and a second portion 110a-2 that is on the convex portion 104a-2 of the first poly-Si layer 104a and is disconnected from the first portion 110a-1 due to presence of the spacer 108a. Each second silicide layer 110b includes a first portion 110b-1 that is connected with a word line 110c, and a second portion 110b-2 that is connected with the first portion 110b-1. Thereby, a plurality of first resistors 12 each based on a non-contiguous silicide layer 110a, and a plurality of second resistors 14 each based on a contiguous silicide layer 110b are made, serving as a first part of memory cells that represent “1” (or “0”) and a second part of memory cells that represent “0” (or “1”), respectively.

Referring to FIG. 5, a plurality of contact plugs 112 are formed on the second portions 110a-2 of the first silicide layers 110a on the convex portions 104a-2 of the first poly-Si layers 104a, and on the second portions 110b-2 of the second silicide layers 110b. A plurality of bit lines 114 are formed, each being connected with the contact plugs 112 of a column of resistors 12/14.

For a first resistor 12 that is based on a non-contiguous silicide layer 110a, because the corresponding word line 110c and the corresponding bit line 114 are connected with disconnected portions 110a-1 and 110a-2 of the non-contiguous silicide layer 110a, respectively, a current cannot flow between the corresponding word line 110c and the corresponding bit line 114. On the contrary, for a second resistor 14 that is based on a contiguous silicide layer 110b, because the corresponding word line 110c and the corresponding bit line 114 are connected with connected portions 110b-1 and 110b-2 of the contiguous silicide layer 110b, respectively, a current can flow between the corresponding word line 110c and the corresponding bit line 114. Thus, it is possible that each first resistor 12 represents “1” and each second resistor 14 represents “0”, or each first resistor 12 represents “0” and each second resistor 14 represents “1”.

Since resistors are utilized as memory cells and the bit-line contact plugs are formed on the resistors in the Mask ROM of this invention, current leakage can be prevented even if a contact plug is misaligned.

Moreover, the lateral area occupied by a resistor is remarkably smaller than the lateral area occupied by a MOS transistor in a conventional Mask ROM.

This invention has been disclosed above in the embodiments, but is not limited to those. It is known to people of ordinary skill in the art that some modifications and innovations may be made without departing from the spirit and scope of this invention. Hence, the scope of this invention should be defined by the following claims.

Claims

1. A Mask ROM, comprising: a plurality of first resistors as a first part of memory cells, each of which includes an undoped first poly-Si layer including a convex portion and a step structure with a step height adjacent to the convex portion, a spacer on a sidewall of the step structure, and a first silicide layer on the undoped first poly-Si layer, wherein the first silicide layer is divided apart by the spacer to be non-contiguous;a plurality of second resistors as a second part of the memory cells, each of which includes an undoped second poly-Si layer and a contiguous second silicide layer on the undoped second poly-Si layer; anda plurality of contact plugs, disposed on the first silicide layer on the convex portion of each undoped first poly-Si layer, and on the second silicide layer.

2. The Mask ROM of claim 1, wherein each first resistor further includes a material layer that is under the convex portion of the undoped first poly-Si layer and causes the step height.

3. The Mask ROM of claim 2, wherein the material layer comprises an insulating layer.

4. The Mask ROM of claim 3, wherein the insulating layer comprises a pad oxide layer and an SiN layer on the pad oxide layer.

5. The Mask ROM of claim 1, wherein first portions of the second silicide layer and the first silicide layer on non-convex portions of the undoped first poly-Si layers are connected with a plurality of word lines, and second portions of the second silicide layer and the first silicide layer on the convex portions of the undoped first poly-Si layers are connected with a plurality of bit lines.

6. The Mask ROM of claim 1, wherein the first resistors and the second resistors are disposed on a field oxide (FOX) layer.

7. The Mask ROM of claim 1, wherein the first resistors and the second resistors are disposed on a semiconductor substrate and separated from the semiconductor substrate by an insulating layer.

8. The Mask ROM of claim 7, wherein the insulating layer is formed simultaneously with gate dielectric of logic devices.

9. The Mask ROM of claim 1, wherein the undoped first poly-Si layers and the undoped second poly-Si layers are formed simultaneously with poly-Si gate electrodes of logic devices.

10. The Mask ROM of claim 1, wherein the step height ranges from 300 Å to 500 Å.

11. A process for fabricating a Mask ROM, comprising: forming a plurality of undoped first poly-Si layers and a plurality of undoped second poly-Si layers, wherein each undoped first poly-Si layer includes a convex portion and a step structure with a step height adjacent to the convex portion;forming a spacer on a sidewall of the step structure of each undoped first poly-Si layer;performing a salicide process to form a first silicide layer on each undoped first poly-Si layer and a second silicide layer on each undoped second poly-Si layer, wherein the first silicide layer is divided apart by the spacer to be non-contiguous on the undoped first poly-Si layer, and the second silicide layer is contiguous on the undoped second poly-Si layer; andforming a plurality of contact plugs on the first silicide layers on the convex portions of the undoped first poly-Si layers, and on the second silicide layers.

12. The process of claim 11, further comprising: forming, before the undoped first poly-Si layers and the undoped second poly-Si layers are formed, a patterned material layer for causing the step height,wherein the convex portion of each undoped first poly-Si layers is located on the patterned material layer.

13. The process of claim 12, wherein the material layer comprises an insulating layer.

14. The process of claim 13, wherein the insulating layer comprises a pad oxide layer and an SiN layer on the pad oxide layer.

15. The process of claim 11, further comprising: forming a plurality of third poly-Si layers simultaneously with the undoped first poly-Si layers and the undoped second poly-Si layers, wherein the third poly-Si layers are connected with first portions of the undoped second poly-Si layers and non-convex portions of the undoped first poly-Si layers;forming a plurality of silicide word lines simultaneously with the first silicide layers and the second silicide layers, wherein the word lines are connected with first portions of the second silicide layers and the first silicide layers on the non-convex portions of the undoped first poly-Si layers; andforming a plurality of bit lines that are connected with second portions of the second silicide layers and the first silicide layer on the convex portions of the undoped first poly-Si layers.

16. The process of claim 11, wherein the undoped first poly-Si layers and the undoped second poly-Si layers are formed on a field oxide (FOX) layer.

17. The process of claim 11, wherein the undoped first poly-Si layers and the undoped second poly-Si layers are formed on a semiconductor substrate after an insulating layer is formed on the semiconductor substrate.

18. The process of claim 17, wherein the insulating layer is formed simultaneously with gate dielectric of logic devices.

19. The process of claim 11, wherein the undoped first poly-Si layers and the undoped second poly-Si layers are formed simultaneously with poly-Si gate electrodes of logic devices.

20. The process of claim 11, wherein the step height ranges from 300 Å to 500 Å.