Patent Grant
10797055
The present invention relates to semiconductor memory technology. More specifically, the present invention relates to a semiconductor memory device comprising an electrically floating body transistor and an access transistor.
Semiconductor memory devices are used extensively to store data. Memory devices can be characterized according to two general types: volatile and non-volatile. Volatile memory devices such as static random access memory (SRAM) and dynamic random access memory (DRAM) lose data that is stored therein when power is not continuously supplied thereto.
DRAM based on the electrically floating body effect has been proposed (see for example “A Capacitor-less 1T-DRAM Cell”, S. Okhonin et al., pp. 85-87, IEEE Electron Device Letters, vol. 23, no. 2, February 2002 and “Memory Design Using One-Transistor Gain Cell on SOI”, T. Ohsawa et al., pp. 152-153, Tech. Digest, 2002 IEEE International Solid-State Circuits Conference, February 2002). Such memory eliminates the capacitor used in the conventional 1T/1C memory cell, and thus is easier to scale to smaller feature size. In addition, such memory allows for a smaller cell size compared to the conventional 1T/1C memory cell.
Widjaja and Or-Bach describes a bi-stable SRAM cell incorporating a floating body transistor, where more than one stable state exists for each memory cell (for example as described in U.S. Patent Application Publication No. 2010/00246284 to Widjaja et al., titled “Semiconductor Memory Having Floating Body Transistor and Method of Operating” and U.S. Patent Application Publication No. 2010/0034041, “Method of Operating Semiconductor Memory Device with Floating Body Transistor Using Silicon Controlled Rectifier Principle”, which are both hereby incorporated herein, in their entireties, by reference thereto). This bi-stability is achieved due to the applied back bias which causes impact ionization and generates holes to compensate for the charge leakage current and recombination.
In a memory array comprising rows and columns of memory cells, performing an operation on a memory cell may trigger a change in its surrounding memory cells, a condition often referred to as disturb. There is a continuing need for improving disturb resistance in memory cells. Two-transistor memory cells, for example as described in “Capacitorless Twin-Transistor Random Access Memory (TTRAM) on SOI”, F. Morishita et al, Custom Integrated Circuits Conference, 2005, pp. 435-438, “A configurable enhanced TTRAM macro for system-level power management unified memory”, F. Morishita et al., Solid-State Circuits, IEEE Journal of, vol. 42 no. 4 (2007), pp. 853-861, “A high-density scalable twin transistor RAM (TTRAM) with verify control for SOI platform memory IPs”, K. Arimoto et al., Solid-State Circuits, IEEE Journal of, vol. 42, no. 11 (2007), pp. 2611-2619, and “A Scalable ET2RAM (SETRAM) with Verify Control for SoC Platform Memory IP on SOI”, K. Arimoto et al. pp. 429-432, Custom Integrated Circuits Conference, 2006, which are hereby incorporated herein, in their entireties, may improve the disturb resistance of the memory cells.
The present invention address the continuing need for improving disturb resistance by providing an improvement of disturb resistance during memory cell operation by incorporating an access transistor.
In one aspect of the present invention, a semiconductor memory cell includes: a bi-stable floating body transistor; and an access device; wherein the bi-stable floating body transistor and said access device are electrically connected in series.
In at least one embodiment, the access device comprises a metal-oxide-semiconductor transistor.
In at least one embodiment, the access device comprises a bipolar transistor.
In at least one embodiment, the access transistor is of the same conductivity type as the bi-stable floating body transistor.
In at least one embodiment, the access transistor has a conductivity type different from a conductivity type of the bi-stable floating body transistor.
In at least one embodiment, the bi-stable floating body transistor comprises a buried well region.
In at least one embodiment, the bi-stable floating body transistor comprises a multiple port floating body transistor, and the access device comprises multiple access transistors.
In at least one embodiment, the bi-stable floating body transistor comprises a dual-port floating body transistor, and the access device comprises two access transistors.
In another aspect of the present invention, a semiconductor memory cell includes: a first transistor having a first body; a second transistor having a second body; a substrate underlying both of the first and second bodies; a buried layer interposed between the substrate and at least one of the first and second bodies; a first source region contacting the first body; a first drain region separated from the first source line region and contacting the first body; a first gate insulated from the first body; an insulating member insulating the first body from the second body; a second source region contacting the second body; a second drain region separated from the second source region and contacting the second body; and a second gate insulated from the second body.
In at least one embodiment, the first gate is positioned between the first source region and the first drain region and the second gate is positioned between the second source region and the second drain region.
In at least one embodiment, the first transistor is a floating body transistor and the second transistor is an access transistor.
In at least one embodiment, the first body is a floating body and the second body is a well region electrically connected to the substrate.
In at least one embodiment, the first drain region is electrically connected to the second source region.
In at least one embodiment, the first body has a first conductivity type selected from p-type conductivity type and n-type conductivity type, wherein the second body has the first conductivity type, and wherein the first and second source regions and first and second drain regions each have a second conductivity type selected from the p-type conductivity type and n-type conductivity type, and wherein the first conductivity type is different from the second conductivity type.
In at least one embodiment, the first body is a floating body and the second body is a well region electrically connected to the buried layer, wherein the first body has a first conductivity type selected from p-type conductivity type and n-type conductivity type, and wherein the second body has a second conductivity type selected from the p-type conductivity type and n-type conductivity type, and wherein the first conductivity type is different from the second conductivity type.
In at least one embodiment, the semiconductor memory cell comprises a reference cell, the reference cell further comprising: a sense line region spaced apart from the first source region and the first drain region and contacting the first body, wherein the first body has a first conductivity type selected from p-type conductivity type and n-type conductivity type, and wherein the sense line region has the first conductivity type.
In at least one embodiment, the first drain region is electrically connected to the second gate.
In at least one embodiment, the first transistor is a floating body transistor and the second transistor is a floating body transistor.
In at least one embodiment, the first and second floating body transistors are configured to store complementary charges.
In at least one embodiment, at least one of the first and second bodies is a bi-stable floating body.
In another aspect of the present invention, a semiconductor memory cell includes: a first transistor having a floating body; a buried layer below the floating body, wherein application of voltage on the buried layer maintains a state of the memory cell; and a second transistor; wherein the first and second transistors are connected in series.
In another aspect of the present invention, a semiconductor memory cell includes: a bi-stable floating body transistor; and a floating gate transistor.
In another aspect of the present invention, a semiconductor memory cell includes: a first bi-stable floating body transistor; and a second bi-stable floating body transistor; wherein the first and second floating body transistors are configured to store complementary charges.
In another aspect of the present invention, a method of operating a semiconductor memory cell having a bi-stable floating body transistor and an access transistor includes: applying voltage to the access transistor to turn on the access transistor; and assisting selection of the memory cell for an operation by activating the access transistor.
In at least one embodiment, the operation is a read operation comprising monitoring current through the memory cell to sense a state of the floating body transistor.
In at least one embodiment, the operation is a write logic-1 operation, wherein the voltage applied to the access transistor is a positive bias applied to a bit line terminal of the access transistor, and wherein the access transistor passes the positive bias to a drain region of the floating body transistor.
In at least one embodiment, the method further includes further biasing the floating body transistor to maximize hole generation through an impact ionization mechanism.
In at least one embodiment, the voltage applied to the access transistor is biased to cause a source region of the access transistor to float, the method further comprising increasing potential of a floating body of the floating body transistor by capacitive coupling.
In at least one embodiment, the operation is a write logic-0 operation, wherein the voltage applied to the access transistor is a negative bias, and wherein the access transistor passes the negative bias to a drain region of the floating body transistor.
In at least one embodiment, the operation is an active low read operation.
In at least one embodiment, the operation is an active low write logic-1 operation.
In at least one embodiment, the operation is a read operation comprising monitoring current through the memory cell to sense a state of the floating body transistor; and wherein the voltage applied to turn on the access transistor is zero voltage.
In at least one embodiment, the operation is a write logic-1 operation, wherein the voltage applied to the access transistor comprises applying zero voltage to a word line terminal of the access transistor, and the write logic-1 operation is performed by a band-to-band tunneling mechanism.
In at least one embodiment, the operation is a write logic-1 operation, wherein the voltage applied to the access transistor comprises applying zero voltage to a word line terminal of the access transistor, and the write logic-1 operation is performed by through an impact ionization mechanism.
In at least one embodiment, the operation is a write logic-1 operation, and the voltage applied to the access transistor is a positive voltage biased to cause a source region of the access transistor to float, the method further comprising increasing potential of a floating body of the floating body transistor by capacitive coupling.
In at least one embodiment, the operation is a write logic-0 operation, wherein the voltage applied to the access transistor is a positive bias applied to a word line terminal of the access transistor.
In at least one embodiment, the operation is a write logic-0 operation, wherein the voltage applied to the a word line terminal of the access transistor is a negative bias that is more negative than a negative bias applied to a drain region of the floating body transistor.
These and other features of the invention will become apparent to those persons skilled in the art upon reading the details of the memory devices and methods as more fully described below.
Before the present memory devices and methods are described, it is to be understood that this invention is not limited to particular embodiments described, as such may, of course, vary. It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to be limiting, since the scope of the present invention will be limited only by the appended claims.
Where a range of values is provided, it is understood that each intervening value, to the tenth of the unit of the lower limit unless the context clearly dictates otherwise, between the upper and lower limits of that range is also specifically disclosed. Each smaller range between any stated value or intervening value in a stated range and any other stated or intervening value in that stated range is encompassed within the invention. The upper and lower limits of these smaller ranges may independently be included or excluded in the range, and each range where either, neither or both limits are included in the smaller ranges is also encompassed within the invention, subject to any specifically excluded limit in the stated range. Where the stated range includes one or both of the limits, ranges excluding either or both of those included limits are also included in the invention.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Although any methods and materials similar or equivalent to those described herein can be used in the practice or testing of the present invention, the preferred methods and materials are now described. All publications mentioned herein are incorporated herein by reference to disclose and describe the methods and/or materials in connection with which the publications are cited.
It must be noted that as used herein and in the appended claims, the singular forms “a”, “an”, and “the” include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to “a cell” includes a plurality of such cells and reference to “the terminal” includes reference to one or more terminals and equivalents thereof known to those skilled in the art, and so forth.
The publications discussed herein are provided solely for their disclosure prior to the filing date of the present application. Nothing herein is to be construed as an admission that the present invention is not entitled to antedate such publication by virtue of prior invention. Further, the dates of publication provided may be different from the actual publication dates which may need to be independently confirmed.
A schematic cross-sectional view of a memory device 100 according to an embodiment of the present invention is shown in
Floating body transistor 40 also comprises a buried layer region 30 of a second conductivity type, such as n-type, for example; a floating body region 24 of the first conductivity type, such as p-type, for example; and source/drain regions 16 and 18 of the second conductivity type, such as n-type, for example.
Buried layer 30 may be formed by an ion implantation process on the material of substrate 10. Alternatively, buried layer 30 can be grown epitaxially on top of substrate 10.
The floating body region 24 of the first conductivity type is bounded on top by surface 14, source line region 16, drain region 18, and insulating layer 62, on the sides by insulating layer 26, and on the bottom by buried layer 30. Floating body 24 may be the portion of the original substrate 10 above buried layer 30 if buried layer 30 is implanted. Alternatively, floating body 24 may be epitaxially grown. Depending on how buried layer 30 and floating body 24 are formed, floating body 24 may have the same doping as substrate 10 in some embodiments or a different doping, if desired in other embodiments.
A gate 60 is positioned in between the source line region 16 and the drain region 18, above the floating body region 24. The gate 60 is insulated from the floating body region 24 by an insulating layer 62. Insulating layer 62 may be made of silicon oxide and/or other dielectric materials, including high-K dielectric materials, such as, but not limited to, tantalum peroxide, titanium oxide, zirconium oxide, hafnium oxide, and/or aluminum oxide. The gate 60 may be made of, for example, polysilicon material or metal gate electrode, such as tungsten, tantalum, titanium and their nitrides.
Insulating layers 26 (like, for example, shallow trench isolation (STI)), may be made of silicon oxide, for example, though other insulating materials may be used. Insulating layers 26 insulate floating body transistor 40 from adjacent floating body transistor 40 and adjacent access transistor 42. The bottom of insulating layer 26 may reside inside the buried region 30 allowing buried region 30 to be continuous as shown in
Access transistor 42 comprises a well region 12 of the first conductivity type, such as p-type, source region 20 and bit line region 22 of the second conductivity type, such as n-type. The well region 12 of the first conductivity type is electrically connected to the substrate region 10, and is therefore not floating. A gate 64 is positioned in between the source region 20 and the bit line region 22. The gate 64 is insulated from the well region 12 by an insulating layer 66. Insulating layer 66 may be made of silicon oxide and/or other dielectric materials, including high-K dielectric materials, such as, but not limited to, tantalum peroxide, titanium oxide, zirconium oxide, hafnium oxide, and/or aluminum oxide. The gate 64 may be made of, for example, polysilicon material or metal gate electrode, such as tungsten, tantalum, titanium and their nitrides.
The drain region 18 of the floating body transistor 40 is connected to the source region 20 of the access transistor 42 through a conductive element 94. Conductive element 90 connects the source line region 16 of the floating body transistor 40 (which may be referred to as the source line region 16 of the memory device 100 interchangeably) to the source line (SL) terminal 74, while conductive element 92 connects the bit line region 22 of the access transistor (which may be referred to as the bit line region 22 of the memory device 100 interchangeably) to the bit line (BL) terminal 76. The conductive elements 90, 92, and 94 may be formed of, but not limited to, tungsten or silicided silicon.
In addition to the SL terminal 74 and BL terminal 76, memory cell 100 also includes word line 1 (WL1) terminal 70, which is electrically connected to the gate 60 of the floating body transistor 40, word line 2 (WL2) terminal 72, which is electrically connected to the gate 64 of the access transistor 42, buried well (BW) terminal 78, which is electrically connected to the buried well region 30 of the floating body transistor 40, and substrate (SUB) terminal 80, which is connected to the substrate region 10.
In an alternative embodiment illustrated in
Also inherent in floating body transistor 40 is bipolar device 48, formed by the source line region 16, floating body region 24, and the drain region 18. For drawings clarity, bipolar device 48 is shown separately in
A memory array comprising a plurality of the memory cells 100 as illustrated in
Present in
Several operations can be performed to memory cell 100, such as: holding, read, write logic-1 and write logic-0 operations.
In one embodiment the bias conditions for the holding operation for memory cell 100 are: 0.0 volts is applied to WL1 terminal 70, WL2 terminal 72, SL terminal 74, BL terminal 76, and SUB terminal 78, and a positive voltage like, for example, +1.2 volts is applied to BW terminal 78. In other embodiments, different voltages may be applied to the various terminals of memory cell 100 as a matter of design choice and the exemplary voltages described are not limiting in any way.
From the equivalent circuit representation of memory cell 100 shown in
The region where the product β×(M−1) approaches 1 and is characterized by hole current moving into the base region of a bipolar transistor is sometimes referred to as the reverse base current region and has been described for example in “A New Static Memory Cell Based on Reverse Base Current (RBC) Effect of Bipolar Transistor”, K. Sakui et al., pp. 44-47, International Electron Devices Meeting, 1988 (“Sakui-1”), “A New Static Memory Cell Based on the Reverse Base Current Effect of Bipolar Transistors”, K. Sakui et al., pp. 1215-1217, IEEE Transactions on Electron Devices, vol. 36, no. 6, June 1989 (“Sakui-2”), “On Bistable Behavior and Open-Base Breakdown of Bipolar Transistors in the Avalanche Regime—Modeling and Applications”, M. Reisch, pp. 1398-1409, IEEE Transactions on Electron Devices, vol. 39, no. 6, June 1992 (“Reisch”), which are hereby incorporated herein, in their entireties, by reference thereto.
The latching behavior based on the reverse base current region has also been described in a biristor (i.e. bi-stable resistor) for example in “Bistable resistor (Biristor)—Gateless Silicon Nanowire Memory”, J.-W. Han and Y.-K. Choi, pp. 171-172, 2010 Symposium on VLSI Technology, Digest of Technical Papers, 2010 “(“J.-W. Han”), which is hereby incorporated herein, in its entirety, by reference thereto. In a two-terminal biristor device, a refresh operation is still required. J.-W. Han describes a 200 ms data retention for the silicon nanowire biristor memory. In memory cell 100, the state of the memory cell is maintained due to the vertical bipolar transistors 44 and 46, while the remaining cell operations (i.e. read and write operations) are governed by the lateral bipolar transistor 48 and MOS transistor 40. Hence, the holding operation does not require any interruptions to the memory cell 100 access.
If floating body 24 is neutrally charged (the voltage on floating body 24 being equal to the voltage on grounded source line region 16), a state corresponding to logic-0, no current will flow through bipolar transistors 44 and 46. The bipolar devices 44 and 46 will remain off and no impact ionization occurs. Consequently memory cells in the logic-0 state will remain in the logic-0 state.
An autonomous refresh for a floating body memory, without requiring to first read the memory cell state, has been described for example in “Autonomous Refresh of Floating Body Cell (FBC)”, Ohsawa et al., pp. 801-804, International Electron Device Meeting, 2008 (“Ohsawa”), U.S. Pat. No. 7,170,807 “Data Storage Device and Refreshing Method for Use with Such Device”, Fazan et al. (“Fazan”), which are hereby incorporated herein, in their entireties, by reference thereto. Ohsawa and Fazan teach an autonomous refresh method by applying periodic gate and drain voltage pulses, which interrupt access to the memory cells being refreshed. In memory cell 100, more than one stable state is achieved because of the vertical bipolar transistors 44 and 46. The read and write operations of the memory cell 100 are governed by the lateral bipolar transistor 48 and MOS transistor 40. Hence, the holding operation does not require any interruptions to the memory cell 100 access.
In the holding operation described in
The holding operation results in the floating body memory cell having two stable states: the logic-0 state and the logic-1 state separated by an energy barrier, which are represented by VFB0, VFB1, and VTS, respectively.
The values of the floating body 24 potential where the current changes direction, i.e. VFB0, VFB1, and VTS, can be modulated by the potential applied to the BW terminal 78. These values are also temperature dependent.
The holding/standby operation also results in a larger memory window by increasing the amount of charge that can be stored in the floating body 24. Without the holding/standby operation, the maximum potential that can be stored in the floating body 24 is limited to the flat band voltage VFB as the junction leakage current to regions 16 and 18 increases exponentially at floating body potential greater than VFB. However, by applying a positive voltage to BW terminal 78, the bipolar action results in a hole current flowing into the floating body 24, compensating for the junction leakage current between floating body 24 and regions 16 and 18. As a result, the maximum charge VMC stored in floating body 24 can be increased by applying a positive bias to the BW terminal 78 as shown in
Floating body DRAM cells described in Ranica-1, Ranica-2, Villaret, and Pulicani only exhibit one stable state, which is often assigned as logic-0 state. Villaret describes the intrinsic bipolar transistors enhance the data retention of logic-1 state, by drawing the electrons which otherwise would recombine with the holes stored in the floating body region. However, only one stable state is observed because there is no hole injection into the floating body region to compensate for the charge leakage and recombination.
In one embodiment, the following bias conditions are applied for the alternative holding operation: 0.0 volts is applied to WL1 terminal 70, WL2 terminal 72, SL2 terminal 74, BL terminal 76; a positive voltage like, for example, +1.2 volts is applied to SUB terminal 80; while the BW terminal 78 is left floating. In other embodiments, different voltages may be applied to the various terminals of memory cell 100 as a matter of design choice and the exemplary voltages described are not limiting in any way. Alternatively, the BW terminal 78 may be eliminated from the array 120, leaving the buried well region 30 floating.
Applications of the back bias, either through the BW terminal 78 as shown in
The read operation of the memory cell 100 and array 120 will be described in conjunction with
A read operation for example can be performed on memory cell 100 by applying the following bias conditions. A positive voltage is applied to the WL2 terminal 72, which turns on the access transistor 42, a positive voltage is applied to the BL terminal 76, zero voltage is applied to the SL terminal 74, zero or positive voltage is applied to the BW terminal 78, and zero voltage is applied to the SUB terminal 80. Positive voltage may also be applied to the WL1 terminal 70 to further enhance the current flowing through the memory cell 100, from the BL terminal 76 to the SL terminal 74. If memory cell 100 is in a logic-1 state having holes in the floating body region 24, then a higher current will flow from the BL terminal 76 to the SL terminal 74 of the selected memory cell 100, compared to if memory cell 100 is in a logic-0 state having no holes in the floating body region 24. In one particular embodiment, +1.2 volts is applied to the WL1 terminal 70, WL2 terminal 72, BL terminal 76, BW terminal 78, 0.0 volts is applied to the SL terminal 74 and SUB terminal 80. In other embodiments, different voltages may be applied to the various terminals of memory cell 100 as a matter of design choice and the exemplary voltages described are not limiting in any way.
The access transistor 42 is used to assist the selection of the memory cell 100 during a read operation. Because the access transistor 42 of the unselected memory cells in different rows (e.g. memory cells 100c and 100d) are turned off, it will not pass the positive voltage applied to the BL terminal 76 to the drain region 18 of the floating body transistor 40. As a result, no current will flow through the floating body transistor 40 of the unselected memory cells in different rows.
The unselected memory cells in different columns (e.g. memory cells 100b and 100d) will not conduct current since zero bias is applied to both the BL terminal 76 and SL terminal 74.
In one particular non-limiting embodiment, about +1.2 volts is applied to the selected WL2 terminal 72, about −1.2 volts is applied to the selected WL1 terminal 70, about +1.2 volts is applied to the selected BL terminal 76, about +1.2 volts is applied to the selected BW terminal 78, and about 0.0 volts is applied to the SUB terminal 80.
The positive bias applied to the WL2 terminal 72 will turn on the access transistor 42, which will pass the positive bias applied to the BL terminal 76 to the drain region 18 of the floating body transistor 40. The positive bias now present on the drain region 18 of the floating body transistor 40, along with the negative voltage applied to the WL1 terminal 70 (connected to the gate 60), will create a strong electric field around the junction area of the drain region 18 in the proximity of the gate 60. The strong electric field bends the energy band sharply upward near the gate 60 and drain region 18 junction overlap region, causing electrons to tunnel from the valence band of the floating body region 24 to the conduction band of the drain region 18, leaving holes in the valence band of the floating body region 24. The electrons which tunnel across the energy band become the drain region 18 leakage current, while the holes are injected into floating body region 24 and become the hole charge that creates the logic-1 state.
In one particular non-limiting embodiment, about +1.2 volts is applied to the selected WL2 terminal 72, about +0.5 volts is applied to the selected WL1 terminal 70, about +1.2 volts is applied to the selected BL terminal 76, about +1.2 volts is applied to the selected BW terminal 78, and about 0.0 volts is applied to the SUB terminal 80. These voltage levels are exemplary only and may vary from embodiment to embodiment. Thus the exemplary embodiments, features, bias levels, etc., described are not limiting.
In one particular non-limiting embodiment, about 0.0 volts is applied to the WL2 terminal 72, the voltage applied to the WL1 terminal is increased from 0.0 volts to about +1.2, about +1.2 volts is applied to the SL terminal 74, about +1.2 volts is applied to the BL terminal 76, about +1.2 volts is applied to the BW terminal 78, and about 0.0 volts is applied to the SUB terminal 80. These voltage levels are exemplary only and may vary from embodiment to embodiment. Thus the exemplary embodiments, features, bias levels, etc., described are not limiting.
The ramp rate of the positive bias applied to the WL1 terminal 70 (connected to gate electrode 60) may be optimized to increase the coupling ratio from the gate 60 to the floating body region 24. As described for example in “Substrate Response of a Floating Gate n-channel MOS Memory Cell Subject to a Positive Linear Ramp Voltage”, H.-S. Lee and D. S. Lowrie, Solid-State Electronics 24, no. 3, pp. 267-273, 1981, which is hereby incorporated herein, in its entirety, by reference thereto, a higher coupling from the gate 60 to the floating body region 24 can be achieved with a higher ramp rate. The ramp rate applied to the gate 60 may also be higher in the write logic-1 operation than in other operations, such as read operation, to further improve the write logic-1 operation time.
In one particular non-limiting embodiment, about −1.2 volts is applied to the selected SL terminal 74, about 0.0 volts is applied to the WL1 terminal 70, WL2 terminal 72, BL terminal 76, and SUB terminal 80, and about +1.2 volts is applied to the BW terminal 78. These voltage levels are exemplary only and may vary from embodiment to embodiment. Thus the exemplary embodiments, features, bias levels, etc., described are not limiting.
In one particular non-limiting embodiment, about +1.2 volts is applied to the WL2 terminal 72, about +1.2 volts is applied to the WL1 terminal 70, about 0.0 volts is applied to the SL terminal 74, about −0.2 volts is applied to the BL terminal 76, about +1.2 volts is applied to the BW terminal 78, and about 0.0 volts is applied to the SUB terminal 80. These voltage levels are exemplary only and may vary from embodiment to embodiment. Thus the exemplary embodiments, features, bias levels, etc., described are not limiting.
An active low scheme—where the selected BL terminal 74 is biased at low voltage, for example zero voltage—can also be performed on memory cell 100 and memory array 120.
Exemplary bias conditions for an active low read operation according to an embodiment of the present invention are illustrated in
In one particular non-limiting embodiment, the following conditions are applied to the selected terminals: about +1.2 volts is applied to the WL2 terminal 72, about +1.2 volts is applied to the WL1 terminal 70, about +1.2 volts is applied to the SL terminal 74, about 0.0 volts is applied to the BL terminal 76, about 0.0 volts is applied to the BW terminal 78, and about 0.0 volts is applied to the SUB terminal 80; while the following bias conditions are applied to the unselected terminals: about 0.0 volts is applied to the WL1 terminal 70, WL2 terminal 72, about 0.0 volts is applied to the SL terminal 74, about +1.2 volts is applied to the BL terminal 76, about +1.2 volts is applied to the BW terminal 78, and about 0.0 volts is applied to the SUB terminal 80. These voltage levels are exemplary only and may vary from embodiment to embodiment. Thus the exemplary embodiments, features, bias levels, etc., described are not limiting.
In one particular non-limiting embodiment, the following conditions are applied to the selected terminals: about +1.2 volts is applied to the WL2 terminal 72, about +0.5 volts is applied to the WL1 terminal 70, about +1.2 volts is applied to the SL terminal 74, about 0.0 volts is applied to the BL terminal 76, about 0.0 volts is applied to the BW terminal 78, and about 0.0 volts is applied to the SUB terminal 80; while the following bias conditions are applied to the unselected terminals: about 0.0 volts is applied to the WL1 terminal 70, WL2 terminal 72, about 0.0 volts is applied to the SL terminal 74, about +1.2 volts is applied to the BL terminal 76, about +1.2 volts is applied to the BW terminal 78, and about 0.0 volts is applied to the SUB terminal 80. These voltage levels are exemplary only and may vary from embodiment to embodiment. Thus the exemplary embodiments, features, bias levels, etc., described are not limiting.
Memory cell 102 includes gates 60 on two opposite sides of the floating substrate region 24 of the floating body transistor 40 and gates 64 on two opposite sides of the well region 12 of the access transistor 42, see
Memory cells 102 and 104 comprise source line (SL) terminal 74 connected to the source line region 16, bit line (BL) terminal 76 connected to the bit line region 22, word line 1 (WL1) terminal 70, which is electrically connected to the gate 60 of the floating body transistor 40, word line 2 (WL2) terminal 72, which is electrically connected to the gate 64 of the access transistor 42, buried well (BW) terminal 78, which is electrically connected to the buried well region 30 of the floating body transistor 40, and substrate (SUB) terminal 80, which is connected to the substrate region 10.
Memory cells 100, 102, and 104 each have two transistors having the same conductivity type in series (two n-channel transistors 40 and 42 are used in the examples).
Also inherent in floating body transistor 40 is bipolar device 48, formed by the source line region 16, floating body region 24, and the drain region 18. For drawings clarity, bipolar device 48 is shown separately in
Several operations can be performed on memory cell 200, such as: holding, read, write logic-1 and write logic-0 operations.
In one embodiment the bias conditions for the holding operation for memory cell 200 are: 0.0 volts is applied to WL1 terminal 70, WL2 terminal 72, SL terminal 74, BL terminal 76, and SUB terminal 78, and a positive voltage like, for example, +1.2 volts is applied to BW terminal 78. In other embodiments, different voltages may be applied to the various terminals of memory cell 200 as a matter of design choice and the exemplary voltages described are not limiting in any way.
In one embodiment, the following bias conditions are applied for the alternative holding operation: 0.0 volts is applied to WL1 terminal 70, WL2 terminal 72, SL2 terminal 74, BL terminal 76, a positive voltage like, for example, +1.2 volts is applied to SUB terminal 80, while the BW terminal 78 is left floating. In other embodiments, different voltages may be applied to the various terminals of memory cell 200 as a matter of design choice and the exemplary voltages described are not limiting in any way. Alternatively, the BW terminal 78 may be eliminated from the array 220, leaving the buried well region 30 floating.
The read operation for example can be performed on memory cell 200 by applying the following bias conditions: zero voltage is applied to the WL2 terminal 72, which turns on the access transistor 42, a positive voltage is applied to the BL terminal 76, zero voltage is applied to the SL terminal 74, zero or positive voltage is applied to the BW terminal 78, and zero voltage is applied to the SUB terminal 80. Positive voltage may also be applied to the WL1 terminal 70 to further enhance the current flowing through the memory cell 200, from the BL terminal 76 to the SL terminal 74. If memory cell 200 is in a logic-1 state having holes in the floating body region 24, then a higher current will flow from the BL terminal 76 to the SL terminal 74 of the selected memory cell 200, compared to if memory cell 200 is in a logic-0 state having no holes in the floating body region 24. In one particular embodiment, +1.2 volts is applied to the WL1 terminal 70, BL terminal 76, BW terminal 78, 0.0 volts is applied to the WL2 terminal 72, SL terminal 74, and SUB terminal 80. In other embodiments, different voltages may be applied to the various terminals of memory cell 200 as a matter of design choice and the exemplary voltages described are not limiting in any way.
The access transistor 42 is used to assist the selection of the memory cell 200 during the read operation. Because the access transistor 42 of the unselected memory cells in different rows (e.g. memory cells 200c and 200d) are turned off (through the application of a positive voltage applied on WL2 terminal 72), it will not pass the positive voltage applied to the BL terminal 76 to the drain region 18 of the floating body transistor 40. As a result, no current will flow through the floating body transistor 40 of the unselected memory cells in different rows.
The unselected memory cells in different columns (e.g. memory cells 200b and 200d) will not conduct current since zero bias is applied to both the BL terminal 76 and SL terminal 74.
In one particular non-limiting embodiment, about 0.0 volts is applied to the selected WL2 terminal 72, about −1.2 volts is applied to the selected WL1 terminal 70, about +1.2 volts is applied to the selected BL terminal 76, about +1.2 volts is applied to the selected BW terminal 78, and about 0.0 volts is applied to the SUB terminal 80.
The zero voltage applied to the WL2 terminal 72 will turn on the p-type access transistor 42, which will pass the positive bias applied to the BL terminal 76 to the drain region 18 of the floating body transistor 40. The positive bias now present on the drain region 18 of the floating body transistor 40, along with the negative voltage applied to the WL1 terminal 70 (connected to the gate 60), will create a strong electric field around the junction area of the drain region 18 in the proximity of the gate 60. The strong electric field bends the energy band sharply upward near the gate and bit line junction overlap region, causing electrons to tunnel from the valence band to the conduction band, leaving holes in the valence band. The electrons which tunnel across the energy band become the drain leakage current, while the holes are injected into floating body region 24 and become the hole charge that creates the logic-1 state.
In one particular non-limiting embodiment, about 0.0 volts is applied to the selected WL2 terminal 72, about +0.5 volts is applied to the selected WL1 terminal 70, about +1.2 volts is applied to the selected BL terminal 76, about +1.2 volts is applied to the selected BW terminal 78, and about 0.0 volts is applied to the SUB terminal 80. These voltage levels are exemplary only may vary from embodiment to embodiment. Thus the exemplary embodiments, features, bias levels, etc., described are not limiting.
In one particular non-limiting embodiment, about +1.2 volts is applied to the WL2 terminal 72, the voltage applied to the WL1 terminal is increased from 0.0 volts to about +1.2, about +1.2 volts is applied to the SL terminal 74, about +1.2 volts is applied to the BL terminal 76, about +1.2 volts is applied to the BW terminal 78, and about 0.0 volts is applied to the SUB terminal 80. These voltage levels are exemplary only may vary from embodiment to embodiment. Thus the exemplary embodiments, features, bias levels, etc., described are not limiting.
In one particular non-limiting embodiment, about −1.2 volts is applied to the selected SL terminal 74, about 0.0 volts is applied to the WL1 terminal 70, BL terminal 76, and SUB terminal 80, about +1.2 volts is applied to the WL2 terminal 72, and about +1.2 volts is applied to the BW terminal 78. These voltage levels are exemplary only may vary from embodiment to embodiment. Thus the exemplary embodiments, features, bias levels, etc., described are not limiting.
In one particular non-limiting embodiment, about −1.2 volts is applied to the WL2 terminal 72, about +1.2 volts is applied to the WL1 terminal 70, about 0.0 volts is applied to the SL terminal 74, about −0.2 volts is applied to the BL terminal 76, about +1.2 volts is applied to the BW terminal 78, and about 0.0 volts is applied to the SUB terminal 80. These voltage levels are exemplary only may vary from embodiment to embodiment. Thus the exemplary embodiments, features, bias levels, etc., described are not limiting.
A reference cell may be used in the sensing operation of the memory cells 100 and 200 described above. The properties (e.g. cell current) of the reference cell can be used to compare the properties of the memory cell being sensed to determine its logic state.
Reference cell 100R1 comprises a sense line region 32 having the same conductivity type as the floating body region 24, which allows for an electrical connection to the floating body region 24 of the floating body transistor 40. The sense line region 32 is located in the same plane as the source and drain regions 16, 18, 20, and 22 of the floating body transistor 40 and the access transistor 42. The sense line region 32 can be connected to sense line terminal 82 as shown in
Floating body transistor 340 also comprises a buried layer region 330 of a second conductivity type, such as n-type, for example; a floating body region 324 of the first conductivity type, such as p-type, for example; and source or drain region 316 of the second conductivity type, such as n-type, for example; and sense line region 318 of the first conductivity type (same conductivity type as that of floating body region 324), such as p-type, for example.
Buried layer 330 may be formed by an ion implantation process on the material of substrate 310. Alternatively, buried layer 330 can be grown epitaxially on top of substrate 310.
The floating body region 324 of the first conductivity is bounded on top by surface 314, source line region 316, sense line region 318, and insulating layer 362, on the sides by insulating layer 326, and on the bottom by buried layer 330. Floating body 324 may be the portion of the original substrate 310 above buried layer 330 if buried layer 330 is implanted. Alternatively, floating body 324 may be epitaxially grown. Depending on how buried layer 330 and floating body 324 are formed, floating body 324 may have the same doping as substrate 310 in some embodiments or a different doping, if desired in other embodiments.
A gate 360 is positioned in between the source line region 316 and the sense region 318, above the floating body region 324. The gate 360 is insulated from the floating body region 324 by an insulating layer 362. Insulating layer 362 may be made of silicon oxide and/or other dielectric materials, including high-K dielectric materials, such as, but not limited to, tantalum peroxide, titanium oxide, zirconium oxide, hafnium oxide, and/or aluminum oxide. The gate 360 may be made of, for example, polysilicon material or metal gate electrode, such as tungsten, tantalum, titanium and their nitrides.
Insulating layers 326 (like, for example, shallow trench isolation (STI)), may be made of silicon oxide, for example, though other insulating materials may be used. Insulating layers 326 insulate floating body transistor 340 from adjacent floating body transistor 340 and adjacent access transistor 342. The bottom of insulating layer 326 may reside inside the buried region 330 allowing buried region 330 to be continuous as shown in
Access transistor 342 comprises a well region 312 of the first conductivity type, such as p-type, source region 320 and bit line region 322 of the second conductivity type, such as n-type. The well region 312 of the first conductivity type is electrically connected to the substrate region 310, and is therefore not floating. A floating gate 364 is positioned in between the source region 320 and the bit line region 322. The floating gate 364 is insulated from the well region 312 by an insulating layer 366 and is not connected to any terminals. The floating gate 364 is connected to the sense line region 318, which in turn is connected to the floating body region 324.
Insulating layer 366 may be made of silicon oxide and/or other dielectric materials, including high-K dielectric materials, such as, but not limited to, tantalum peroxide, titanium oxide, zirconium oxide, hafnium oxide, and/or aluminum oxide. The gate 364 may be made of, for example, polysilicon material or metal gate electrode, such as tungsten, tantalum, titanium and their nitrides.
The sense line region 318 of the floating body transistor 340 is connected to the floating gate 364 of the access transistor 342 through a conductive element 98. Conductive element 90 connects the source/drain region 316 of the floating body transistor 340 (which may be referred to as the source/drain region 316 of the memory device 300 interchangeably) to the bit line 1 (BL1) terminal 374, the conductive element 92 connects the bit line region 322 of the access transistor (which may be referred to as the bit line region 322 of the memory device 300 interchangeably) to the bit line 2 (BL2) terminal 376, while the conductive element 94 connects the source region 320 of the access transistor 342 to the source line (SL) terminal. The conductive elements 90, 92, 94, and 98 may be formed of, but are not limited to, tungsten or silicided silicon.
In addition to the SL terminal 372, BL1 terminal 374 and BL2 terminal 376, memory cell 300 also includes word line (WL) terminal 370, which is electrically connected to the gate 360 of the floating body transistor 340, buried well (BW) terminal 378, which is electrically connected to the buried well region 330 of the floating body transistor 340, and substrate (SUB) terminal 380, which is connected to the substrate region 310.
Present in
Similarly, other terminals may be segmented or buffered, while control circuits such as word decoders, column decoders, segmentation devices, sense amplifiers, write amplifiers, etc. may be arrayed around array 320 or inserted between sub-arrays of array 320. Thus the exemplary embodiments, features, design options, etc., described are not limiting in any way.
Lu et al. describes a two-transistor floating-body gate DRAM cell in “A Novel Two-Transistor Floating-Body/Gate Cell for Low-Power Nanoscale Embedded DRAM”, Z. Lu et al., pp. 1511-1518, IEEE Transactions on Electron Devices, vol. 55, no. 6, June 2008 (“Lu-1”) and “A Simplified Superior Floating-Body/Gate DRAM Cell”, Z. Lu et al., pp. 282-284, IEEE Electron Device Letters, vol. 30, no. 3, March 2009 (“Lu-2”), which are hereby incorporated herein, in their entireties, by reference thereto.
The two-transistor memory cell described in Lu-1 and Lu-2 utilizes the floating body region as the charge storage region and operates similar to capacitor-less DRAMs as described in Okhonin-1 and Ohsawa-1. As a result, the two-transistor memory cell described by Lu-1 and Lu-2 has a limited data retention time, and requires a refresh operation.
The floating body transistor 340 in memory cell 300 is a bi-stable memory cell, where the two stable states are obtained through the application of a positive bias to the back-bias region 330 (connected to terminal 378), following similar principles as those of memory cells 100 and 200. The state of the floating body transistor 340 can be sensed through the properties of the access transistor 342, for example the cell current flowing from the BL2 terminal 376 to the SL terminal 372 of the access transistor 342. A positively charged floating body region 324 (i.e. logic-1 state) will turn on the access transistor 342, and as a result, the access transistor 342 will conduct a higher current compared to if the floating body region 324 is neutral (or low positive charge) state (i.e. logic-0 state).
In one particular non-limiting embodiment, the following bias conditions are applied to the selected terminals: about 0.0 volts is applied to the WL terminal 370, about 0.0 volts is applied to the SL terminal 372, about 0.0 volts is applied to the BL1 terminal 374, about +0.4 volts is applied to the BL2 terminal 376, about +1.2 volts is applied to the BW terminal 378, and about 0.0 volts is applied to the SUB terminal 380; while the following bias conditions are applied to the unselected terminals: about 0.0 volts is applied to the WL terminal 370, about +0.4 volts is applied to the SL terminal 372, about 0.0 volts is applied to the BL1 terminal 374, about 0.0 volts is applied to the BL terminal 376, about +1.2 volts is applied to the BW terminal 378, and about 0.0 volts is applied to the SUB terminal 380. These voltage levels are exemplary only may vary from embodiment to embodiment. Thus the exemplary embodiments, features, bias levels, etc., described are not limiting.
The writing operations of the floating body transistor 340 are similar to the operations of “half transistor memory cell” described by Y. Widjaja and Z. Or-Bach, for example in U.S. application Ser. No. 12/897,516, “A Semiconductor Memory Device Having an Electrically Floating Body Transistor” and U.S. application Ser. No. 12/897,538, “A Semiconductor Memory Device Having an Electrically Floating Body Transistor”, which are hereby incorporated herein, in their entireties, by reference thereto.
In one particular non-limiting embodiment, the following bias conditions are applied to the selected terminals: about −1.2 volts is applied to the WL terminal 370, about 0.0 volts is applied to the SL terminal 372, about +1.2 volts is applied to the BL1 terminal 374, about 0.0 volts is applied to the BL2 terminal 376, about +1.2 volts is applied to the BW terminal 378, and about 0.0 volts is applied to the SUB terminal 380; while the following bias conditions are applied to the unselected terminals: about 0.0 volts is applied to the WL terminal 370, about 0.0 volts is applied to the SL terminal 372, about 0.0 volts is applied to the BL1 terminal 374, about 0.0 volts is applied to the BL terminal 376, about +1.2 volts is applied to the BW terminal 378, and about 0.0 volts is applied to the SUB terminal 380. These voltage levels are exemplary only may vary from embodiment to embodiment. Thus the exemplary embodiments, features, bias levels, etc., described are not limiting.
In one particular non-limiting embodiment, the following bias conditions are applied to the selected terminals: about +1.2 volts is applied to the WL terminal 370, about 0.0 volts is applied to the SL terminal 372, about −0.2 volts is applied to the BL1 terminal 374, about 0.0 volts is applied to the BL2 terminal 376, about +1.2 volts is applied to the BW terminal 378, and about 0.0 volts is applied to the SUB terminal 380; while the following bias conditions are applied to the unselected terminals: about 0.0 volts is applied to the WL terminal 370, about 0.0 volts is applied to the SL terminal 372, about 0.0 volts is applied to the BL1 terminal 374, about 0.0 volts is applied to the BL terminal 376, about +1.2 volts is applied to the BW terminal 378, and about 0.0 volts is applied to the SUB terminal 380. These voltage levels are exemplary only may vary from embodiment to embodiment. Thus the exemplary embodiments, features, bias levels, etc., described are not limiting.
Memory cell 500 further includes a word line #1A (WL1A) terminal 70A electrically connected to gate 60A, a word line #1B (WL1B) terminal 70B electrically connected to gate 60B, a word line #2A (WL2A) 72A electrically connected to gate 64A, a word line #2B (WL2B) 72B electrically connected to gate 64B, a source line (SL) terminal 74 electrically connected to region 16, a bit line #1 (BL1) terminal 76A electrically connected to the region 22A, a bit line #2 (BL2) terminal 76B electrically connected to the region 22B, a buried well (BW) terminal 78, which is electrically connected to the buried well region 30 of the dual-port floating body transistor 40D, and substrate (SUB) terminal 80, which is connected to the substrate region 10. WL1A terminal 70A, WL2A terminal 72A, and BL1 terminal 76A also may be referred to as ‘port #1’, while WL1B terminal 70B, WL2B terminal 72B, and BL2 terminal 76B also may be referred to as ‘port #2’.
The dual-port floating body transistor 40D is connected in series to the access transistors 42A and 42B. The drain region 18A of the floating body transistor 40D is connected to the source region 20A of the access transistor 42A of the port #1 through a conductive element 94A. Similarly, the drain region 18B of the floating body transistor 40D is connected to the source region 20B of the access transistor 42B of the port #2 through conductive element 94B.
Access to the memory cell 500, i.e. read and write operations to the memory cell 500, may be performed independently by port #1 and/or port #2 irrespective of timing.
As described in Widjaja-5, a multi-port floating body transistor may also be formed in place of the dual-port floating body transistor 40D by forming additional source or drain regions and positioning an additional gate(s) above the surface and in between the source and drain regions. For an n-port memory cell, the number of gates and the number of bit lines of the floating body transistor are equal to n, while the number of regions of the second conductivity type (i.e. the source or drain regions) of the floating body transistor is equal to (n+1). All regions of a second conductivity type and gates in a multi-port memory cell will be coupled to the same floating body region 24. Correspondingly, for an n-port memory cell, the number of access transistors is equal to n.
From the foregoing it can be seen that a memory cell comprising two transistors, for example a floating body transistor and an access transistor in series, a floating body transistor and a floating gate transistor, or two floating body transistors storing complementary charges, has been described. While the foregoing written description of the invention enables one of ordinary skill to make and use what is considered presently to be the best mode thereof, those of ordinary skill will understand and appreciate the existence of variations, combinations, and equivalents of the specific embodiment, method, and examples herein. The invention should therefore not be limited by the above described embodiment, method, and examples, but by all embodiments and methods within the scope and spirit of the invention as claimed.
While the present invention has been described with reference to the specific embodiments thereof, it should be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the invention. In addition, many modifications may be made to adapt a particular situation, material, composition of matter, process, process step or steps, to the objective, spirit and scope of the present invention. All such modifications are intended to be within the scope of the claims appended hereto.
This application is a division of co-pending U.S. application Ser. No. 15/485,718, filed Apr. 12, 2017, which is a division of U.S. application Ser. No. 14/380,779, filed Aug. 25, 2014, now U.S. Pat. No. 9,905,564, which claims the benefit under 35 USC 371(c) of PCT Application No. PCT/US2013/026466, filed 15 Feb. 2013, which claims the benefit of U.S. Provisional Application No. 61/599,425, filed Feb. 16, 2012, and U.S. Provisional Application No. 61/621,546, filed Apr. 8, 2012, and is a continuation-in-part of U.S. application Ser. No. 13/746,523, filed Jan. 22, 2013, now U.S. Pat. No. 9,230,651, issued on Jan. 5, 2016, which applications and patents are each hereby incorporated herein, in their entireties, by reference thereto and to which applications we claim priority under 35 U.S.C. Sections 371, 119 and 120, respectively.
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| Number | Date | Country | |
|---|---|---|---|
| 20190131305 A1 | May 2019 | US |
| Number | Date | Country | |
|---|---|---|---|
| 61621546 | Apr 2012 | US | |
| 61599425 | Feb 2012 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 15485718 | Apr 2017 | US |
| Child | 16219359 | US | |
| Parent | 14380779 | US | |
| Child | 15485718 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 13746523 | Jan 2013 | US |
| Child | 14380779 | US |
