Memory cell, memory with a memory cell, and method for writing data in a memory cell

Abstract

A memory cell having a programmable solid state electrolyte layer, a writing line and a controllable switch that is arranged between the solid state electrolyte layer and the writing line. The controllable switch has a control input that is connected with a selecting line and the switch also has a limiting element that limits a current through the solid state electrolyte layer to a predetermined amount of electric charge for a write operation.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

So that the manner in which the above recited features of the present invention can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments.

A more complete understanding of the present invention may be derived by referring to the detailed description and claims, considering in connection with the Figures, wherein like reference numbers refer to similar elements throughout the Figures, and:

FIG. 1 depicts a programmable solid state electrolyte layer;

FIG. 2 depicts a schematic diagram of current and bias voltage for writing and erasing a data and the programmable solid state electrolyte layer;

FIG. 3 depicts a partial view of a memory with a memory element;

FIG. 4 depicts a detailed view of the memory element and a writing and erasing circuit;

FIG. 5 depicts a diagram of threshold voltages of a bit line during a writing, erasing and writing operation;

FIG. 6 depicts threshold values of a word line and a current on the bit line is a function of a gate voltage before and after programming of the floating gate;

FIG. 7 depicts diagrams with voltages and currents for writing a data;

FIG. 8 depicts diagrams with voltages and currents for reading a data and

FIG. 9 depicts a field effect transistor with a floating gate.

Claims

1. A memory cell, comprising: a programmable solid state electrolyte layer configured to represent a logical state according to a resistance of the programmable solid state electrolyte layer;a writing line;a selecting line; anda controllable switch arranged between the solid state electrolyte layer and the writing line, and connected to the selecting line; wherein the controllable switch is controlled, at least in part, by application of a voltage on the selected line; wherein the switch comprises a limiting element that limits a current through the solid state electrolyte layer to a predetermined amount of electric charge for a write operation.

2. The memory cell of claim 1, wherein the programmable solid state electrolyte layer is connected to a potential source.

3. The memory cell of claim 1, further comprising a potential source providing a programming voltage to the writing line during the write operation.

4. The memory cell of claim 3, wherein the programming voltage is selected to be greater than an initial threshold voltage of the controllable switch and less than a maximum threshold voltage of the controllable switch.

5. The memory cell of claim 3, wherein the controllable switch has a threshold voltage which rises from an initial level to a terminal level during the write operation; and wherein the initial level is less than a programming voltage applied to the writing line and the terminal level is greater than the programming voltage applied to the writing line during the write operation, whereby the controllable switch is in a closed position while the threshold voltage is less than the programming voltage and changes from the closed position to an open position when the threshold voltage exceeds the programming voltage during the write operation.

6. A memory cell, comprising: a programmable solid state electrolyte layer connected with a potential source;a writing line;a selecting line,a transistor with a first source/drain terminal, a second source/drain terminal and a floating gate, the transistor being connected to the writing line by the first terminal and to the solid state electrolyte layer by the second terminal; wherein the floating gate of the transistor limits a current through the solid state electrolyte layer during a write operation of the solid state electrolyte layer to a predetermined amount of electric charge.

7. The memory cell of claim 6, further comprising an oxide layer between the floating gate and the solid state electrolyte layer with a thickness less than 4 nm.

8. The memory cell of claim 6, further comprising an oxide layer between the floating gate and the solid state electrolyte layer with a thickness smaller than 2 nm.

9. The memory cell of claim 6, wherein the floating gate has a starting voltage that increases over a control voltage applied to a gate terminal of the transistor after a predetermined amount of current is flowed through the solid state electrolyte layer.

10. The memory cell of claim 6, a potential source providing a programming voltage to the writing line during the write operation.

11. The memory cell of claim 10, wherein the programming voltage is selected to be greater than an initial threshold voltage of the transistor and less than a maximum threshold voltage of the transistor.

12. The memory cell of claim 10, wherein the transistor has a threshold voltage which changes during the write operation; and wherein transistor is in a closed position while the threshold voltage is less than the programming voltage and changes from the closed position to an open position when the threshold voltage exceeds the programming voltage during the write operation.

13. A memory, comprising: a row decoder;a column decoder;a plurality of bit lines connected to input/output drivers;a plurality of word lines; anda memory cell located at each intersection of the plurality of bit lines and plurality of word lines and selectable according to a row address provided to the row decoder and a column address provided to the column decoder; wherein each memory cell comprises: a programmable solid state electrolyte layer; anda controllable switch, comprising: a control input coupled to a word line of the plurality of word lines;a first terminal coupled to the solid state electrolyte layer;a second terminal coupled to a bit line of the plurality of bit lines;a limiting element that limits a current through the solid state electrolyte layer to a predetermined amount of electric charge for a write operation.

14. The memory cell of claim 13, wherein the programmable solid state electrolyte layer is connected to a potential source.

15. The memory cell of claim 13, further a potential source providing a programming voltage to the writing line during the write operation.

16. The memory cell of claim 13, wherein the programming voltage is selected to be greater than an initial threshold voltage of the controllable switch and less than a maximum threshold voltage of the controllable switch.

17. The memory cell of claim 13, wherein the controllable switch has a threshold voltage which rises from an initial level to a terminal level during the write operation; and wherein the initial level is less than a programming voltage applied to the writing line and the terminal level is greater than the programming voltage applied to the writing line during the write operation, whereby the controllable switch is in a closed position while the threshold voltage is less than the programming voltage and changes from the closed position to an open position when the threshold voltage exceeds the programming voltage during the write operation.

18. A memory, comprising: a row decoder;a column decoder;a plurality of bit lines connected to input/output drivers;a plurality of word lines; anda memory cell located at each intersection of the plurality of bit lines and plurality of word lines and selectable according to a row address provided to the row decoder and a column address provided to the column decoder; wherein each memory cell comprises: a programmable solid state electrolyte layer; anda transistor, comprising: a gate terminal connected with a word line of the plurality of word lines;a first terminal connected with the solid state electrolyte layer;a second terminal connected with a bit line of the plurality of bit lines; anda floating gate configured to limit a current through the solid state electrolyte layer to a predetermined amount of electric charge for a write operation.

19. The memory of claim 18, further comprising an oxide layer between the floating gate and the solid state electrolyte layer with a thickness less than 4 nm.

20. The memory of claim 18, further comprising an oxide layer between the floating gate and the solid state electrolyte layer with a thickness less than 2 nm.

21. A method for writing a data memory, comprising: applying a first voltage to a bit line during a write operation, the bit line being connected to a first terminal of a switch, wherein a second terminal of the switch is connected to a first electrode of a programmable structure and wherein a second electrode of the programmable structure is connected to a potential source, and wherein a solid state electrolyte layer is disposed between the first and second electrodes;applying a second voltage to a word line during the write operation, the word line being connected to a control terminal of the switch; wherein applying the second voltage to the word lines while maintaining the first voltage to the bit lines causes the switch to open, thereby allowing current flow through the solid state electrolyte layer which causes a resistance of the electrolyte layer to change; and wherein the switch is configured to close upon reaching a predefined voltage level relative to the second voltage during continued application of the first and second voltages.

22. The method of claim 21, wherein the switch comprises a field effect transistor and wherein the control terminal comprises a floating gate and a terminal gate connected to the word line, wherein during the write operation a potential of the floating gate is increased by charge injection until the potential of the floating gate exceeds the second voltage, causing the field effect transistor to open.